diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv
index de2ce351e..e4d5ded16 100644
--- a/pipelined/src/privileged/privileged.sv
+++ b/pipelined/src/privileged/privileged.sv
@@ -157,7 +157,7 @@ module privileged (
             .LoadAccessFaultM, .StoreAmoAccessFaultM, .EcallFaultM, .InstrPageFaultM,
             .LoadPageFaultM, .StoreAmoPageFaultM,
             .mretM, .sretM, 
-            .PrivilegeModeW, .NextPrivilegeModeM,
+            .PrivilegeModeW, 
             .MIP_REGW, .MIE_REGW, .MIDELEG_REGW,
             .STATUS_MIE, .STATUS_SIE,
             .InstrValidM, .CommittedM,  
diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv
index 4467ab6a7..f23efeba2 100644
--- a/pipelined/src/privileged/trap.sv
+++ b/pipelined/src/privileged/trap.sv
@@ -38,7 +38,7 @@ module trap (
   (* mark_debug = "true" *) input logic 		   LoadAccessFaultM, StoreAmoAccessFaultM, EcallFaultM, InstrPageFaultM,
   (* mark_debug = "true" *) input logic 		   LoadPageFaultM, StoreAmoPageFaultM,
   (* mark_debug = "true" *) input logic 		   mretM, sretM, 
-  input logic [1:0] 	   PrivilegeModeW, NextPrivilegeModeM,
+  input logic [1:0] 	   PrivilegeModeW, 
   (* mark_debug = "true" *) input logic [11:0] 	   MIP_REGW, MIE_REGW, MIDELEG_REGW,
   input logic 		   STATUS_MIE, STATUS_SIE,
   input logic 		   InstrValidM, CommittedM,