mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
add CSRs to waveview
This commit is contained in:
bbracker
parent
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commit
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@ -14,30 +14,30 @@ add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/StoreStallD
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add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/LSUStallM
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add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/LSUStallM
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add wave -noupdate -group HDU -group hazards /testbench/dut/core/MDUStallD
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add wave -noupdate -group HDU -group hazards /testbench/dut/core/MDUStallD
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add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/DivBusyE
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add wave -noupdate -group HDU -group hazards /testbench/dut/core/hzu/DivBusyE
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add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/InterruptM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM
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add wave -noupdate -group HDU -group traps /testbench/dut/core/priv/priv/trap/PendingInterruptM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/PendingInterruptM
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/hzu/FlushF
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/hzu/FlushF
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallF
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add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallF
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallD
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add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallD
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE
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add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallE
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM
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add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallM
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW
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add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallW
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add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
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add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/FinalInstrRawF
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/FinalInstrRawF
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
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@ -63,6 +63,24 @@ add wave -noupdate -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM
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add wave -noupdate -group {WriteBack stage} /testbench/PCW
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add wave -noupdate -group {WriteBack stage} /testbench/PCW
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add wave -noupdate -group {WriteBack stage} /testbench/InstrW
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add wave -noupdate -group {WriteBack stage} /testbench/InstrW
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add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
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add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTEREN_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MCOUNTINHIBIT_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEDELEG_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MEPC_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIDELEG_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIE_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MIP_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MSTATUS_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/MTVEC_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPADDR_ARRAY_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/PMPCFG_ARRAY_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SATP_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SCOUNTEREN_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SIE_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SIP_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW
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add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW
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add wave -noupdate -group Bpred -color Orange /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHR
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add wave -noupdate -group Bpred -color Orange /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHR
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add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
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add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
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add wave -noupdate -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
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add wave -noupdate -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
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@ -351,8 +369,6 @@ add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SU
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add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWReadPTE
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add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWReadPTE
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add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWAdr
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add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWAdr
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add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PTE
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add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/PTE
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add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBMissF
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add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBMissM
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add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBWriteF
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add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/ITLBWriteF
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add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBWriteM
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add wave -noupdate -group lsu -group ptwalker -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/DTLBWriteM
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add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HCLK
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add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HCLK
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@ -454,7 +470,6 @@ add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW
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add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PCNext2F
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add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PCNext2F
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add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PrivilegedNextPCM
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add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PrivilegedNextPCM
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add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PrivilegedChangePCM
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add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PrivilegedChangePCM
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add wave -noupdate /testbench/dut/core/priv/priv/csr/MEPC_REGW
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add wave -noupdate -group ifu -color Gold /testbench/dut/core/lsu/bus/busdp/busfsm/BusCurrState
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add wave -noupdate -group ifu -color Gold /testbench/dut/core/lsu/bus/busdp/busfsm/BusCurrState
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add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusRead
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add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusRead
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add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusAdr
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add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUBusAdr
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@ -493,7 +508,6 @@ add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {I
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add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
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add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
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add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]}
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add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]}
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add wave -noupdate /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/NextPTE
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add wave -noupdate /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/NextPTE
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add wave -noupdate /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/HPTWWrite
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add wave -noupdate /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/UpdatePTE
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add wave -noupdate /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/hptw/UpdatePTE
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TreeUpdate [SetDefaultTree]
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 5} {0 ns} 0}
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WaveRestoreCursors {{Cursor 5} {0 ns} 0}
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@ -512,4 +526,4 @@ configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timeline 0
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configure wave -timelineunits ns
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configure wave -timelineunits ns
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update
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update
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WaveRestoreZoom {0 ns} {224 ns}
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WaveRestoreZoom {0 ns} {496 ns}
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