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Simplified Access fault logic in HPTW
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@ -93,15 +93,17 @@ module hptw (
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logic [`XLEN+1:0] HPTWAdrExt;
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logic [`XLEN+1:0] HPTWAdrExt;
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logic ITLBMissOrDAFaultF;
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logic ITLBMissOrDAFaultF;
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logic DTLBMissOrDAFaultM;
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logic DTLBMissOrDAFaultM;
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logic LSUAccessFaultM;
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logic [`PA_BITS-1:0] HPTWAdr;
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logic [`PA_BITS-1:0] HPTWAdr;
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logic [1:0] HPTWRW;
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logic [1:0] HPTWRW;
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logic [2:0] HPTWSize; // 32 or 64 bit access
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logic [2:0] HPTWSize; // 32 or 64 bit access
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statetype WalkerState, NextWalkerState, InitialWalkerState;
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statetype WalkerState, NextWalkerState, InitialWalkerState;
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// map hptw access faults onto either the original LSU load/store fault or instruction access fault
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// map hptw access faults onto either the original LSU load/store fault or instruction access fault
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assign LoadAccessFaultM = WalkerState == IDLE ? LSULoadAccessFaultM : (LSULoadAccessFaultM | LSUStoreAmoAccessFaultM) & DTLBWalk & MemRWM[1] & ~MemRWM[0];
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assign LSUAccessFault = LSULoadAccessFaultM | LSUStoreAmoAccessFaultM;
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assign StoreAmoAccessFaultM = WalkerState == IDLE ? LSUStoreAmoAccessFaultM : (LSULoadAccessFaultM | LSUStoreAmoAccessFaultM) & DTLBWalk & MemRWM[0];
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assign LoadAccessFaultM = WalkerState == IDLE ? LSULoadAccessFaultM : LSUAccessFaultM & DTLBWalk & MemRWM[1] & ~MemRWM[0];
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assign HPTWInstrAccessFaultM = WalkerState == IDLE ? 1'b0: (LSUStoreAmoAccessFaultM | LSULoadAccessFaultM) & ~DTLBWalk;
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assign StoreAmoAccessFaultM = WalkerState == IDLE ? LSUStoreAmoAccessFaultM : LSUAccessFaultM & DTLBWalk & MemRWM[0];
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assign HPTWInstrAccessFaultM = WalkerState == IDLE ? 1'b0: LSUAccessFaultM & ~DTLBWalk;
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// Extract bits from CSRs and inputs
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// Extract bits from CSRs and inputs
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assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
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assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
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