mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Lee Moore
GitHub
commit
e96f0fc7ad
@ -25,7 +25,8 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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`include "config.vh"
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// This is set from the command line script
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// `define USE_IMPERAS_DV
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@ -34,6 +35,8 @@
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`include "rvvi/imperasDV.svh"
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`endif
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import cvw::*;
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module testbench;
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parameter DEBUG=0;
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@ -43,21 +46,23 @@ module testbench;
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import idvApiPkg::*;
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`endif
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`include "parameter-defs.vh"
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logic clk;
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logic reset_ext, reset;
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logic [`XLEN-1:0] testadr, testadrNoBase;
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logic [P.XLEN-1:0] testadr, testadrNoBase;
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string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
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logic [31:0] InstrW;
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logic [3:0] dummy;
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logic [`AHBW-1:0] HRDATAEXT;
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logic [P.AHBW-1:0] HRDATAEXT;
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logic HREADYEXT, HRESPEXT;
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logic [`PA_BITS-1:0] HADDR;
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logic [`AHBW-1:0] HWDATA;
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logic [`XLEN/8-1:0] HWSTRB;
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logic [P.PA_BITS-1:0] HADDR;
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logic [P.AHBW-1:0] HWDATA;
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logic [P.XLEN/8-1:0] HWSTRB;
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logic HWRITE;
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logic [2:0] HSIZE;
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logic [2:0] HBURST;
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@ -65,7 +70,7 @@ module testbench;
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logic [1:0] HTRANS;
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logic HMASTLOCK;
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logic HCLK, HRESETn;
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logic [`XLEN-1:0] PCW;
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logic [P.XLEN-1:0] PCW;
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string ProgramAddrMapFile, ProgramLabelMapFile;
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integer ProgramAddrLabelArray [string] = '{ "begin_signature" : 0, "tohost" : 0 };
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@ -108,7 +113,7 @@ module testbench;
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$error("Must specify test directory using plusarg testDir");
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end
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if (`BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
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if (P.BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
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else $error("Imperas test bench requires BUS.");
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ProgramAddrMapFile = {testDir, "/ref/ref.elf.objdump.addr"};
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@ -123,8 +128,8 @@ module testbench;
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`ifdef USE_IMPERAS_DV
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rvviTrace #(.XLEN(`XLEN), .FLEN(`FLEN)) rvvi();
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wallyTracer wallyTracer(rvvi);
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rvviTrace #(.XLEN(P.XLEN), .FLEN(P.FLEN)) rvvi();
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wallyTracer #(P) wallyTracer(rvvi);
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trace2log idv_trace2log(rvvi);
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trace2cov idv_trace2cov(rvvi);
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@ -171,23 +176,23 @@ module testbench;
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// Privileges for PMA are set in the imperas.ic
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// volatile (IO) regions are defined here
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// only real ROM/RAM areas are BOOTROM and UNCORE_RAM
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if (`CLINT_SUPPORTED) begin
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void'(rvviRefMemorySetVolatile(`CLINT_BASE, (`CLINT_BASE + `CLINT_RANGE)));
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if (P.CLINT_SUPPORTED) begin
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void'(rvviRefMemorySetVolatile(P.CLINT_BASE, (P.CLINT_BASE + P.CLINT_RANGE)));
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end
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if (`GPIO_SUPPORTED) begin
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void'(rvviRefMemorySetVolatile(`GPIO_BASE, (`GPIO_BASE + `GPIO_RANGE)));
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if (P.GPIO_SUPPORTED) begin
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void'(rvviRefMemorySetVolatile(P.GPIO_BASE, (P.GPIO_BASE + P.GPIO_RANGE)));
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end
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if (`UART_SUPPORTED) begin
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void'(rvviRefMemorySetVolatile(`UART_BASE, (`UART_BASE + `UART_RANGE)));
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if (P.UART_SUPPORTED) begin
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void'(rvviRefMemorySetVolatile(P.UART_BASE, (P.UART_BASE + P.UART_RANGE)));
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end
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if (`PLIC_SUPPORTED) begin
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void'(rvviRefMemorySetVolatile(`PLIC_BASE, (`PLIC_BASE + `PLIC_RANGE)));
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if (P.PLIC_SUPPORTED) begin
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void'(rvviRefMemorySetVolatile(P.PLIC_BASE, (P.PLIC_BASE + P.PLIC_RANGE)));
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end
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if (`SDC_SUPPORTED) begin
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void'(rvviRefMemorySetVolatile(`SDC_BASE, (`SDC_BASE + `SDC_RANGE)));
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if (P.SDC_SUPPORTED) begin
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void'(rvviRefMemorySetVolatile(P.SDC_BASE, (P.SDC_BASE + P.SDC_RANGE)));
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end
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if(`XLEN==32) begin
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if(P.XLEN==32) begin
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void'(rvviRefCsrSetVolatile(0, 32'hC80)); // CYCLEH
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void'(rvviRefCsrSetVolatile(0, 32'hB80)); // MCYCLEH
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void'(rvviRefCsrSetVolatile(0, 32'hC82)); // INSTRETH
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@ -211,19 +216,19 @@ module testbench;
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`endif
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flopenr #(`XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW);
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flopenr #(P.XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW);
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flopenr #(32) InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.InstrM, InstrW);
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// check assertions for a legal configuration
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riscvassertions riscvassertions();
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riscvassertions #(P) riscvassertions();
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// instantiate device to be tested
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assign GPIOIN = 0;
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assign UARTSin = 1;
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if(`EXT_MEM_SUPPORTED) begin
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ram_ahb #(.BASE(`EXT_MEM_BASE), .RANGE(`EXT_MEM_RANGE))
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if(P.EXT_MEM_SUPPORTED) begin
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ram_ahb #(.BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE))
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ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT),
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.HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY,
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.HWSTRB);
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@ -233,7 +238,7 @@ module testbench;
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assign HRDATAEXT = 0;
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end
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if(`FPGA) begin : sdcard
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if(P.FPGA) begin : sdcard
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sdModel sdcard
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(.sdClk(SDCCLK),
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.cmd(SDCCmd),
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@ -247,7 +252,7 @@ module testbench;
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assign SDCDat = '0;
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end
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wallypipelinedsoc dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
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wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
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.HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
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.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
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.UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK);
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@ -287,7 +292,7 @@ module testbench;
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// track the current function or global label
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if (DEBUG == 1) begin : FunctionName
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FunctionName FunctionName(.reset(reset),
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FunctionName #(P) FunctionName(.reset(reset),
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.clk(clk),
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.ProgramAddrMapFile(ProgramAddrMapFile),
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.ProgramLabelMapFile(ProgramLabelMapFile));
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@ -299,7 +304,7 @@ module testbench;
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// or sd gp, -56(t0)
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// or on a jump to self infinite loop (6f) for RISC-V Arch tests
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logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls
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if (`ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM;
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if (P.ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM;
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else assign ecf = 0;
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assign DCacheFlushStart = ecf &
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(dut.core.ieu.dp.regf.rf[3] == 1 |
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@ -309,13 +314,13 @@ module testbench;
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((dut.core.ifu.InstrM == 32'h6f | dut.core.ifu.InstrM == 32'hfc32a423 | dut.core.ifu.InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM ) |
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((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" );
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DCacheFlushFSM DCacheFlushFSM(.clk(clk),
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DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk),
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.reset(reset),
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.start(DCacheFlushStart),
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.done(DCacheFlushDone));
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// initialize the branch predictor
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if (`BPRED_SUPPORTED == 1)
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if (P.BPRED_SUPPORTED == 1)
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begin
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genvar adrindex;
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@ -331,24 +336,7 @@ module testbench;
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end
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end
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// check for hange up.
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logic [`XLEN-1:0] OldPCW;
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integer WatchDogTimerCount;
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localparam WatchDogTimerThreshold = 1000000;
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logic WatchDogTimeOut;
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always_ff @(posedge clk) begin
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OldPCW <= PCW;
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if(OldPCW == PCW) WatchDogTimerCount = WatchDogTimerCount + 1'b1;
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else WatchDogTimerCount = '0;
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end
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always_comb begin
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WatchDogTimeOut = WatchDogTimerCount >= WatchDogTimerThreshold;
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if(WatchDogTimeOut) begin
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$display("FAILURE: Watch Dog Time Out triggered. PCW stuck at %x for more than %d cycles", PCW, WatchDogTimerCount);
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$stop;
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end
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end
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watchdog #(P.XLEN, 1000000) watchdog(.clk, .reset); // check if PCW is stuck
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endmodule
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@ -356,120 +344,6 @@ endmodule
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/* verilator lint_on STMTDLY */
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/* verilator lint_on WIDTH */
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module DCacheFlushFSM
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(input logic clk,
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input logic reset,
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input logic start,
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output logic done);
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genvar adr;
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logic [`XLEN-1:0] ShadowRAM[`UNCORE_RAM_BASE>>(1+`XLEN/32):(`UNCORE_RAM_RANGE+`UNCORE_RAM_BASE)>>1+(`XLEN/32)];
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if(`DCACHE_SUPPORTED) begin
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localparam integer numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES;
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localparam integer numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS;
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localparam integer linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN;
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localparam integer linelen = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN;
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localparam integer sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN;
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localparam integer cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM;
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//testbench.dut.core.lsu.bus.dcache.dcache.CacheWays.NUMSRAM;
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localparam integer numwords = sramlen/`XLEN;
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localparam integer lognumlines = $clog2(numlines);
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localparam integer loglinebytelen = $clog2(linebytelen);
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localparam integer lognumways = $clog2(numways);
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localparam integer tagstart = lognumlines + loglinebytelen;
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genvar index, way, cacheWord;
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logic [sramlen-1:0] CacheData [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
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logic [sramlen-1:0] cacheline;
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logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
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logic CacheValid [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
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logic CacheDirty [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
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logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
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for(index = 0; index < numlines; index++) begin
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for(way = 0; way < numways; way++) begin
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for(cacheWord = 0; cacheWord < cachesramwords; cacheWord++) begin
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copyShadow #(.tagstart(tagstart),
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.loglinebytelen(loglinebytelen), .sramlen(sramlen))
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copyShadow(.clk,
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.start,
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.tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][`PA_BITS-1-tagstart:0]),
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.valid(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]),
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.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].DirtyBits[index]),
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// these dirty bit selections would be needed if dirty is moved inside the tag array.
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//.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].dirty.DirtyMem.RAM[index]),
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//.dirty(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][`PA_BITS+tagstart]),
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.data(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].word[cacheWord].wordram.CacheDataMem.RAM[index]),
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.index(index),
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.cacheWord(cacheWord),
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.CacheData(CacheData[way][index][cacheWord]),
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.CacheAdr(CacheAdr[way][index][cacheWord]),
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.CacheTag(CacheTag[way][index][cacheWord]),
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.CacheValid(CacheValid[way][index][cacheWord]),
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.CacheDirty(CacheDirty[way][index][cacheWord]));
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end
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end
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end
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integer i, j, k, l;
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always @(posedge clk) begin
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if (start) begin #1
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#1
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for(i = 0; i < numlines; i++) begin
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for(j = 0; j < numways; j++) begin
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for(l = 0; l < cachesramwords; l++) begin
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if (CacheValid[j][i][l] & CacheDirty[j][i][l]) begin
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for(k = 0; k < numwords; k++) begin
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//cacheline = CacheData[j][i][0];
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// does not work with modelsim
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// # ** Error: ../testbench/testbench.sv(483): Range must be bounded by constant expressions.
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// see https://verificationacademy.com/forums/systemverilog/range-must-be-bounded-constant-expressions
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//ShadowRAM[CacheAdr[j][i][k] >> $clog2(`XLEN/8)] = cacheline[`XLEN*(k+1)-1:`XLEN*k];
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ShadowRAM[(CacheAdr[j][i][l] >> $clog2(`XLEN/8)) + k] = CacheData[j][i][l][`XLEN*k +: `XLEN];
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end
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end
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end
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end
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end
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end
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end
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end
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flop #(1) doneReg(.clk, .d(start), .q(done));
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endmodule
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module copyShadow
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#(parameter tagstart, loglinebytelen, sramlen)
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(input logic clk,
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input logic start,
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input logic [`PA_BITS-1:tagstart] tag,
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input logic valid, dirty,
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input logic [sramlen-1:0] data,
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input logic [32-1:0] index,
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input logic [32-1:0] cacheWord,
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output logic [sramlen-1:0] CacheData,
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output logic [`PA_BITS-1:0] CacheAdr,
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output logic [`XLEN-1:0] CacheTag,
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output logic CacheValid,
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output logic CacheDirty);
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always_ff @(posedge clk) begin
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if(start) begin
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CacheTag = tag;
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CacheValid = valid;
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CacheDirty = dirty;
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CacheData = data;
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CacheAdr = (tag << tagstart) + (index << loglinebytelen) + (cacheWord << $clog2(sramlen/8));
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end
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end
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endmodule
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task automatic updateProgramAddrLabelArray;
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input string ProgramAddrMapFile, ProgramLabelMapFile;
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