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	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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							| @ -0,0 +1,26 @@ | |||||||
|  | make all: submodules other | ||||||
|  | submodules: addins/riscv-isa-sim addins/riscv-arch-test | ||||||
|  | 	cd addins;git init; git submodule add https://github.com/riscv-non-isa/riscv-arch-test; git submodule add https://github.com/riscv-software-src/riscv-isa-sim | ||||||
|  | 	git submodule update --init --recursive | ||||||
|  | 
 | ||||||
|  | other: | ||||||
|  | 	cp -r addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/I addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/F | ||||||
|  | 	cp -r addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/I addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/D | ||||||
|  | 	sed -i 's/--isa=rv32i /--isa=32if/' addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/F/Makefile.include | ||||||
|  | 	sed -i 's/--isa=rv32i /--isa=32if/' addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/D/Makefile.include | ||||||
|  | ifneq ("$(wildcard $(addins/riscv-isa-sim/build/.*))",) | ||||||
|  | else | ||||||
|  | 	mkdir addins/riscv-isa-sim/build | ||||||
|  | endif | ||||||
|  | 	cd addins/riscv-isa-sim/build; ../configure --prefix=/cad/riscv/gcc/bin | ||||||
|  | 	make -C addins/riscv-isa-sim/ | ||||||
|  | 	sed -i '/export TARGETDIR ?=/c\export TARGETDIR ?= /home/harris/riscv-wally/addins/riscv-isa-sim/arch_test_target' tests/wally-riscv-arch-test/Makefile.include | ||||||
|  | 	echo export RISCV_PREFIX = riscv64-unknown-elf- >> tests/wally-riscv-arch-test/Makefile.include | ||||||
|  | 	make -C tests/wally-riscv-arch-test | ||||||
|  | 	make -C tests/wally-riscv-arch-test XLEN=32 | ||||||
|  | 	cd tests/wally-riscv-arch-test; exe2memfile.pl work/*/*/*.elf | ||||||
|  | 	make -C wally-pipelined/regression | ||||||
|  | 	 | ||||||
|  | 
 | ||||||
|  | 
 | ||||||
|  | 
 | ||||||
| @ -39,7 +39,7 @@ cd ../wally-riscv-arch-test | |||||||
| make | make | ||||||
| make XLEN=32 | make XLEN=32 | ||||||
| exe2memfile.pl work/*/*/*.elf  # converts ELF files to a format that can be read by Modelsim | exe2memfile.pl work/*/*/*.elf  # converts ELF files to a format that can be read by Modelsim | ||||||
| cd ../../tests/linux-testgen/linux-testvectors | cd ../linux-testgen/linux-testvectors | ||||||
| ./tvLinker.sh | ./tvLinker.sh | ||||||
| ``` | ``` | ||||||
| 
 | 
 | ||||||
|  | |||||||
							
								
								
									
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							| @ -0,0 +1,16 @@ | |||||||
|  | work/coremark.bare.riscv.memfile: work/coremark.bare.riscv.objdump | ||||||
|  | 	exe2memfile.pl work/coremark.bare.riscv | ||||||
|  | 
 | ||||||
|  | work/coremark.bare.riscv.objdump: work/coremark.bare.riscv | ||||||
|  | 	riscv64-unknown-elf-objdump -D work/coremark.bare.riscv > work/coremark.bare.riscv.objdump  | ||||||
|  | 
 | ||||||
|  | work/coremark.bare.riscv: | ||||||
|  | 	make -C coremark PORT_DIR=/home/harris/riscv-wally/benchmarks/riscv-coremark/riscv64-baremetal compile RISCV=/courses/e190ax/riscvcompiler XCFLAGS="-march=rv64im" | ||||||
|  | 	mv coremark/coremark.bare.riscv work | ||||||
|  | 	#make -C ../../addins/coremark PORT_DIR=/home/harris/riscv-wally/benchmarks/riscv-coremark/riscv64-baremetal compile RISCV=/courses/e190ax/riscvcompiler XCFLAGS="-march=rv64im" | ||||||
|  | 	#mv ../../addins/coremark/coremark.bare.riscv work | ||||||
|  | 
 | ||||||
|  | .PHONY: clean | ||||||
|  | 
 | ||||||
|  | clean: | ||||||
|  | 	rm -f work/* | ||||||
							
								
								
									
										
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								benchmarks/riscv-coremark/coremark/coremark.exe
									
									
									
									
									
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							| Before Width: | Height: | Size: 48 KiB After Width: | Height: | Size: 48 KiB | 
| Before Width: | Height: | Size: 70 KiB After Width: | Height: | Size: 70 KiB | 
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