Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Fix many more lint errors

Browse Source
This commit is contained in:
Matthew 2024-06-25 14:45:17 -05:00
parent 8bd674ba17
commit e9194395e3
6 changed files with 33 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/debug/dm.sv
View File

@ -76,6 +76,7 @@ module dm import cvw::*; #(parameter cvw_t P) (
localparam PROGBUF_SIZE = (P.PROGBUF_RANGE+1)/4;
localparam DATA_COUNT = (P.LLEN/32);
localparam AARSIZE_ENC = $clog2(P.LLEN/8);
// DMI Signals
logic ReqReady;
@ -348,7 +349,7 @@ module dm import cvw::*; #(parameter cvw_t P) (
`ACCESS_REGISTER : begin
if (~ReqData[`TRANSFER])
State <= ReqData[`POSTEXEC] ? EXEC_PROGBUF : ACK; // If not transfer, exec progbuf or do nothing
else if (ReqData[`AARSIZE] > $clog2(P.LLEN/8)[2:0])
else if (ReqData[`AARSIZE] > AARSIZE_ENC[2:0])
CmdErr <= `CMDERR_BUS; // If AARSIZE (encoded) is greater than P.LLEN, set CmdErr, do nothing
else if (InvalidRegNo)
CmdErr <= `CMDERR_EXCEPTION; // If InvalidRegNo, set CmdErr, do nothing

32
src/debug/rad.sv
View File

@ -49,7 +49,7 @@ module rad import cvw::*; #(parameter cvw_t P) (
localparam WRITEDATAMLEN = P.XLEN;
localparam IEUADRMLEN = P.XLEN;
localparam READDATAMLEN = P.LLEN;
localparam SCANCHAINLEN = P.LLEN - 1
localparam SCANCHAINLEN = P.LLEN
+ TRAPMLEN + PCMLEN + INSTRMLEN
+ MEMRWMLEN + INSTRVALIDMLEN + WRITEDATAMLEN
+ IEUADRMLEN + READDATAMLEN;
@ -66,7 +66,7 @@ module rad import cvw::*; #(parameter cvw_t P) (
logic [P.LLEN-1:0] Mask;
assign RegAddr = Regno[11:0];
assign ScanChainLen = (CSRegNo | GPRegNo) ? P.XLEN : FPRegNo ? P.FLEN : SCANCHAINLEN;
assign ScanChainLen = (CSRegNo | GPRegNo) ? P.XLEN[9:0] : FPRegNo ? P.FLEN[9:0] : SCANCHAINLEN[9:0];
// Register decoder
always_comb begin
@ -77,7 +77,7 @@ module rad import cvw::*; #(parameter cvw_t P) (
FPRegNo = 0;
case (Regno) inside
[`DCSR_REGNO:`DPC_REGNO] : begin
ShiftCount = P.LLEN - 1;
ShiftCount = P.LLEN[9:0] - 1;
CSRegNo = 1;
end
@ -108,7 +108,7 @@ module rad import cvw::*; #(parameter cvw_t P) (
`SIP_REGNO,
`MIE_REGNO,
`MIP_REGNO : begin
ShiftCount = P.LLEN - 1;
ShiftCount = P.LLEN[9:0] - 1'b1;
CSRegNo = 1;
// Comment out because gives error on openocd
// This value cause the csrs to all go read-only
@ -119,44 +119,44 @@ module rad import cvw::*; #(parameter cvw_t P) (
[`HPMCOUNTERBASE_REGNO:`TIME_REGNO],
[`HPMCOUNTERHBASE_REGNO:`TIMEH_REGNO],
[`MVENDORID_REGNO:`MCONFIGPTR_REGNO] : begin
ShiftCount = P.LLEN - 1;
ShiftCount = P.LLEN[9:0] - 1;
CSRegNo = 1;
RegReadOnly = 1;
end
[`X0_REGNO:`X15_REGNO] : begin
ShiftCount = P.LLEN - 1;
ShiftCount = P.LLEN[9:0] - 1;
GPRegNo = 1;
end
[`X16_REGNO:`X31_REGNO] : begin
ShiftCount = P.LLEN - 1;
ShiftCount = P.LLEN[9:0] - 1;
InvalidRegNo = P.E_SUPPORTED;
GPRegNo = 1;
end
[`FP0_REGNO:`FP31_REGNO] : begin
ShiftCount = P.LLEN - 1;
ShiftCount = P.LLEN[9:0] - 1;
InvalidRegNo = ~(P.F_SUPPORTED | P.D_SUPPORTED | P.Q_SUPPORTED);
FPRegNo = 1;
end
`TRAPM_REGNO : begin
ShiftCount = SCANCHAINLEN - TRAPM_IDX;
ShiftCount = SCANCHAINLEN[9:0] - TRAPM_IDX[9:0];
InvalidRegNo = ~P.ZICSR_SUPPORTED;
RegReadOnly = 1;
end
`PCM_REGNO : begin
ShiftCount = SCANCHAINLEN - PCM_IDX;
ShiftCount = SCANCHAINLEN[9:0] - PCM_IDX[9:0];
InvalidRegNo = ~(P.ZICSR_SUPPORTED | P.BPRED_SUPPORTED);
end
`INSTRM_REGNO : begin
ShiftCount = SCANCHAINLEN - INSTRM_IDX;
ShiftCount = SCANCHAINLEN[9:0] - INSTRM_IDX[9:0];
InvalidRegNo = ~(P.ZICSR_SUPPORTED | P.A_SUPPORTED);
end
`MEMRWM_REGNO : ShiftCount = SCANCHAINLEN - MEMRWM_IDX;
`INSTRVALIDM_REGNO : ShiftCount = SCANCHAINLEN - INSTRVALIDM_IDX;
`WRITEDATAM_REGNO : ShiftCount = SCANCHAINLEN - WRITEDATAM_IDX;
`IEUADRM_REGNO : ShiftCount = SCANCHAINLEN - IEUADRM_IDX;
`MEMRWM_REGNO : ShiftCount = SCANCHAINLEN[9:0] - MEMRWM_IDX[9:0];
`INSTRVALIDM_REGNO : ShiftCount = SCANCHAINLEN[9:0] - INSTRVALIDM_IDX[9:0];
`WRITEDATAM_REGNO : ShiftCount = SCANCHAINLEN[9:0] - WRITEDATAM_IDX[9:0];
`IEUADRM_REGNO : ShiftCount = SCANCHAINLEN[9:0] - IEUADRM_IDX[9:0];
`READDATAM_REGNO : begin
ShiftCount = SCANCHAINLEN - READDATAM_IDX;
ShiftCount = SCANCHAINLEN[9:0] - READDATAM_IDX[9:0];
RegReadOnly = 1;
end
default : begin

8
src/ifu/ifu.sv
View File

@ -431,8 +431,10 @@ module ifu import cvw::*; #(parameter cvw_t P) (
mux2 #(32) FlushInstrMMux(InstrE, nop, FlushM, NextInstrE);
if (P.DEBUG_SUPPORTED)
flopenrs #(32) InstrMReg(clk, reset, ~StallM, NextInstrE, InstrM, DebugScanEn, DebugScanChainReg, DebugScanOut);
else
else begin
flopenr #(32) InstrMReg(clk, reset, ~StallM, NextInstrE, InstrM);
assign DebugScanOut = DebugScanChainReg;
end
end else begin
assign InstrM = '0;
assign DebugScanOut = DebugScanChainReg;
@ -441,8 +443,10 @@ module ifu import cvw::*; #(parameter cvw_t P) (
if (P.ZICSR_SUPPORTED | P.BPRED_SUPPORTED)
if (P.DEBUG_SUPPORTED)
flopenrs #(P.XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM, DebugScanEn, DebugScanIn, DebugScanChainReg);
else
else begin
flopenr #(P.XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM);
assign DebugScanChainReg = DebugScanIn;
end
else begin
assign PCM = '0;
assign DebugScanChainReg = DebugScanIn;

2
src/ifu/progbuf.sv
View File

@ -31,7 +31,7 @@ module progbuf import cvw::*; #(parameter cvw_t P) (
input logic [5:0] Addr,
output logic [31:0] ProgBufInstrF,
input logic [3:0] ScanAddr,
input logic [$clog2(PROGBUF_SIZE)-1:0] ScanAddr,
input logic Scan,
input logic ScanIn
);

8
src/privileged/csr.sv
View File

@ -188,8 +188,8 @@ module csr import cvw::*; #(parameter cvw_t P) (
// A return sets the PC to MEPC or SEPC
if (P.DEBUG_SUPPORTED) begin
always_comb
if (ExecProgBuf) EPCM = P.PROGBUF_BASE;
else if (DRet) EPCM = DPC;
if (ExecProgBuf) EPCM = P.PROGBUF_BASE[P.XLEN-1:0];
else if (DRet) EPCM = DPC;
else if (mretM) EPCM = MEPC_REGW;
else EPCM = SEPC_REGW;
end else begin
@ -320,6 +320,10 @@ module csr import cvw::*; #(parameter cvw_t P) (
.CSRWriteDM, .CSRAdrM(CSRAdrDM), .CSRWriteValM(CSRWriteValDM), .CSRDReadValM, .IllegalCSRDAccessM,
.DebugCause, .ebreakEn, .Step, .DPC, .PCM, .DCall);
end else begin
assign Step = '0;
assign DPC = '0;
assign DebugScanOut = '0;
assign ebreakEn = 0;
assign CSRDReadValM = '0;
assign IllegalCSRDAccessM = 1'b1; // Debug isn't supported
end

4
src/privileged/trap.sv
View File

@ -67,7 +67,7 @@ module trap import cvw::*; #(parameter cvw_t P) (
assign IntPendingM = |PendingIntsM;
assign Committed = CommittedM | CommittedF;
assign EnabledIntsM = (MIntGlobalEnM ? PendingIntsM & ~MIDELEG_REGW : '0) | (SIntGlobalEnM ? PendingIntsM & MIDELEG_REGW : '0);
assign ValidIntsM = Committed ? '0 : EnabledIntsM;
assign ValidIntsM = (Committed | DebugMode) ? '0 : EnabledIntsM;
assign InterruptM = (|ValidIntsM) & InstrValidM & (~wfiM | wfiW); // suppress interrupt if the memory system has partially processed a request. Delay interrupt until wfi is in the W stage.
// wfiW is to support possible but unlikely back to back wfi instructions. wfiM would be high in the M stage, while also in the W stage.
assign DelegateM = P.S_SUPPORTED & (InterruptM ? MIDELEG_REGW[CauseM] : MEDELEG_REGW[CauseM]) &
@ -98,7 +98,7 @@ module trap import cvw::*; #(parameter cvw_t P) (
///////////////////////////////////////////
always_comb
if (reset) CauseM = 4'd0; // hard reset 3.3
if (reset) CauseM = 4'd0; // hard reset 3.3
else if (ValidIntsM[11]) CauseM = 4'd11; // Machine External Int
else if (ValidIntsM[3]) CauseM = 4'd3; // Machine Sw Int
else if (ValidIntsM[7]) CauseM = 4'd7; // Machine Timer Int