diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv
index 2f1bd9d80..a0370f2b4 100644
--- a/src/ieu/alu.sv
+++ b/src/ieu/alu.sv
@@ -55,22 +55,14 @@ module alu #(parameter WIDTH=32) (
   logic             Asign, Bsign;                                                 // Sign bits of A, B
   logic             shSignA;
   logic [WIDTH-1:0] rotA;                                                         // XLEN bit input source to shifter
-  logic [1:0]       shASelect;                                                    // select signal for shifter source generation mux 
-  logic             Rotate;                                                       // Indicates if it is Rotate instruction
 
   // Extract control signals from ALUControl.
   assign {W64, SubArith, ALUOp} = ALUControl;
 
-  // Extract rotate signal from BALUControl.
-  assign Rotate = BALUControl[2];
-
-  // Pack control signals into shifter select signal.
-  assign shASelect = {W64, SubArith};
-
   // A, A sign bit muxes
   if (WIDTH == 64) begin
     mux3 #(1) signmux(A[63], A[31], 1'b0, {~SubArith, W64}, shSignA);
-    mux3 #(64) extendmux({{32{1'b0}}, A[31:0]},{{32{A[31]}}, A[31:0]}, A,{~W64, SubArith}, CondExtA);
+    mux3 #(64) extendmux({{32{1'b0}}, A[31:0]},{{32{A[31]}}, A[31:0]}, A, {~W64, SubArith}, CondExtA); // bottom 32 bits are always A[31:0], so effectively a 32-bit upper mux
   end else begin 
     mux2 #(1) signmux(1'b0, A[31], SubArith, shSignA);
     assign CondExtA = A;
@@ -81,7 +73,7 @@ module alu #(parameter WIDTH=32) (
   assign {Carry, Sum} = CondShiftA + CondMaskInvB + {{(WIDTH-1){1'b0}}, SubArith};
   
   // Shifts (configurable for rotation)
-  shifter sh(.shA(CondExtA), .Sign(shSignA), .rotA, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .Y(Shift), .Rotate);
+  shifter sh(.shA(CondExtA), .Sign(shSignA), .rotA, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .Y(Shift), .Rotate(BALUControl[2]));
 
   // Condition code flags are based on subtraction output Sum = A-B.
   // Overflow occurs when the numbers being subtracted have the opposite sign 
diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv
index 46222cf7a..4769c63dd 100644
--- a/src/ieu/bmu/bmuctrl.sv
+++ b/src/ieu/bmu/bmuctrl.sv
@@ -34,7 +34,6 @@ module bmuctrl(
   // Decode stage control signals
   input  logic        StallD, FlushD,          // Stall, flush Decode stage
   input  logic [31:0] InstrD,                  // Instruction in Decode stage
-  output logic [2:0]  ALUSelectD,              // ALU Mux select signal in Decode Stage
   output logic [1:0]  BSelectD,                // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage
   output logic [2:0]  ZBBSelectD,              // ZBB mux select signal in Decode stage NOTE: do we need this in decode?
   output logic        BRegWriteD,              // Indicates if it is a R type B instruction in Decode Stage
@@ -62,6 +61,7 @@ module bmuctrl(
   logic       MaskD;                           // Indicates if zbs instruction in Decode Stage
   logic       PreShiftD;                       // Indicates if sh1add, sh2add, sh3add instruction in Decode Stage
   logic [2:0] BALUControlD;                    // ALU Control signals for B instructions
+  logic [2:0] ALUSelectD;                      // ALU Mux select signal in Decode Stage
 
   `define BMUCTRLW 17
   `define BMUCTRLWSUB3 14
diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv
index 5c397d157..2cb453110 100644
--- a/src/ieu/controller.sv
+++ b/src/ieu/controller.sv
@@ -98,7 +98,6 @@ module controller(
   logic	       BaseSubArithD;                  // Indicates if Base instruction subtracts, sra, slt, sltu
   logic        BaseALUSrcBD;                   // Base instruction ALU B source select signal
   logic [2:0]  ALUControlD;                    // Determines ALU operation
-  logic [2:0]  ALUSelectD;                     // ALU mux select signal
   logic 	     ALUSrcAD, ALUSrcBD;             // ALU inputs
   logic        ALUResultSrcD, W64D, MDUD;      // ALU result, is RV64 W-type, is multiply/divide instruction
   logic        CSRZeroSrcD;                    // Ignore setting and clearing zeros to CSR
@@ -260,7 +259,7 @@ module controller(
 
   // bit manipulation Configuration Block
   if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags
-    bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, 
+    bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .BSelectD, .ZBBSelectD, 
       .BRegWriteD, .BALUSrcBD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, 
       .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE, .BComparatorSignedE, .BALUControlE);
     if (`ZBA_SUPPORTED) begin
@@ -269,7 +268,6 @@ module controller(
     end else assign sltD = (Funct3D == 3'b010);
 
   end else begin: bitmanipi
-    assign ALUSelectD = Funct3D;
     assign ALUSelectE = Funct3E;
     assign BSelectE = 2'b00;
     assign BSelectD = 2'b00;