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https://github.com/openhwgroup/cvw
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
This commit is contained in:
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e8b966c5d1
@ -49,9 +49,9 @@
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`define PMPCFG_ENTRIES (`PMP_ENTRIES/8)
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// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits
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`define FLEN (`Q_SUPPORTED ? 128 : `D_SUPPORTED ? 64 : 32)
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`define NE (`Q_SUPPORTED ? 15 : `D_SUPPORTED ? 11 : 8)
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`define NF (`Q_SUPPORTED ? 112 : `D_SUPPORTED ? 52 : 23)
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`define FLEN 64//(`Q_SUPPORTED ? 128 : `D_SUPPORTED ? 64 : 32)
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`define NE 11//(`Q_SUPPORTED ? 15 : `D_SUPPORTED ? 11 : 8)
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`define NF 52//(`Q_SUPPORTED ? 112 : `D_SUPPORTED ? 52 : 23)
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// Disable spurious Verilator warnings
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@ -23,6 +23,7 @@
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///////////////////////////////////////////
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`include "wally-config.vh"
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// `include "../../../config/rv64icfd/wally-config.vh"
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module fma(
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input logic clk,
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@ -33,11 +34,11 @@ module fma(
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input logic [2:0] FOpCtrlM, FOpCtrlE, // 000 = fmadd (X*Y)+Z, 001 = fmsub (X*Y)-Z, 010 = fnmsub -(X*Y)+Z, 011 = fnmadd -(X*Y)-Z, 100 = fmul (X*Y)
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input logic [2:0] FrmM, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
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input logic XSgnE, YSgnE, ZSgnE,
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input logic [10:0] XExpE, YExpE, ZExpE,
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input logic [51:0] XFracE, YFracE, ZFracE,
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input logic [`NE-1:0] XExpE, YExpE, ZExpE,
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input logic [`NF-1:0] XFracE, YFracE, ZFracE,
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input logic XSgnM, YSgnM, ZSgnM,
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input logic [10:0] XExpM, YExpM, ZExpM,
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input logic [51:0] XFracM, YFracM, ZFracM,
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input logic [`NE-1:0] XExpM, YExpM, ZExpM,
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input logic [`NF-1:0] XFracM, YFracM, ZFracM,
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input logic XAssumed1E, YAssumed1E, ZAssumed1E,
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input logic XDenormE, YDenormE, ZDenormE,
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input logic XZeroE, YZeroE, ZZeroE,
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@ -46,13 +47,13 @@ module fma(
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input logic XZeroM, YZeroM, ZZeroM,
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input logic XInfM, YInfM, ZInfM,
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input logic [10:0] BiasE,
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output logic [63:0] FMAResM,
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output logic [`FLEN-1:0] FMAResM,
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output logic [4:0] FMAFlgM);
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logic [105:0] ProdManE, ProdManM;
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logic [161:0] AlignedAddendE, AlignedAddendM;
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logic [12:0] ProdExpE, ProdExpM;
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logic [2*`NF+1:0] ProdManE, ProdManM;
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logic [3*`NF+5:0] AlignedAddendE, AlignedAddendM;
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logic [`NE+1:0] ProdExpE, ProdExpM;
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logic AddendStickyE, AddendStickyM;
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logic KillProdE, KillProdM;
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@ -128,7 +129,7 @@ module fma1(
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assign AlignCnt = ProdExpE - ZExpE - ZDenormE;
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// Defualt Addition without shifting
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// | 55'b0 | 106'b(product) | 2'b0 |
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// | 54'b0 | 106'b(product) | 2'b0 |
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// |1'b0| addnend |
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// the 1'b0 before the added is because the product's mantissa has two bits before the binary point (xx.xxxxxxxxxx...)
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@ -140,7 +141,7 @@ module fma1(
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// | 54'b0 | 106'b(product) | 2'b0 |
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// | addnend |
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if ($signed(AlignCnt) <= /*$signed(-13'd56)*/-(`NF+4)) begin
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if ($signed(AlignCnt) <= $signed(-(`NF+4))) begin
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KillProdE = 1;
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ZManShifted = ZManPreShifted;//{107'b0, {~ZAssumed1E, ZFrac}, 54'b0};
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AddendStickyE = ~(XZeroE|YZeroE);
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@ -149,19 +150,19 @@ module fma1(
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// | 54'b0 | 106'b(product) | 2'b0 |
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// | addnend |
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end else if($signed(AlignCnt) <= 0) begin
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end else if($signed(AlignCnt) <= $signed(0)) begin
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KillProdE = 0;
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ZManShifted = ZManPreShifted << -AlignCnt;
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AddendStickyE = |(ZManShifted[51:0]);
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AddendStickyE = |(ZManShifted[`NF-1:0]);
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// If the Addend is shifted right (positive AlignCnt)
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// | 54'b0 | 106'b(product) | 2'b0 |
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// | addnend |
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end else if ($signed(AlignCnt)<=(2*`NF+2)) begin
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end else if ($signed(AlignCnt)<=$signed(2*`NF+1)) begin
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KillProdE = 0;
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ZManShifted = ZManPreShifted >> AlignCnt;
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AddendStickyE = |(ZManShifted[51:0]);
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AddendStickyE = |(ZManShifted[`NF-1:0]);
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// If the addend is too small to effect the addition
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// - The addend has to shift two past the end of the addend to be considered too small
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@ -176,47 +177,47 @@ module fma1(
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end
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end
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assign AlignedAddendE = ZManShifted[(4*`NF+5):`NF];
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assign AlignedAddendE = ZManShifted[4*`NF+5:`NF];
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endmodule
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module fma2(
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input logic XSgnM, YSgnM, ZSgnM,
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input logic [10:0] XExpM, YExpM, ZExpM,
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input logic [51:0] XFracM, YFracM, ZFracM,
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input logic [`NE-1:0] XExpM, YExpM, ZExpM,
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input logic [`NF-1:0] XFracM, YFracM, ZFracM,
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input logic [2:0] FrmM, // rounding mode 000 = rount to nearest, ties to even 001 = round twords zero 010 = round down 011 = round up 100 = round to nearest, ties to max magnitude
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input logic [2:0] FOpCtrlM, // 000 = fmadd (X*Y)+Z, 001 = fmsub (X*Y)-Z, 010 = fnmsub -(X*Y)+Z, 011 = fnmadd -(X*Y)-Z, 100 = fmul (X*Y)
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input logic FmtM, // precision 1 = double 0 = single
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input logic [105:0] ProdManM, // 1.X frac * 1.Y frac
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input logic [161:0] AlignedAddendM, // Z aligned for addition
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input logic [12:0] ProdExpM, // X exponent + Y exponent - bias
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input logic [2*`NF+1:0] ProdManM, // 1.X frac * 1.Y frac
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input logic [3*`NF+5:0] AlignedAddendM, // Z aligned for addition
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input logic [`NE+1:0] ProdExpM, // X exponent + Y exponent - bias
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input logic AddendStickyM, // sticky bit that is calculated during alignment
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input logic KillProdM, // set the product to zero before addition if the product is too small to matter
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input logic XZeroM, YZeroM, ZZeroM, // inputs are zero
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input logic XInfM, YInfM, ZInfM, // inputs are infinity
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input logic XNaNM, YNaNM, ZNaNM, // inputs are NaN
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input logic XSNaNM, YSNaNM, ZSNaNM, // inputs are signaling NaNs
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output logic [63:0] FMAResM, // FMA final result
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output logic [`FLEN-1:0] FMAResM, // FMA final result
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output logic [4:0] FMAFlgM); // FMA flags {invalid, divide by zero, overflow, underflow, inexact}
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logic [51:0] ResultFrac; // Result fraction
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logic [10:0] ResultExp; // Result exponent
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logic [`NF-1:0] ResultFrac; // Result fraction
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logic [`NE-1:0] ResultExp; // Result exponent
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logic ResultSgn; // Result sign
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logic PSgn; // product sign
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logic [105:0] ProdMan2; // product being added
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logic [162:0] AlignedAddend2; // possibly inverted aligned Z
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logic [161:0] Sum; // positive sum
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logic [162:0] PreSum; // possibly negitive sum
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logic [12:0] SumExp; // exponent of the normalized sum
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logic [12:0] SumExpTmp; // exponent of the normalized sum not taking into account denormal or zero results
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logic [12:0] SumExpTmpMinus1; // SumExpTmp-1
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logic [12:0] FullResultExp; // ResultExp with bits to determine sign and overflow
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logic [54:0] NormSum; // normalized sum
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logic [161:0] SumShifted; // sum shifted for normalization
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logic [8:0] NormCnt; // output of the leading zero detector
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logic [2*`NF+1:0] ProdMan2; // product being added
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logic [3*`NF+6:0] AlignedAddend2; // possibly inverted aligned Z
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logic [3*`NF+5:0] Sum; // positive sum
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logic [3*`NF+6:0] PreSum; // possibly negitive sum
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logic [`NE+1:0] SumExp; // exponent of the normalized sum
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logic [`NE+1:0] SumExpTmp; // exponent of the normalized sum not taking into account denormal or zero results
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logic [`NE+1:0] SumExpTmpMinus1; // SumExpTmp-1
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logic [`NE+1:0] FullResultExp; // ResultExp with bits to determine sign and overflow
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logic [`NF+2:0] NormSum; // normalized sum
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logic [3*`NF+5:0] SumShifted; // sum shifted for normalization
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logic [8:0] NormCnt; // output of the leading zero detector //***change this later
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logic NormSumSticky; // sticky bit calulated from the normalized sum
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logic SumZero; // is the sum zero
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logic NegSum; // is the sum negitive
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@ -226,18 +227,18 @@ module fma2(
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logic Plus1, Minus1, CalcPlus1, CalcMinus1; // do you add or subtract one for rounding
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logic UfPlus1, UfCalcPlus1; // do you add one (for determining underflow flag)
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logic Invalid,Underflow,Overflow,Inexact; // flags
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logic [8:0] DenormShift; // right shift if the result is denormalized
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logic [8:0] DenormShift; // right shift if the result is denormalized //***change this later
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logic SubBySmallNum; // was there supposed to be a subtraction by a small number
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logic [63:0] Addend; // value to add (Z or zero)
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logic [`FLEN-1:0] Addend; // value to add (Z or zero)
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logic ZeroSgn; // the result's sign if the sum is zero
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logic ResultSgnTmp; // the result's sign assuming the result is not zero
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logic Guard, Round, LSBNormSum; // bits needed to determine rounding
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logic UfGuard, UfRound, UfLSBNormSum; // bits needed to determine rounding for underflow flag
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logic [12:0] MaxExp; // maximum value of the exponent
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logic [12:0] FracLen; // length of the fraction
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logic [`NE+1:0] MaxExp; // maximum value of the exponent
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logic [`NE+1:0] FracLen; // length of the fraction
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logic SigNaN; // is an input a signaling NaN
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logic UnderflowFlag; // Underflow singal used in FMAFlgM (used to avoid a circular depencency)
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logic [63:0] XNaNResult, YNaNResult, ZNaNResult, InvalidResult, OverflowResult, KillProdResult, UnderflowResult; // possible results
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logic [`FLEN-1:0] XNaNResult, YNaNResult, ZNaNResult, InvalidResult, OverflowResult, KillProdResult, UnderflowResult; // possible results
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@ -259,17 +260,17 @@ module fma2(
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// Choose an inverted or non-inverted addend - the one is added later
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assign AlignedAddend2 = InvZ ? ~{1'b0, AlignedAddendM} : {1'b0, AlignedAddendM};
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// Kill the product if the product is too small to effect the addition (determined in fma1.sv)
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assign ProdMan2 = KillProdM ? 106'b0 : ProdManM;
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assign ProdMan2 = KillProdM ? 0 : ProdManM;
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// Do the addition
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// - add one to negate if the added was inverted
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// - the 2 extra bits at the begining and end are needed for rounding
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assign PreSum = AlignedAddend2 + {55'b0, ProdMan2, 2'b0} + {162'b0, InvZ};
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assign PreSum = AlignedAddend2 + {ProdMan2, 2'b0} + InvZ;
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// Is the sum negitive
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assign NegSum = PreSum[162];
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assign NegSum = PreSum[3*`NF+6];
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// If the sum is negitive, negate the sum.
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assign Sum = NegSum ? -PreSum[161:0] : PreSum[161:0];
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assign Sum = NegSum ? -PreSum[3*`NF+5:0] : PreSum[3*`NF+5:0];
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@ -284,7 +285,7 @@ module fma2(
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logic [8:0] i;
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always_comb begin
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i = 0;
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while (~Sum[161-i] && $unsigned(i) <= $unsigned(9'd161)) i = i+1; // search for leading one
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while (~Sum[3*`NF+5-i] && $unsigned(i) <= $unsigned(3*`NF+5)) i = i+1; // search for leading one
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NormCnt = i+1; // compute shift count
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end
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@ -306,26 +307,26 @@ module fma2(
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assign SumZero = ~(|Sum);
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// determine the length of the fraction based on precision
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assign FracLen = FmtM ? 13'd52 : 13'd23;
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assign FracLen = FmtM ? `NF : 13'd23;
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// Determine if the result is denormal
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assign SumExpTmp = KillProdM ? {2'b0, ZExpM} : ProdExpM + -({4'b0, NormCnt} - 13'd56);
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assign SumExpTmp = KillProdM ? {2'b0, ZExpM} : ProdExpM + -({4'b0, NormCnt} - (`NF+4));
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assign ResultDenorm = $signed(SumExpTmp)<=0 & ($signed(SumExpTmp)>=$signed(-FracLen)) & ~SumZero;
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// Determine the shift needed for denormal results
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assign SumExpTmpMinus1 = SumExpTmp-1;
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assign DenormShift = ResultDenorm ? SumExpTmpMinus1[8:0] : 9'b0;
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assign DenormShift = ResultDenorm ? SumExpTmpMinus1[8:0] : 0; //*** change this when changing the size of DenormShift also change to an and opperation
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// Normalize the sum
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assign SumShifted = SumZero ? 162'b0 : Sum << NormCnt+DenormShift;
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assign NormSum = SumShifted[161:107];
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assign SumShifted = SumZero ? 0 : Sum << NormCnt+DenormShift; //*** fix mux's with constants in them
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assign NormSum = SumShifted[3*`NF+5:2*`NF+3];
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// Calculate the sticky bit
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assign NormSumSticky = FmtM ? (|SumShifted[107:0]) : (|SumShifted[136:0]);
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assign NormSumSticky = FmtM ? (|SumShifted[2*`NF+3:0]) : (|SumShifted[136:0]);
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assign Sticky = AddendStickyM | NormSumSticky;
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// Determine sum's exponent
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assign SumExp = SumZero ? 13'b0 :
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ResultDenorm ? 13'b0 :
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assign SumExp = SumZero ? 0 : //***again fix mux
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ResultDenorm ? 0 :
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SumExpTmp;
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@ -412,14 +413,14 @@ module fma2(
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assign Minus1 = CalcMinus1 & (Sticky | UfGuard | Guard | Round);
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// Compute rounded result
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logic [64:0] RoundAdd;
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logic [51:0] NormSumTruncated;
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assign RoundAdd = FmtM ? Minus1 ? {65{1'b1}} : {64'b0, Plus1} :
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logic [`FLEN:0] RoundAdd; //*** move this up
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logic [`NF-1:0] NormSumTruncated;
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assign RoundAdd = FmtM ? Minus1 ? {`FLEN+1{1'b1}} : {{{`FLEN{1'b0}}}, Plus1} :
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Minus1 ? {{36{1'b1}}, 29'b0} : {35'b0, Plus1, 29'b0};
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assign NormSumTruncated = FmtM ? NormSum[54:3] : {NormSum[54:32], 29'b0};
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assign NormSumTruncated = FmtM ? NormSum[`NF+2:3] : {NormSum[54:32], 29'b0};
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assign {FullResultExp, ResultFrac} = {SumExp, NormSumTruncated} + RoundAdd;
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assign ResultExp = FullResultExp[10:0];
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assign ResultExp = FullResultExp[`NE-1:0];
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@ -457,18 +458,18 @@ module fma2(
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// 1) any input is a signaling NaN
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// 2) Inf - Inf (unless x or y is NaN)
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// 3) 0 * Inf
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assign MaxExp = FmtM ? 13'd2047 : 13'd255;
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assign MaxExp = FmtM ? {`NE{1'b1}} : 13'd255;
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assign SigNaN = XSNaNM | YSNaNM | ZSNaNM;
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assign Invalid = SigNaN | ((XInfM || YInfM) & ZInfM & (PSgn ^ ZSgnM) & ~XNaNM & ~YNaNM) | (XZeroM & YInfM) | (YZeroM & XInfM);
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// Set Overflow flag if the number is too big to be represented
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// - Don't set the overflow flag if an overflowed result isn't outputed
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assign Overflow = FullResultExp >= MaxExp & ~FullResultExp[12]&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM);
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assign Overflow = FullResultExp >= MaxExp & ~FullResultExp[`NE+1]&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM);
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// Set Underflow flag if the number is too small to be represented in normal numbers
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// - Don't set the underflow flag if the result is exact
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assign Underflow = (SumExp[12] | ((SumExp == 0) & (Round|Guard|Sticky|UfGuard)))&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM);
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assign UnderflowFlag = (FullResultExp[12] | ((FullResultExp == 0) | ((FullResultExp == 1) & (SumExp == 0) & ~(UfPlus1&UfLSBNormSum)))&(Round|Guard|Sticky))&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM);
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assign Underflow = (SumExp[`NE+1] | ((SumExp == 0) & (Round|Guard|Sticky|UfGuard)))&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM);
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assign UnderflowFlag = (FullResultExp[`NE+1] | ((FullResultExp == 0) | ((FullResultExp == 1) & (SumExp == 0) & ~(UfPlus1&UfLSBNormSum)))&(Round|Guard|Sticky))&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM);
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// Set Inexact flag if the result is diffrent from what would be outputed given infinite precision
|
||||
// - Don't set the underflow flag if an underflowed result isn't outputed
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assign Inexact = (Sticky|UfGuard|Overflow|Guard|Round|Underflow)&~(XNaNM|YNaNM|ZNaNM|XInfM|YInfM|ZInfM);
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@ -489,23 +490,23 @@ module fma2(
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///////////////////////////////////////////////////////////////////////////////
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// Select the result
|
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///////////////////////////////////////////////////////////////////////////////
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assign XNaNResult = FmtM ? {XSgnM, XExpM, 1'b1, XFracM[50:0]} : {{32{1'b1}}, XSgnM, XExpM[7:0], 1'b1, XFracM[50:29]};
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assign YNaNResult = FmtM ? {YSgnM, YExpM, 1'b1, YFracM[50:0]} : {{32{1'b1}}, YSgnM, YExpM[7:0], 1'b1, YFracM[50:29]};
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assign ZNaNResult = FmtM ? {ZSgnM, ZExpM, 1'b1, ZFracM[50:0]} : {{32{1'b1}}, ZSgnM, ZExpM[7:0], 1'b1, ZFracM[50:29]};
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assign OverflowResult = FmtM ? ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {ResultSgn, 11'h7fe, {52{1'b1}}} :
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{ResultSgn, 11'h7ff, 52'b0} :
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assign XNaNResult = FmtM ? {XSgnM, XExpM, 1'b1, XFracM[`NF-2:0]} : {{32{1'b1}}, XSgnM, XExpM[7:0], 1'b1, XFracM[50:29]};
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assign YNaNResult = FmtM ? {YSgnM, YExpM, 1'b1, YFracM[`NF-2:0]} : {{32{1'b1}}, YSgnM, YExpM[7:0], 1'b1, YFracM[50:29]};
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||||
assign ZNaNResult = FmtM ? {ZSgnM, ZExpM, 1'b1, ZFracM[`NF-2:0]} : {{32{1'b1}}, ZSgnM, ZExpM[7:0], 1'b1, ZFracM[50:29]};
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assign OverflowResult = FmtM ? ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {ResultSgn, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} :
|
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{ResultSgn, {`NE{1'b1}}, {`NF{1'b0}}} :
|
||||
((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{32{1'b1}}, ResultSgn, 8'hfe, {23{1'b1}}} :
|
||||
{{32{1'b1}}, ResultSgn, 8'hff, 23'b0};
|
||||
assign InvalidResult = FmtM ? {ResultSgn, 11'h7ff, 1'b1, 51'b0} : {{32{1'b1}}, ResultSgn, 8'hff, 1'b1, 22'b0};
|
||||
assign KillProdResult = FmtM ? {ResultSgn, {ZExpM, ZFracM} - {62'b0, (Minus1&AddendStickyM)}} + {62'b0, (Plus1&AddendStickyM)} : {{32{1'b1}}, ResultSgn, {ZExpM[7:0], ZFracM[51:29]} - {30'b0, (Minus1&AddendStickyM)} + {30'b0, (Plus1&AddendStickyM)}};
|
||||
assign UnderflowResult = FmtM ? {ResultSgn, 63'b0} + {63'b0, (CalcPlus1&(AddendStickyM|FrmM[1]))} : {{32{1'b1}}, {ResultSgn, 31'b0} + {31'b0, (CalcPlus1&(AddendStickyM|FrmM[1]))}};
|
||||
assign InvalidResult = FmtM ? {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{32{1'b1}}, ResultSgn, 8'hff, 1'b1, 22'b0};
|
||||
assign KillProdResult = FmtM ? {ResultSgn, {ZExpM, ZFracM} - (Minus1&AddendStickyM) + (Plus1&AddendStickyM)} : {{32{1'b1}}, ResultSgn, {ZExpM[7:0], ZFracM[51:29]} - {30'b0, (Minus1&AddendStickyM)} + {30'b0, (Plus1&AddendStickyM)}};
|
||||
assign UnderflowResult = FmtM ? {ResultSgn, {`FLEN-1{1'b0}}} + (CalcPlus1&(AddendStickyM|FrmM[1])) : {{32{1'b1}}, {ResultSgn, 31'b0} + {31'b0, (CalcPlus1&(AddendStickyM|FrmM[1]))}};
|
||||
assign FMAResM = XNaNM ? XNaNResult :
|
||||
YNaNM ? YNaNResult :
|
||||
ZNaNM ? ZNaNResult :
|
||||
Invalid ? InvalidResult : // has to be before inf
|
||||
XInfM ? FmtM ? {PSgn, XExpM, XFracM} : {{32{1'b1}}, PSgn, XExpM[7:0], XFracM[51:29]} :
|
||||
XInfM ? FmtM ? {PSgn, YExpM, YFracM} : {{32{1'b1}}, PSgn, YExpM[7:0], YFracM[51:29]} :
|
||||
XInfM ? FmtM ? {ZSgnM, ZExpM, ZFracM} : {{32{1'b1}}, ZSgnM, ZExpM[7:0], ZFracM[51:29]} :
|
||||
YInfM ? FmtM ? {PSgn, YExpM, YFracM} : {{32{1'b1}}, PSgn, YExpM[7:0], YFracM[51:29]} :
|
||||
ZInfM ? FmtM ? {ZSgnM, ZExpM, ZFracM} : {{32{1'b1}}, ZSgnM, ZExpM[7:0], ZFracM[51:29]} :
|
||||
Overflow ? OverflowResult :
|
||||
KillProdM ? KillProdResult : // has to be after Underflow
|
||||
Underflow & ~ResultDenorm ? UnderflowResult :
|
||||
|
||||
@ -56,9 +56,9 @@ module unpacking (
|
||||
assign YNaNE = YExpMaxE & ~YFracZero;
|
||||
assign ZNaNE = ZExpMaxE & ~ZFracZero;
|
||||
|
||||
assign XSNaNE = XNaNE&~XExpE[51];
|
||||
assign YSNaNE = YNaNE&~YExpE[51];
|
||||
assign ZSNaNE = ZNaNE&~ZExpE[51];
|
||||
assign XSNaNE = XNaNE&~XFracE[51];
|
||||
assign YSNaNE = YNaNE&~YFracE[51];
|
||||
assign ZSNaNE = ZNaNE&~ZFracE[51];
|
||||
|
||||
assign XDenormE = XExpZero & ~XFracZero;
|
||||
assign YDenormE = YExpZero & ~YFracZero;
|
||||
|
||||
@ -61,7 +61,7 @@ string tests32f[] = '{
|
||||
"rv32f/I-FCVT-S-WU-01", "2000",
|
||||
"rv32f/I-FCVT-W-S-01", "2000",
|
||||
"rv32f/I-FCVT-WU-S-01", "2000",
|
||||
"rv32f/I-FDIV-S-01", "2000",
|
||||
// "rv32f/I-FDIV-S-01", "2000",
|
||||
"rv32f/I-FEQ-S-01", "2000",
|
||||
"rv32f/I-FLE-S-01", "2000",
|
||||
"rv32f/I-FLT-S-01", "2000",
|
||||
@ -77,7 +77,7 @@ string tests32f[] = '{
|
||||
"rv32f/I-FSGNJ-S-01", "2000",
|
||||
"rv32f/I-FSGNJN-S-01", "2000",
|
||||
"rv32f/I-FSGNJX-S-01", "2000",
|
||||
"rv32f/I-FSQRT-S-01", "2000",
|
||||
// "rv32f/I-FSQRT-S-01", "2000",
|
||||
"rv32f/I-FSW-01", "2000",
|
||||
"rv32f/I-FLW-01", "2110",
|
||||
"rv32f/I-FSUB-S-01", "2000"
|
||||
@ -98,7 +98,7 @@ string tests32f[] = '{
|
||||
"rv64f/I-FCVT-LU-S-01", "2000",
|
||||
"rv64f/I-FCVT-W-S-01", "2000",
|
||||
"rv64f/I-FCVT-WU-S-01", "2000",
|
||||
"rv64f/I-FDIV-S-01", "2000",
|
||||
// "rv64f/I-FDIV-S-01", "2000",
|
||||
"rv64f/I-FEQ-S-01", "2000",
|
||||
"rv64f/I-FLE-S-01", "2000",
|
||||
"rv64f/I-FLT-S-01", "2000",
|
||||
@ -112,7 +112,7 @@ string tests32f[] = '{
|
||||
"rv64f/I-FSGNJ-S-01", "2000",
|
||||
"rv64f/I-FSGNJN-S-01", "2000",
|
||||
"rv64f/I-FSGNJX-S-01", "2000",
|
||||
"rv64f/I-FSQRT-S-01", "2000",
|
||||
// "rv64f/I-FSQRT-S-01", "2000",
|
||||
"rv64f/I-FSUB-S-01", "2000"
|
||||
};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user