From 33110ed6363bc3a692e9a0255139b0fff334ce16 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 7 Feb 2021 23:21:55 -0500 Subject: [PATCH 01/33] Data memory bus integration --- wally-pipelined/config/rv64ic/wally-config.vh | 2 +- wally-pipelined/regression/wally-pipelined.do | 9 +- wally-pipelined/src/dmem/dmem.sv | 17 ++-- wally-pipelined/src/ebu/ahblite.sv | 93 +++++++++++++++---- wally-pipelined/src/ebu/subwordread.sv | 20 ++-- wally-pipelined/src/hazard/hazard.sv | 38 +++++--- wally-pipelined/src/ieu/controller.sv | 12 +-- wally-pipelined/src/ieu/datapath.sv | 30 +++--- wally-pipelined/src/ieu/forward.sv | 2 +- wally-pipelined/src/ieu/ieu.sv | 3 +- wally-pipelined/src/ifu/ifu.sv | 33 ++++--- wally-pipelined/src/uncore/dtim.sv | 52 ++++++++--- wally-pipelined/src/uncore/subwordwrite.sv | 33 ++++--- wally-pipelined/src/uncore/uartPC16550D.sv | 1 + wally-pipelined/src/uncore/uncore.sv | 6 +- .../src/wally/wallypipelinedhart.sv | 39 +++++--- .../src/wally/wallypipelinedsoc.sv | 3 + .../testbench/testbench-imperas.sv | 11 ++- 18 files changed, 267 insertions(+), 137 deletions(-) diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh index eb340ddc2..8ab42cdd3 100644 --- a/wally-pipelined/config/rv64ic/wally-config.vh +++ b/wally-pipelined/config/rv64ic/wally-config.vh @@ -61,7 +61,7 @@ // Bus Interface width `define AHBW 64 -// Peripheral Addresses +// Peripheral Physiccal Addresses // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits diff --git a/wally-pipelined/regression/wally-pipelined.do b/wally-pipelined/regression/wally-pipelined.do index b7f41535d..a88569f49 100644 --- a/wally-pipelined/regression/wally-pipelined.do +++ b/wally-pipelined/regression/wally-pipelined.do @@ -45,11 +45,14 @@ view wave add wave /testbench/clk add wave /testbench/reset add wave -divider -add wave /testbench/dut/hart/ebu/IReadF +#add wave /testbench/dut/hart/ebu/IReadF add wave /testbench/dut/hart/DataStall add wave /testbench/dut/hart/InstrStall add wave /testbench/dut/hart/StallF add wave /testbench/dut/hart/StallD +add wave /testbench/dut/hart/StallE +add wave /testbench/dut/hart/StallM +add wave /testbench/dut/hart/StallW add wave /testbench/dut/hart/FlushD add wave /testbench/dut/hart/FlushE add wave /testbench/dut/hart/FlushM @@ -101,6 +104,6 @@ configure wave -childrowmargin 2 set DefaultRadix hexadecimal -- Run the Simulation -#run 1000 -run -all +run 2000 +#run -all #quit diff --git a/wally-pipelined/src/dmem/dmem.sv b/wally-pipelined/src/dmem/dmem.sv index 4c602659f..aab74fadc 100644 --- a/wally-pipelined/src/dmem/dmem.sv +++ b/wally-pipelined/src/dmem/dmem.sv @@ -30,19 +30,19 @@ module dmem ( input logic clk, reset, input logic FlushW, - output logic DataStall, + //output logic DataStall, // Memory Stage input logic [1:0] MemRWM, input logic [`XLEN-1:0] MemAdrM, input logic [2:0] Funct3M, - input logic [`XLEN-1:0] ReadDataM, + //input logic [`XLEN-1:0] ReadDataW, input logic [`XLEN-1:0] WriteDataM, output logic [`XLEN-1:0] MemPAdrM, - output logic [1:0] MemRWAlignedM, + output logic MemReadM, MemWriteM, output logic DataMisalignedM, // Writeback Stage input logic MemAckW, - output logic [`XLEN-1:0] ReadDataW, + input logic [`XLEN-1:0] ReadDataW, // faults input logic DataAccessFaultM, output logic LoadMisalignedFaultM, LoadAccessFaultM, @@ -52,9 +52,6 @@ module dmem ( // Initially no MMU assign MemPAdrM = MemAdrM; - // Pipeline register *** AHB data will eventually come back in W anyway - floprc #(`XLEN) ReadDataWReg(clk, reset, FlushW, ReadDataM, ReadDataW); - // Determine if an Unaligned access is taking place always_comb case(Funct3M[1:0]) @@ -66,7 +63,9 @@ module dmem ( // Squash unaligned data accesses // *** this is also the place to squash if the cache is hit - assign MemRWAlignedM = MemRWM & {2{~DataMisalignedM}}; + assign MemReadM = MemRWM[1] & ~DataMisalignedM; + assign MemWriteM = MemRWM[0] & ~DataMisalignedM; +// assign MemRWAlignedM = MemRWM & {2{~DataMisalignedM}}; // Determine if address is valid assign LoadMisalignedFaultM = DataMisalignedM & MemRWM[1]; @@ -75,7 +74,7 @@ module dmem ( assign StoreAccessFaultM = DataAccessFaultM & MemRWM[0]; // Data stall - assign DataStall = 0; + //assign DataStall = 0; endmodule diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv index 8ce17545f..9d4e62be7 100644 --- a/wally-pipelined/src/ebu/ahblite.sv +++ b/wally-pipelined/src/ebu/ahblite.sv @@ -36,16 +36,16 @@ module ahblite ( input logic UnsignedLoadM, // Signals from Instruction Cache input logic [`XLEN-1:0] InstrPAdrF, // *** rename these to match block diagram - input logic IReadF, - output logic [`XLEN-1:0] IRData, + input logic InstrReadF, + output logic [31:0] InstrRData, // output logic IReady, // Signals from Data Cache input logic [`XLEN-1:0] MemPAdrM, - input logic DReadM, DWriteM, + input logic MemReadM, MemWriteM, input logic [`XLEN-1:0] WriteDataM, - input logic [1:0] DSizeM, + input logic [1:0] MemSizeM, // Return from bus - output logic [`XLEN-1:0] DRData, + output logic [`XLEN-1:0] ReadDataW, // output logic DReady, // AHB-Lite external signals input logic [`AHBW-1:0] HRDATA, @@ -59,49 +59,108 @@ module ahblite ( output logic [3:0] HPROT, output logic [1:0] HTRANS, output logic HMASTLOCK, + // Delayed signals for subword write + output logic [2:0] HADDRD, + output logic [3:0] HSIZED, + output logic HWRITED, // Acknowledge - output logic InstrAckD, MemAckW + output logic InstrAckD, MemAckW, // Stalls -// output logic InstrStall, DataStall + output logic InstrStall, DataStall ); logic GrantData; logic [2:0] ISize; logic [`AHBW-1:0] HRDATAMasked; logic IReady, DReady; +// logic [3:0] HSIZED; // size delayed by one cycle for reads +// logic [2:0] HADDRD; // address delayed for subword reads assign HCLK = clk; assign HRESETn = ~reset; // Arbitrate requests by giving data priority over instructions - assign GrantData = DReadM | DWriteM; + assign GrantData = MemReadM | MemWriteM; // *** initially support HABW = XLEN + // track bus state + typedef enum {IDLE, MEMREAD, MEMWRITE, INSTRREAD} statetype; + statetype AdrState, DataState, NextAdrState; // what is happening in the first and second phases of the bus + always_ff @(posedge HCLK, negedge HRESETn) + if (~HRESETn) begin + AdrState <= IDLE; DataState <= IDLE; + HWDATA <= 0; // unnecessary but avoids x at startup + HSIZED <= 0; + HADDRD <= 0; + HWRITED <= 0; + end else begin + if (HREADY || (DataState == IDLE)) begin // only advance bus state if bus is idle or previous transaction returns ready + DataState <= AdrState; + AdrState <= NextAdrState; + if (HWRITE) HWDATA <= WriteDataM; + HSIZED <= {UnsignedLoadM, HSIZE}; + HADDRD <= HADDR[2:0]; + HWRITED <= HWRITE; + end + end + always_comb + if (MemReadM) NextAdrState = MEMREAD; + else if (MemWriteM) NextAdrState = MEMWRITE; + else if (InstrReadF) NextAdrState = INSTRREAD; + else NextAdrState = IDLE; + + // Generate acknowledges based on bus state and ready + assign MemAckW = (AdrState == MEMREAD || AdrState == MEMWRITE) && HREADY; + assign InstrAckD = (AdrState == INSTRREAD) && HREADY; + // Choose ISize based on XLen generate - if (`AHBW == 32) assign ISize = 3'b010; // 32-bit transfers - else assign ISize = 3'b011; // 64-bit transfers + //if (`AHBW == 32) assign ISize = 3'b010; // 32-bit transfers + //else assign ISize = 3'b011; // 64-bit transfers + assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width endgenerate // drive bus outputs assign HADDR = GrantData ? MemPAdrM[31:0] : InstrPAdrF[31:0]; - assign HWDATA = WriteDataM; + //assign HWDATA = WriteDataW; //flop #(`XLEN) wdreg(HCLK, DWDataM, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN - assign HWRITE = DWriteM; - assign HSIZE = GrantData ? {1'b0, DSizeM} : ISize; + assign HWRITE = MemWriteM; + assign HSIZE = GrantData ? {1'b0, MemSizeM} : ISize; assign HBURST = 3'b000; // Single burst only supported; consider generalizing for cache fillsfHPROT assign HPROT = 4'b0011; // not used; see Section 3.7 - assign HTRANS = IReadF | DReadM | DWriteM ? 2'b10 : 2'b00; // NONSEQ if reading or writing, IDLE otherwise + assign HTRANS = InstrReadF | MemReadM | MemWriteM ? 2'b10 : 2'b00; // NONSEQ if reading or writing, IDLE otherwise assign HMASTLOCK = 0; // no locking supported // Route signals to Instruction and Data Caches // *** assumes AHBW = XLEN - assign IRData = HRDATAMasked; - assign IReady = HREADY & IReadF & ~GrantData; // maybe unused?*** - assign DRData = HRDATAMasked; + assign InstrRData = HRDATAMasked[31:0]; + assign IReady = HREADY & InstrReadF & ~GrantData; // maybe unused?*** + assign ReadDataW = HRDATAMasked; assign DReady = HREADY & GrantData; // ***unused? + + // State machines for stalls (probably can merge with FSM above***) + // Idle, DataBusy, InstrBusy. Stall while in busystate add suffixes + logic MemState, NextMemState, InstrState, NextInstrState; + flopr #(1) msreg(HCLK, ~HRESETn, NextMemState, MemState); + flopr #(1) isreg(HCLK, ~HRESETn, NextInstrState, InstrState); +/* always_ff @(posedge HCLK, negedge HRESETn) + if (~HRESETn) MemState <= 0; + else MemState <= NextMemState; */ + assign NextMemState = (MemState == 0 && InstrState == 0 && (MemReadM || MemWriteM)) || (MemState == 1 && ~MemAckW); + assign DataStall = NextMemState; +/* always_ff @(posedge HCLK, negedge HRESETn) + if (~HRESETn) InstrState <= 0; + else InstrState <= NextInstrState;*/ + + assign NextInstrState = (InstrState == 0 && MemState == 0 && (~MemReadM && ~MemWriteM && InstrReadF)) || + (InstrState == 1 && ~InstrAckD); + assign InstrStall = NextInstrState | MemState | NextMemState; // *** check this, explain better + // temporarily turn off stalls and check it works + //assign DataStall = 0; + //assign InstrStall = 0; + // stalls // Stall MEM stage if data is being accessed and bus isn't yet ready //assign DataStall = GrantData & ~HREADY; diff --git a/wally-pipelined/src/ebu/subwordread.sv b/wally-pipelined/src/ebu/subwordread.sv index 74b1e0aa7..352a33c05 100644 --- a/wally-pipelined/src/ebu/subwordread.sv +++ b/wally-pipelined/src/ebu/subwordread.sv @@ -28,9 +28,9 @@ module subwordread ( // from AHB Interface input logic [`XLEN-1:0] HRDATA, - input logic [31:0] HADDR, - input logic UnsignedLoadM, - input logic [2:0] HSIZE, + input logic [2:0] HADDRD, + //input logic UnsignedLoadM, + input logic [3:0] HSIZED, // to ifu/dmems output logic [`XLEN-1:0] HRDATAMasked ); @@ -42,7 +42,7 @@ module subwordread ( if (`XLEN == 64) begin // ByteMe mux always_comb - case(HADDR[2:0]) + case(HADDRD[2:0]) 3'b000: ByteM = HRDATA[7:0]; 3'b001: ByteM = HRDATA[15:8]; 3'b010: ByteM = HRDATA[23:16]; @@ -55,7 +55,7 @@ module subwordread ( // halfword mux always_comb - case(HADDR[2:1]) + case(HADDRD[2:1]) 2'b00: HalfwordM = HRDATA[15:0]; 2'b01: HalfwordM = HRDATA[31:16]; 2'b10: HalfwordM = HRDATA[47:32]; @@ -65,14 +65,14 @@ module subwordread ( logic [31:0] WordM; always_comb - case(HADDR[2]) + case(HADDRD[2]) 1'b0: WordM = HRDATA[31:0]; 1'b1: WordM = HRDATA[63:32]; endcase // sign extension always_comb - case({UnsignedLoadM, HSIZE[1:0]}) + case({HSIZED[3], HSIZED[1:0]}) // HSIZED[3] indicates unsigned load 3'b000: HRDATAMasked = {{56{ByteM[7]}}, ByteM}; // lb 3'b001: HRDATAMasked = {{48{HalfwordM[15]}}, HalfwordM[15:0]}; // lh 3'b010: HRDATAMasked = {{32{WordM[31]}}, WordM[31:0]}; // lw @@ -85,7 +85,7 @@ module subwordread ( end else begin // 32-bit // byte mux always_comb - case(HADDR[1:0]) + case(HADDRD[1:0]) 2'b00: ByteM = HRDATA[7:0]; 2'b01: ByteM = HRDATA[15:8]; 2'b10: ByteM = HRDATA[23:16]; @@ -94,14 +94,14 @@ module subwordread ( // halfword mux always_comb - case(HADDR[1]) + case(HADDRD[1]) 1'b0: HalfwordM = HRDATA[15:0]; 1'b1: HalfwordM = HRDATA[31:16]; endcase // sign extension always_comb - case({UnsignedLoadM, HSIZE[1:0]}) + case({HSIZED[3], HSIZED[1:0]}) 3'b000: HRDATAMasked = {{24{ByteM[7]}}, ByteM}; // lb 3'b001: HRDATAMasked = {{16{HalfwordM[15]}}, HalfwordM[15:0]}; // lh 3'b010: HRDATAMasked = HRDATA; // lw diff --git a/wally-pipelined/src/hazard/hazard.sv b/wally-pipelined/src/hazard/hazard.sv index 2fe0541a5..7c4afd6fe 100644 --- a/wally-pipelined/src/hazard/hazard.sv +++ b/wally-pipelined/src/hazard/hazard.sv @@ -34,12 +34,14 @@ module hazard( input logic LoadStallD, input logic InstrStall, DataStall, // Stall outputs - output logic StallF, StallD, FlushD, FlushE, FlushM, FlushW + output logic StallF, StallD, StallE, StallM, StallW, + output logic FlushD, FlushE, FlushM, FlushW ); logic BranchFlushDE; - logic StallDCause, StallFCause, StallWCause; - + logic StallFCause, StallDCause, StallECause, StallMCause, StallWCause; + logic FirstUnstalledD, FirstUnstalledE, FirstUnstalledM, FirstUnstalledW; + // stalls and flushes // loads: stall for one cycle if the subsequent instruction depends on the load // branches and jumps: flush the next two instructions if the branch is taken in EXE @@ -54,14 +56,28 @@ module hazard( assign BranchFlushDE = PCSrcE | RetM | TrapM; - assign StallDCause = LoadStallD; - assign StallFCause = InstrStall | CSRWritePendingDEM; - assign StallWCause = DataStall; // *** not yet used + assign StallFCause = InstrStall | CSRWritePendingDEM; // stall at fetch if unable to get the instruction, + // or if a CSR will be written and may change system behavior + assign StallDCause = LoadStallD; // stall in decode if instruction is a load dependent on previous + assign StallECause = 0; + assign StallMCause = 0; // sDataStall; // not yet used*** + assign StallWCause = DataStall; - assign StallD = StallDCause; + // Each stage stalls if the next stage is stalled or there is a cause to stall this stage. assign StallF = StallD | StallFCause; - assign FlushD = BranchFlushDE | StallFCause; // PCSrcE |InstrStall | CSRWritePendingDEM | RetM | TrapM; - assign FlushE = StallD | BranchFlushDE; //LoadStallD | PCSrcE | RetM | TrapM; - assign FlushM = RetM | TrapM; - assign FlushW = TrapM; + assign StallD = StallE | StallDCause; + assign StallE = StallM | StallECause; + assign StallM = StallW | StallMCause; + assign StallW = StallWCause; + + assign FirstUnstalledD = (~StallD & StallF); + assign FirstUnstalledE = (~StallE & StallD); + assign FirstUnstalledM = (~StallM & StallE); + assign FirstUnstalledW = (~StallW & StallM);; + + // Each stage flushes if the previous stage is the last one stalled (for cause) or the system has reason to flush + assign FlushD = FirstUnstalledD || BranchFlushDE; // PCSrcE |InstrStall | CSRWritePendingDEM | RetM | TrapM; + assign FlushE = FirstUnstalledE || BranchFlushDE; //LoadStallD | PCSrcE | RetM | TrapM; + assign FlushM = FirstUnstalledM || RetM || TrapM; + assign FlushW = FirstUnstalledW | TrapM; endmodule diff --git a/wally-pipelined/src/ieu/controller.sv b/wally-pipelined/src/ieu/controller.sv index 5a62f0147..1b480dec3 100644 --- a/wally-pipelined/src/ieu/controller.sv +++ b/wally-pipelined/src/ieu/controller.sv @@ -37,7 +37,7 @@ module controller( input logic IllegalIEUInstrFaultD, output logic IllegalBaseInstrFaultD, // Execute stage control signals - input logic FlushE, + input logic StallE, FlushE, input logic [2:0] FlagsE, output logic PCSrcE, // for datapath and Hazard Unit output logic [4:0] ALUControlE, @@ -45,14 +45,14 @@ module controller( output logic TargetSrcE, output logic MemReadE, // for Hazard Unit // Memory stage control signals - input logic FlushM, + input logic StallM, FlushM, input logic DataMisalignedM, output logic [1:0] MemRWM, output logic CSRWriteM, PrivilegedM, output logic [2:0] Funct3M, output logic RegWriteM, // for Hazard Unit // Writeback stage control signals - input logic FlushW, + input logic StallW, FlushW, output logic RegWriteW, // for datapath and Hazard Unit output logic [1:0] ResultSrcW, output logic InstrValidW, @@ -132,7 +132,7 @@ module controller( endcase // Execute stage pipeline control register and logic - floprc #(21) controlregE(clk, reset, FlushE, + flopenrc #(21) controlregE(clk, reset, FlushE, ~StallE, {RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, TargetSrcD, CSRWriteD, PrivilegedD, Funct3D, 1'b1}, {RegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, TargetSrcE, CSRWriteE, PrivilegedE, Funct3E, InstrValidE}); @@ -155,12 +155,12 @@ module controller( assign MemReadE = MemRWE[1]; // Memory stage pipeline control register - floprc #(11) controlregM(clk, reset, FlushM, + flopenrc #(11) controlregM(clk, reset, FlushM, ~StallM, {RegWriteE, ResultSrcE, MemRWE, CSRWriteE, PrivilegedE, Funct3E, InstrValidE}, {RegWriteM, ResultSrcM, MemRWM, CSRWriteM, PrivilegedM, Funct3M, InstrValidM}); // Writeback stage pipeline control register - floprc #(4) controlregW(clk, reset, FlushW, + flopenrc #(4) controlregW(clk, reset, FlushW, ~StallW, {RegWriteM, ResultSrcM, InstrValidM}, {RegWriteW, ResultSrcW, InstrValidW}); diff --git a/wally-pipelined/src/ieu/datapath.sv b/wally-pipelined/src/ieu/datapath.sv index bb02bad53..0147c487d 100644 --- a/wally-pipelined/src/ieu/datapath.sv +++ b/wally-pipelined/src/ieu/datapath.sv @@ -32,7 +32,7 @@ module datapath ( input logic [2:0] ImmSrcD, input logic [31:0] InstrD, // Execute stage signals - input logic FlushE, + input logic StallE, FlushE, input logic [1:0] ForwardAE, ForwardBE, input logic PCSrcE, input logic [4:0] ALUControlE, @@ -42,7 +42,7 @@ module datapath ( output logic [2:0] FlagsE, output logic [`XLEN-1:0] PCTargetE, // Memory stage signals - input logic FlushM, + input logic StallM, FlushM, input logic [2:0] Funct3M, input logic [`XLEN-1:0] CSRReadValW, input logic [`XLEN-1:0] ReadDataW, @@ -50,7 +50,7 @@ module datapath ( output logic [`XLEN-1:0] SrcAM, output logic [`XLEN-1:0] WriteDataM, MemAdrM, // Writeback stage signals - input logic FlushW, + input logic StallW, FlushW, input logic RegWriteW, input logic [1:0] ResultSrcW, input logic [`XLEN-1:0] PCLinkW, @@ -85,12 +85,12 @@ module datapath ( extend ext(.InstrD(InstrD[31:7]), .*); // Execute stage pipeline register and logic - floprc #(`XLEN) RD1EReg(clk, reset, FlushE, RD1D, RD1E); - floprc #(`XLEN) RD2EReg(clk, reset, FlushE, RD2D, RD2E); - floprc #(`XLEN) ExtImmEReg(clk, reset, FlushE, ExtImmD, ExtImmE); - floprc #(5) Rs1EReg(clk, reset, FlushE, Rs1D, Rs1E); - floprc #(5) Rs2EReg(clk, reset, FlushE, Rs2D, Rs2E); - floprc #(5) RdEReg(clk, reset, FlushE, RdD, RdE); + flopenrc #(`XLEN) RD1EReg(clk, reset, FlushE, ~StallE, RD1D, RD1E); + flopenrc #(`XLEN) RD2EReg(clk, reset, FlushE, ~StallE, RD2D, RD2E); + flopenrc #(`XLEN) ExtImmEReg(clk, reset, FlushE, ~StallE, ExtImmD, ExtImmE); + flopenrc #(5) Rs1EReg(clk, reset, FlushE, ~StallE, Rs1D, Rs1E); + flopenrc #(5) Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs2E); + flopenrc #(5) RdEReg(clk, reset, FlushE, ~StallE, RdD, RdE); mux3 #(`XLEN) faemux(RD1E, ResultW, ALUResultM, ForwardAE, PreSrcAE); mux3 #(`XLEN) fbemux(RD2E, ResultW, ALUResultM, ForwardBE, WriteDataE); @@ -101,15 +101,15 @@ module datapath ( assign PCTargetE = ExtImmE + TargetBaseE; // Memory stage pipeline register - floprc #(`XLEN) SrcAMReg(clk, reset, FlushM, SrcAE, SrcAM); - floprc #(`XLEN) ALUResultMReg(clk, reset, FlushM, ALUResultE, ALUResultM); + flopenrc #(`XLEN) SrcAMReg(clk, reset, FlushM, ~StallM, SrcAE, SrcAM); + flopenrc #(`XLEN) ALUResultMReg(clk, reset, FlushM, ~StallM, ALUResultE, ALUResultM); assign MemAdrM = ALUResultM; - floprc #(`XLEN) WriteDataMReg(clk, reset, FlushM, WriteDataE, WriteDataM); - floprc #(5) RdMEg(clk, reset, FlushM, RdE, RdM); + flopenrc #(`XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, WriteDataE, WriteDataM); + flopenrc #(5) RdMEg(clk, reset, FlushM, ~StallM, RdE, RdM); // Writeback stage pipeline register and logic - floprc #(`XLEN) ALUResultWReg(clk, reset, FlushW, ALUResultM, ALUResultW); - floprc #(5) RdWEg(clk, reset, FlushW, RdM, RdW); + flopenrc #(`XLEN) ALUResultWReg(clk, reset, FlushW, ~StallW, ALUResultM, ALUResultW); + flopenrc #(5) RdWEg(clk, reset, FlushW, ~StallW, RdM, RdW); mux4 #(`XLEN) resultmux(ALUResultW, ReadDataW, PCLinkW, CSRReadValW, ResultSrcW, ResultW); endmodule diff --git a/wally-pipelined/src/ieu/forward.sv b/wally-pipelined/src/ieu/forward.sv index 6dcd5154f..166ebe23a 100644 --- a/wally-pipelined/src/ieu/forward.sv +++ b/wally-pipelined/src/ieu/forward.sv @@ -30,7 +30,7 @@ module forward( input logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW, input logic MemReadE, input logic RegWriteM, RegWriteW, - // Forwaring controls + // Forwarding controls output logic [1:0] ForwardAE, ForwardBE, output logic LoadStallD ); diff --git a/wally-pipelined/src/ieu/ieu.sv b/wally-pipelined/src/ieu/ieu.sv index 7ed4bdffa..2b1e7d415 100644 --- a/wally-pipelined/src/ieu/ieu.sv +++ b/wally-pipelined/src/ieu/ieu.sv @@ -47,7 +47,8 @@ module ieu ( input logic [`XLEN-1:0] PCLinkW, output logic InstrValidW, // hazards - input logic StallD, FlushD, FlushE, FlushM, FlushW, + input logic StallF, StallD, StallE, StallM, StallW, + input logic FlushD, FlushE, FlushM, FlushW, input logic RetM, TrapM, output logic LoadStallD, output logic PCSrcE, diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index 3a12b330a..86f96b95c 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -28,13 +28,15 @@ module ifu ( input logic clk, reset, - input logic StallF, StallD, FlushD, FlushE, FlushM, FlushW, + input logic StallF, StallD, StallE, StallM, StallW, + input logic FlushD, FlushE, FlushM, FlushW, // Fetch input logic [31:0] InstrF, output logic [`XLEN-1:0] PCF, output logic [`XLEN-1:0] InstrPAdrF, + output logic InstrReadF, // Decode - output logic InstrStall, + //output logic InstrStall, // Execute input logic PCSrcE, input logic [`XLEN-1:0] PCTargetE, @@ -59,12 +61,12 @@ module ifu ( logic IllegalCompInstrD; logic [`XLEN-1:0] PCPlusUpperF, PCPlus2or4F, PCD, PCW, PCLinkD, PCLinkE, PCLinkM; logic CompressedF; - logic [31:0] InstrRawD, InstrE; + logic [31:0] InstrRawD, InstrE, InstrW; logic [31:0] nop = 32'h00000013; // instruction for NOP // *** put memory interface on here, InstrF becomes output - assign InstrStall = 0; // *** assign InstrPAdrF = PCF; // *** no MMU + assign InstrReadF = ~StallD; assign PrivilegedChangePCM = RetM | TrapM; @@ -107,25 +109,26 @@ module ifu ( // pipeline misaligned faults to M stage assign BranchMisalignedFaultE = misaligned & PCSrcE; // E-stage (Branch/Jump) misaligned - flopr #(1) InstrMisalginedReg(clk, reset, BranchMisalignedFaultE, BranchMisalignedFaultM); - flopr #(`XLEN) InstrMisalignedAdrReg(clk, reset, PCNextF, InstrMisalignedAdrM); + flopenr #(1) InstrMisalginedReg(clk, reset, ~StallM, BranchMisalignedFaultE, BranchMisalignedFaultM); + flopenr #(`XLEN) InstrMisalignedAdrReg(clk, reset, ~StallM, PCNextF, InstrMisalignedAdrM); assign TrapMisalignedFaultM = misaligned & PrivilegedChangePCM; assign InstrMisalignedFaultM = BranchMisalignedFaultM; // | TrapMisalignedFaultM; *** put this back in without causing a cyclic path - flopr #(32) InstrEReg(clk, reset, FlushE ? nop : InstrD, InstrE); - flopr #(32) InstrMReg(clk, reset, FlushM ? nop : InstrE, InstrM); - flopr #(`XLEN) PCEReg(clk, reset, PCD, PCE); - flopr #(`XLEN) PCMReg(clk, reset, PCE, PCM); - flopr #(`XLEN) PCWReg(clk, reset, PCM, PCW); // *** probably not needed; delete later + flopenr #(32) InstrEReg(clk, reset, ~StallE, FlushE ? nop : InstrD, InstrE); + flopenr #(32) InstrMReg(clk, reset, ~StallM, FlushM ? nop : InstrE, InstrM); + flopenr #(32) InstrWReg(clk, reset, ~StallW, FlushW ? nop : InstrM, InstrW); // just for testbench, delete later + flopenr #(`XLEN) PCEReg(clk, reset, ~StallE, PCD, PCE); + flopenr #(`XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM); + flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW); // *** probably not needed; delete later // seems like there should be a lower-cost way of doing this PC+2 or PC+4 for JAL. // either have ALU compute PC+2/4 and feed into ALUResult input of ResultMux or // have dedicated adder in Mem stage based on PCM + 2 or 4 // *** redo this - flopr #(`XLEN) PCPDReg(clk, reset, PCPlus2or4F, PCLinkD); - flopr #(`XLEN) PCPEReg(clk, reset, PCLinkD, PCLinkE); - flopr #(`XLEN) PCPMReg(clk, reset, PCLinkE, PCLinkM); - flopr #(`XLEN) PCPWReg(clk, reset, PCLinkM, PCLinkW); + flopenr #(`XLEN) PCPDReg(clk, reset, ~StallD, PCPlus2or4F, PCLinkD); + flopenr #(`XLEN) PCPEReg(clk, reset, ~StallE, PCLinkD, PCLinkE); + flopenr #(`XLEN) PCPMReg(clk, reset, ~StallM, PCLinkE, PCLinkM); + flopenr #(`XLEN) PCPWReg(clk, reset, ~StallW, PCLinkM, PCLinkW); endmodule diff --git a/wally-pipelined/src/uncore/dtim.sv b/wally-pipelined/src/uncore/dtim.sv index 6a49fcf59..611183605 100644 --- a/wally-pipelined/src/uncore/dtim.sv +++ b/wally-pipelined/src/uncore/dtim.sv @@ -36,13 +36,15 @@ module dtim ( ); logic [`XLEN-1:0] RAM[0:65535]; + logic [18:0] HWADDR; + // logic [`XLEN-1:0] write; logic [15:0] entry; logic memread, memwrite; logic [3:0] busycount; // busy FSM to extend READY signal - always_ff @(posedge HCLK, negedge HRESETn) +/* always_ff @(posedge HCLK, negedge HRESETn) if (~HRESETn) begin HREADYTim <= 1; end else begin @@ -52,25 +54,34 @@ module dtim ( end else if (~HREADYTim) begin if (busycount == 0) begin // TIM latency, for testing purposes HREADYTim <= 1; - end else + end else begin busycount <= busycount + 1; + end end + end*/ + always_ff @(posedge HCLK, negedge HRESETn) + if (~HRESETn) begin + HREADYTim <= 0; + end else begin + HREADYTim <= HSELTim; // always respond one cycle later end - + assign memread = MemRWtim[1]; assign memwrite = MemRWtim[0]; +// always_ff @(posedge HCLK) +// memwrite <= MemRWtim[0]; // delay memwrite to write phase assign HRESPTim = 0; // OK // assign HREADYTim = 1; // Respond immediately; *** extend this // word aligned reads - generate +/* generate if (`XLEN==64) assign #2 entry = HADDR[18:3]; else assign #2 entry = HADDR[17:2]; - endgenerate - assign HREADTim = RAM[entry]; + endgenerate */ +// assign HREADTim = RAM[entry]; // assign HREADTim = HREADYTim ? RAM[entry] : ~RAM[entry]; // *** temproary mess up read value before ready // write each byte based on the byte mask @@ -105,17 +116,34 @@ module dtim ( if (memwrite) RAM[HADDR[17:2]] <= write; end endgenerate */ + + // Model memory read and write + // If write occurs at end of phase (rising edge of clock), + // then read of same address on next cycle won't work. Would need to bypass. + // Faking for now with negedge clock write. Will need to adjust this to + // match capabilities of FPGA or actual chip RAM. + // Also, writes occuring later than reads throws off single ported RAM that + // might be asked to write on one instruction and read on the next and would need + // to stall because both accesses happen on same cycle with AHB delay + generate - if (`XLEN == 64) + if (`XLEN == 64) begin + always_ff @(negedge HCLK) + if (memwrite) RAM[HWADDR[17:3]] <= HWDATA; always_ff @(posedge HCLK) begin - if (memwrite) RAM[HADDR[17:3]] <= HWDATA; -// HREADTim <= RAM[HADDR[17:3]]; + //if (memwrite) RAM[HADDR[17:3]] <= HWDATA; + HWADDR <= HADDR; + HREADTim <= RAM[HADDR[17:3]]; end - else + end else begin + always_ff @(negedge HCLK) + if (memwrite) RAM[HWADDR[17:2]] <= HWDATA; always_ff @(posedge HCLK) begin - if (memwrite) RAM[HADDR[17:2]] <= HWDATA; -// HREADTim <= RAM[HADDR[17:2]]; + //if (memwrite) RAM[HADDR[17:2]] <= HWDATA; + HWADDR <= HADDR; + HREADTim <= RAM[HADDR[17:2]]; end + end endgenerate endmodule diff --git a/wally-pipelined/src/uncore/subwordwrite.sv b/wally-pipelined/src/uncore/subwordwrite.sv index 68c2b0e47..b1e8d683f 100644 --- a/wally-pipelined/src/uncore/subwordwrite.sv +++ b/wally-pipelined/src/uncore/subwordwrite.sv @@ -27,37 +27,35 @@ module subwordwrite ( input logic [`XLEN-1:0] HRDATA, - input logic [31:0] HADDR, - input logic [2:0] HSIZE, + input logic [2:0] HADDRD, + input logic [3:0] HSIZED, input logic [`XLEN-1:0] HWDATAIN, output logic [`XLEN-1:0] HWDATA ); - logic [7:0] ByteM; // *** declare locally to generate as either 4 or 8 bits - logic [15:0] HalfwordM; logic [`XLEN-1:0] WriteDataSubwordDuplicated; - logic [7:0] ByteMaskM; generate if (`XLEN == 64) begin + logic [7:0] ByteMaskM; // Compute write mask always_comb - case(HSIZE[1:0]) - 2'b00: begin ByteMaskM = 8'b00000000; ByteMaskM[HADDR[2:0]] = 1; end // sb - 2'b01: case (HADDR[2:1]) + case(HSIZED[1:0]) + 2'b00: begin ByteMaskM = 8'b00000000; ByteMaskM[HADDRD[2:0]] = 1; end // sb + 2'b01: case (HADDRD[2:1]) 2'b00: ByteMaskM = 8'b00000011; 2'b01: ByteMaskM = 8'b00001100; 2'b10: ByteMaskM = 8'b00110000; 2'b11: ByteMaskM = 8'b11000000; endcase - 2'b10: if (HADDR[2]) ByteMaskM = 8'b11110000; + 2'b10: if (HADDRD[2]) ByteMaskM = 8'b11110000; else ByteMaskM = 8'b00001111; 2'b11: ByteMaskM = 8'b11111111; endcase // Handle subword writes always_comb - case(HSIZE[1:0]) + case(HSIZED[1:0]) 2'b00: WriteDataSubwordDuplicated = {8{HWDATAIN[7:0]}}; // sb 2'b01: WriteDataSubwordDuplicated = {4{HWDATAIN[15:0]}}; // sh 2'b10: WriteDataSubwordDuplicated = {2{HWDATAIN[31:0]}}; // sw @@ -77,19 +75,20 @@ module subwordwrite ( end end else begin // 32-bit + logic [3:0] ByteMaskM; // Compute write mask always_comb - case(HSIZE[1:0]) - 2'b00: begin ByteMaskM = 8'b0000; ByteMaskM[{1'b0, HADDR[1:0]}] = 1; end // sb - 2'b01: if (HADDR[1]) ByteMaskM = 8'b1100; - else ByteMaskM = 8'b0011; - 2'b10: ByteMaskM = 8'b1111; - default: ByteMaskM = 8'b111; // shouldn't happen + case(HSIZED[1:0]) + 2'b00: begin ByteMaskM = 4'b0000; ByteMaskM[HADDRD[1:0]] = 1; end // sb + 2'b01: if (HADDRD[1]) ByteMaskM = 4'b1100; + else ByteMaskM = 4'b0011; + 2'b10: ByteMaskM = 4'b1111; + default: ByteMaskM = 4'b111; // shouldn't happen endcase // Handle subword writes always_comb - case(HSIZE[1:0]) + case(HSIZED[1:0]) 2'b00: WriteDataSubwordDuplicated = {4{HWDATAIN[7:0]}}; // sb 2'b01: WriteDataSubwordDuplicated = {2{HWDATAIN[15:0]}}; // sh 2'b10: WriteDataSubwordDuplicated = HWDATAIN; // sw diff --git a/wally-pipelined/src/uncore/uartPC16550D.sv b/wally-pipelined/src/uncore/uartPC16550D.sv index ec3e25227..051bcef47 100644 --- a/wally-pipelined/src/uncore/uartPC16550D.sv +++ b/wally-pipelined/src/uncore/uartPC16550D.sv @@ -6,6 +6,7 @@ // // Purpose: Universial Asynchronous Receiver/ Transmitter with FIFOs // Emulates interface of Texas Instruments PC16550D +// https://media.digikey.com/pdf/Data%20Sheets/Texas%20Instruments%20PDFs/PC16550D.pdf // Compatible with UART in Imperas Virtio model *** // // Compatible with most of PC16550D with the following known exceptions: diff --git a/wally-pipelined/src/uncore/uncore.sv b/wally-pipelined/src/uncore/uncore.sv index ada1eb93c..2d12d2b50 100644 --- a/wally-pipelined/src/uncore/uncore.sv +++ b/wally-pipelined/src/uncore/uncore.sv @@ -43,6 +43,10 @@ module uncore ( input logic HREADYEXT, HRESPEXT, output logic [`AHBW-1:0] HRDATA, output logic HREADY, HRESP, + // delayed signals + input logic [2:0] HADDRD, + input logic [3:0] HSIZED, + input logic HWRITED, // bus interface output logic DataAccessFaultM, // peripheral pins @@ -71,7 +75,7 @@ module uncore ( assign HSELUART = PreHSELUART && (HSIZE == 3'b000); // only byte writes to UART are supported // Enable read or write based on decoded address - assign MemRW = {~HWRITE, HWRITE}; + assign MemRW = {~HWRITE, HWRITED}; assign MemRWtim = MemRW & {2{HSELTim}}; assign MemRWclint = MemRW & {2{HSELCLINT}}; assign MemRWgpio = MemRW & {2{HSELGPIO}}; diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 408045e23..c491bfc23 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -45,11 +45,16 @@ module wallypipelinedhart ( output logic [2:0] HBURST, output logic [3:0] HPROT, output logic [1:0] HTRANS, - output logic HMASTLOCK + output logic HMASTLOCK, + // Delayed signals for subword write + output logic [2:0] HADDRD, + output logic [3:0] HSIZED, + output logic HWRITED ); - logic [1:0] ForwardAE, ForwardBE; - logic StallF, StallD, FlushD, FlushE, FlushM, FlushW; +// logic [1:0] ForwardAE, ForwardBE; + logic StallF, StallD, StallE, StallM, StallW; + logic FlushD, FlushE, FlushM, FlushW; logic RetM, TrapM; // new signals that must connect through DP @@ -79,26 +84,34 @@ module wallypipelinedhart ( logic FloatRegWriteW; // bus interface to dmem - logic [1:0] MemRWAlignedM; - logic [2:0] Funct3M; + logic MemReadM, MemWriteM; + logic [2:0] Funct3M; logic [`XLEN-1:0] MemAdrM, MemPAdrM, WriteDataM; - logic [`XLEN-1:0] ReadDataM, ReadDataW; + logic [`XLEN-1:0] ReadDataW; logic [`XLEN-1:0] InstrPAdrF; + logic InstrReadF; logic DataStall, InstrStall; logic InstrAckD, MemAckW; ifu ifu(.*); // instruction fetch unit: PC, branch prediction, instruction cache ieu ieu(.*); // inteber execution unit: integer register file, datapath and controller - dmem dmem(/*.Funct3M(InstrM[14:12]),*/ .*); // data cache unit + dmem dmem(.*); // data cache unit - ahblite ebu( // *** make IRData InstrF - .IReadF(1'b1), .IRData(), //.IReady(), - .DReadM(MemRWAlignedM[1]), .DWriteM(MemRWAlignedM[0]), - .DSizeM(Funct3M[1:0]), .DRData(ReadDataM), //.DReady(), - .UnsignedLoadM(Funct3M[2]), +/* + ahblite ebu( + //.InstrReadF(1'b0), + .InstrRData(InstrF), // hook up InstrF later + .MemSizeM(Funct3M[1:0]), .UnsignedLoadM(Funct3M[2]), + .*); +*/ +// changing from this to the line above breaks the program. auipc at 104 fails; seems to be flushed. +// Would need to insertinstruction as InstrD, not InstrF + ahblite ebu( + .InstrReadF(1'b0), + .InstrRData(), // hook up InstrF later + .MemSizeM(Funct3M[1:0]), .UnsignedLoadM(Funct3M[2]), .*); - //assign InstrF = ReadDataM[31:0]; /* mdu mdu(.*); // multiply and divide unit diff --git a/wally-pipelined/src/wally/wallypipelinedsoc.sv b/wally-pipelined/src/wally/wallypipelinedsoc.sv index 9b0ed2456..bdb621726 100644 --- a/wally-pipelined/src/wally/wallypipelinedsoc.sv +++ b/wally-pipelined/src/wally/wallypipelinedsoc.sv @@ -64,6 +64,9 @@ module wallypipelinedsoc ( logic InstrAccessFaultF, DataAccessFaultM; logic TimerIntM, SwIntM; // from CLINT logic ExtIntM = 0; // not yet connected + logic [2:0] HADDRD; + logic [3:0] HSIZED; + logic HWRITED; // instantiate processor and memories wallypipelinedhart hart(.*); diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index 67a896445..4f5a24ffc 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -35,7 +35,7 @@ module testbench(); logic [`XLEN-1:0] signature[0:10000]; logic [`XLEN-1:0] testadr; string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; - logic [31:0] InstrW; + //logic [31:0] InstrW; logic [`XLEN-1:0] meminit; string tests64ic[] = '{ @@ -75,7 +75,7 @@ string tests64iNOc[] = { "rv64i/I-MISALIGN_JMP-01","2000" }; string tests64i[] = '{ - "rv64i/I-LW-01", "4110", + "rv64i/I-ENDIANESS-01", "2010", "rv64i/I-ADD-01", "3000", "rv64i/I-ADDI-01", "3000", "rv64i/I-ADDIW-01", "3000", @@ -262,7 +262,7 @@ string tests32i[] = { // Track names of instructions instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE, dut.hart.ifu.InstrD, dut.hart.ifu.InstrE, - dut.hart.ifu.InstrM, InstrW, + dut.hart.ifu.InstrM, dut.hart.ifu.InstrW, InstrDName, InstrEName, InstrMName, InstrWName); // initialize tests @@ -368,11 +368,12 @@ module instrTrackerTB( input logic clk, reset, FlushE, input logic [31:0] InstrD, input logic [31:0] InstrE, InstrM, - output logic [31:0] InstrW, + input logic [31:0] InstrW, +// output logic [31:0] InstrW, output string InstrDName, InstrEName, InstrMName, InstrWName); // stage Instr to Writeback for visualization - flopr #(32) InstrWReg(clk, reset, InstrM, InstrW); + // flopr #(32) InstrWReg(clk, reset, InstrM, InstrW); instrNameDecTB ddec(InstrD, InstrDName); instrNameDecTB edec(InstrE, InstrEName); From 74bc4c0444f9dda05b7a3eb965a1a15ebd4ea17b Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 7 Feb 2021 23:28:21 -0500 Subject: [PATCH 02/33] Fixed lw by delaying read value by one cycle --- wally-pipelined/src/ebu/ahblite.sv | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv index 9d4e62be7..55f79cebc 100644 --- a/wally-pipelined/src/ebu/ahblite.sv +++ b/wally-pipelined/src/ebu/ahblite.sv @@ -32,6 +32,7 @@ module ahblite ( input logic clk, reset, + input logic StallW, FlushW, // Load control input logic UnsignedLoadM, // Signals from Instruction Cache @@ -71,7 +72,7 @@ module ahblite ( logic GrantData; logic [2:0] ISize; - logic [`AHBW-1:0] HRDATAMasked; + logic [`AHBW-1:0] HRDATAMasked, ReadDataM; logic IReady, DReady; // logic [3:0] HSIZED; // size delayed by one cycle for reads // logic [2:0] HADDRD; // address delayed for subword reads @@ -136,7 +137,9 @@ module ahblite ( // *** assumes AHBW = XLEN assign InstrRData = HRDATAMasked[31:0]; assign IReady = HREADY & InstrReadF & ~GrantData; // maybe unused?*** - assign ReadDataW = HRDATAMasked; +// assign ReadDataW = HRDATAMasked; + assign ReadDataM = HRDATAMasked; // changed from W to M dh 2/7/2021 + flopenrc #(`XLEN) ReadDataWReg(clk, reset, FlushW, ~StallW, ReadDataM, ReadDataW); assign DReady = HREADY & GrantData; // ***unused? From 842c374de929c0d23296996954fcbefd90572178 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 9 Feb 2021 11:02:17 -0500 Subject: [PATCH 03/33] Debugging instruction fetch --- wally-pipelined/regression/wally-pipelined.do | 11 ++++++----- wally-pipelined/src/ebu/ahblite.sv | 4 +++- wally-pipelined/src/ifu/ifu.sv | 6 +++++- wally-pipelined/src/wally/wallypipelinedhart.sv | 15 ++++++++------- wally-pipelined/testbench/testbench-imperas.sv | 10 +++++----- 5 files changed, 27 insertions(+), 19 deletions(-) diff --git a/wally-pipelined/regression/wally-pipelined.do b/wally-pipelined/regression/wally-pipelined.do index a88569f49..227ea3770 100644 --- a/wally-pipelined/regression/wally-pipelined.do +++ b/wally-pipelined/regression/wally-pipelined.do @@ -62,26 +62,27 @@ add wave -divider add wave -hex /testbench/dut/hart/ifu/PCF add wave -hex /testbench/dut/hart/ifu/InstrF add wave /testbench/InstrFName -#add wave -hex /testbench/dut/hart/ifu/PCD +add wave -hex /testbench/dut/hart/ifu/PCD add wave -hex /testbench/dut/hart/ifu/InstrD add wave /testbench/InstrDName add wave -divider -#add wave -hex /testbench/dut/hart/ifu/PCE -#add wave -hex /testbench/dut/hart/ifu/InstrE +add wave -hex /testbench/dut/hart/ifu/PCE +add wave -hex /testbench/dut/hart/ifu/InstrE add wave /testbench/InstrEName add wave -hex /testbench/dut/hart/ieu/dp/SrcAE add wave -hex /testbench/dut/hart/ieu/dp/SrcBE add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE add wave /testbench/dut/hart/ieu/dp/PCSrcE add wave -divider -#add wave -hex /testbench/dut/hart/ifu/PCM -#add wave -hex /testbench/dut/hart/ifu/InstrM +add wave -hex /testbench/dut/hart/ifu/PCM +add wave -hex /testbench/dut/hart/ifu/InstrM add wave /testbench/InstrMName add wave /testbench/dut/uncore/dtim/memwrite add wave -hex /testbench/dut/uncore/HADDR add wave -hex /testbench/dut/uncore/HWDATA add wave -divider add wave -hex /testbench/dut/hart/ifu/PCW +add wave -hex /testbench/dut/hart/ifu/InstrW add wave /testbench/InstrWName add wave /testbench/dut/hart/ieu/dp/RegWriteW add wave -hex /testbench/dut/hart/ieu/dp/ResultW diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv index 55f79cebc..ce54a21fe 100644 --- a/wally-pipelined/src/ebu/ahblite.sv +++ b/wally-pipelined/src/ebu/ahblite.sv @@ -38,6 +38,7 @@ module ahblite ( // Signals from Instruction Cache input logic [`XLEN-1:0] InstrPAdrF, // *** rename these to match block diagram input logic InstrReadF, + input logic ResolveBranchD, output logic [31:0] InstrRData, // output logic IReady, // Signals from Data Cache @@ -158,7 +159,8 @@ module ahblite ( else InstrState <= NextInstrState;*/ assign NextInstrState = (InstrState == 0 && MemState == 0 && (~MemReadM && ~MemWriteM && InstrReadF)) || - (InstrState == 1 && ~InstrAckD); + (InstrState == 1 && ~InstrAckD) || + (InstrState == 1 && ResolveBranchD); // dh 2/8/2021 fixing assign InstrStall = NextInstrState | MemState | NextMemState; // *** check this, explain better // temporarily turn off stalls and check it works //assign DataStall = 0; diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index 86f96b95c..6c16ebd8f 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -37,6 +37,7 @@ module ifu ( output logic InstrReadF, // Decode //output logic InstrStall, + output logic ResolveBranchD, // Execute input logic PCSrcE, input logic [`XLEN-1:0] PCTargetE, @@ -66,12 +67,15 @@ module ifu ( // *** put memory interface on here, InstrF becomes output assign InstrPAdrF = PCF; // *** no MMU - assign InstrReadF = ~StallD; + assign InstrReadF = ~StallD; // *** & ICacheMissF; add later assign PrivilegedChangePCM = RetM | TrapM; assign StallExceptResolveBranchesF = StallF & ~(PCSrcE | PrivilegedChangePCM); + // dh 2/8/2022 keep in instruction fetch stall mode when taking branch + flopr #(1) rbreg(clk, reset, (PCSrcE | PrivilegedChangePCM), ResolveBranchD); + mux3 #(`XLEN) pcmux(PCPlus2or4F, PCTargetE, PrivilegedNextPCM, {PrivilegedChangePCM, PCSrcE}, UnalignedPCNextF); assign PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment flopenl #(`XLEN) pcreg(clk, reset, ~StallExceptResolveBranchesF, PCNextF, `RESET_VECTOR, PCF); diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index c491bfc23..56c98d386 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -29,7 +29,7 @@ module wallypipelinedhart ( input logic clk, reset, output logic [`XLEN-1:0] PCF, - input logic [31:0] InstrF, +// input logic [31:0] InstrF, // Privileged input logic TimerIntM, ExtIntM, SwIntM, input logic InstrAccessFaultF, @@ -60,7 +60,7 @@ module wallypipelinedhart ( // new signals that must connect through DP logic CSRWriteM, PrivilegedM; logic [`XLEN-1:0] SrcAM; -// logic [31:0] InstrF; + logic [31:0] InstrF; logic [31:0] InstrD, InstrM; logic [`XLEN-1:0] PCE, PCM, PCLinkW; logic [`XLEN-1:0] PCTargetE; @@ -75,6 +75,7 @@ module wallypipelinedhart ( logic StoreMisalignedFaultM, StoreAccessFaultM; logic [`XLEN-1:0] InstrMisalignedAdrM; logic [`XLEN-1:0] zero = 0; + logic ResolveBranchD; logic PCSrcE; logic CSRWritePendingDEM; @@ -98,20 +99,20 @@ module wallypipelinedhart ( ieu ieu(.*); // inteber execution unit: integer register file, datapath and controller dmem dmem(.*); // data cache unit -/* + ahblite ebu( //.InstrReadF(1'b0), .InstrRData(InstrF), // hook up InstrF later .MemSizeM(Funct3M[1:0]), .UnsignedLoadM(Funct3M[2]), .*); -*/ + // changing from this to the line above breaks the program. auipc at 104 fails; seems to be flushed. // Would need to insertinstruction as InstrD, not InstrF - ahblite ebu( - .InstrReadF(1'b0), + /*ahblite ebu( + .InstrReadF(1'b0), .InstrRData(), // hook up InstrF later .MemSizeM(Funct3M[1:0]), .UnsignedLoadM(Funct3M[2]), - .*); + .*); */ /* mdu mdu(.*); // multiply and divide unit diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index 4f5a24ffc..98c176161 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -75,7 +75,6 @@ string tests64iNOc[] = { "rv64i/I-MISALIGN_JMP-01","2000" }; string tests64i[] = '{ - "rv64i/I-ENDIANESS-01", "2010", "rv64i/I-ADD-01", "3000", "rv64i/I-ADDI-01", "3000", "rv64i/I-ADDIW-01", "3000", @@ -261,9 +260,9 @@ string tests32i[] = { // Track names of instructions instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE, - dut.hart.ifu.InstrD, dut.hart.ifu.InstrE, + dut.hart.ifu.InstrF, dut.hart.ifu.InstrD, dut.hart.ifu.InstrE, dut.hart.ifu.InstrM, dut.hart.ifu.InstrW, - InstrDName, InstrEName, InstrMName, InstrWName); + InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); // initialize tests initial @@ -366,15 +365,16 @@ endmodule module instrTrackerTB( input logic clk, reset, FlushE, - input logic [31:0] InstrD, + input logic [31:0] InstrF, InstrD, input logic [31:0] InstrE, InstrM, input logic [31:0] InstrW, // output logic [31:0] InstrW, - output string InstrDName, InstrEName, InstrMName, InstrWName); + output string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); // stage Instr to Writeback for visualization // flopr #(32) InstrWReg(clk, reset, InstrM, InstrW); + instrNameDecTB fdec(InstrF, InstrFName); instrNameDecTB ddec(InstrD, InstrDName); instrNameDecTB edec(InstrE, InstrEName); instrNameDecTB mdec(InstrM, InstrMName); From b121b90b287025a195ae0884ef36cd60b96139f3 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 10 Feb 2021 01:43:54 -0500 Subject: [PATCH 04/33] Debugging bus interface. --- wally-pipelined/src/ebu/ahblite.sv | 7 +++++-- wally-pipelined/src/hazard/hazard.sv | 2 +- wally-pipelined/testbench/testbench-imperas.sv | 1 + 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv index ce54a21fe..368824288 100644 --- a/wally-pipelined/src/ebu/ahblite.sv +++ b/wally-pipelined/src/ebu/ahblite.sv @@ -110,6 +110,7 @@ module ahblite ( if (MemReadM) NextAdrState = MEMREAD; else if (MemWriteM) NextAdrState = MEMWRITE; else if (InstrReadF) NextAdrState = INSTRREAD; +// else if (1) NextAdrState = INSTRREAD; // dm 2/9/2021 testing else NextAdrState = IDLE; // Generate acknowledges based on bus state and ready @@ -159,8 +160,10 @@ module ahblite ( else InstrState <= NextInstrState;*/ assign NextInstrState = (InstrState == 0 && MemState == 0 && (~MemReadM && ~MemWriteM && InstrReadF)) || - (InstrState == 1 && ~InstrAckD) || - (InstrState == 1 && ResolveBranchD); // dh 2/8/2021 fixing + (InstrState == 1 && ~InstrAckD) || + (InstrState == 1 && ResolveBranchD); // dh 2/8/2021 fixing; delete this later +/* assign NextInstrState = (InstrState == 0 && MemState == 0 && (~MemReadM && ~MemWriteM)) || + (InstrState == 1 && ~InstrAckD); // *** removed InstrReadF above dh 2/9/20 */ assign InstrStall = NextInstrState | MemState | NextMemState; // *** check this, explain better // temporarily turn off stalls and check it works //assign DataStall = 0; diff --git a/wally-pipelined/src/hazard/hazard.sv b/wally-pipelined/src/hazard/hazard.sv index 7c4afd6fe..88d78ee47 100644 --- a/wally-pipelined/src/hazard/hazard.sv +++ b/wally-pipelined/src/hazard/hazard.sv @@ -61,7 +61,7 @@ module hazard( assign StallDCause = LoadStallD; // stall in decode if instruction is a load dependent on previous assign StallECause = 0; assign StallMCause = 0; // sDataStall; // not yet used*** - assign StallWCause = DataStall; + assign StallWCause = DataStall; // | InstrStall; // Each stage stalls if the next stage is stalled or there is a cause to stall this stage. assign StallF = StallD | StallFCause; diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index 98c176161..cad2d68d2 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -75,6 +75,7 @@ string tests64iNOc[] = { "rv64i/I-MISALIGN_JMP-01","2000" }; string tests64i[] = '{ + "rv64i/I-ENDIANESS-01", "2010", "rv64i/I-ADD-01", "3000", "rv64i/I-ADDI-01", "3000", "rv64i/I-ADDIW-01", "3000", From af3a888cdee792515d5d7fb1a6b537da249908ca Mon Sep 17 00:00:00 2001 From: Teo Ene Date: Fri, 12 Feb 2021 16:08:34 -0600 Subject: [PATCH 05/33] Removed riscv-o3 module --- .gitmodules | 3 --- riscv-o3 | 1 - 2 files changed, 4 deletions(-) delete mode 160000 riscv-o3 diff --git a/.gitmodules b/.gitmodules index e406bcfa5..22f34ffd0 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,6 +1,3 @@ -[submodule "riscv-o3"] - path = riscv-o3 - url = git@github.com:stineje/riscv-o3.git [submodule "sky130/sky130_osu_sc_t12"] path = sky130/sky130_osu_sc_t12 url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12/ diff --git a/riscv-o3 b/riscv-o3 deleted file mode 160000 index afb27bd55..000000000 --- a/riscv-o3 +++ /dev/null @@ -1 +0,0 @@ -Subproject commit afb27bd558a9b6fabb6b768ae81ef122b4db9eea From eab780afb99e919586bfb65309a3745125480dea Mon Sep 17 00:00:00 2001 From: Teo Ene Date: Fri, 12 Feb 2021 21:49:42 -0600 Subject: [PATCH 08/33] - Cleaned up unnecessary files - Pulled updates for std cells - Fixed typo that prevented easy switching between standard cell variants - Fixed asynchronous reset paths from not being flagged as false --- sky130/sky130_osu_sc_t12 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sky130/sky130_osu_sc_t12 b/sky130/sky130_osu_sc_t12 index 87ca77795..f60f2d039 160000 --- a/sky130/sky130_osu_sc_t12 +++ b/sky130/sky130_osu_sc_t12 @@ -1 +1 @@ -Subproject commit 87ca77795004bea5525b25badd7ec36cbc8222e1 +Subproject commit f60f2d0395053c4df362a97d7e2099721b6face6 From bd99a5613a84e534cda959ebca122225b8a32903 Mon Sep 17 00:00:00 2001 From: Teo Ene Date: Sun, 14 Feb 2021 09:05:41 -0600 Subject: [PATCH 13/33] sky130 18T and 15T cell libraries removed Upon noticing their size, concerns were raised about available drive space. As 12T is the main implementation focus, the decision was made to remove 15T and 18T. Apologies if any were interested in implementing the processor across multiple standard cell libraries for comparison. --- .gitmodules | 6 ------ sky130/sky130_osu_sc_t15 | 1 - sky130/sky130_osu_sc_t18 | 1 - 3 files changed, 8 deletions(-) delete mode 160000 sky130/sky130_osu_sc_t15 delete mode 160000 sky130/sky130_osu_sc_t18 diff --git a/.gitmodules b/.gitmodules index 22f34ffd0..65e1e71c9 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,9 +1,3 @@ [submodule "sky130/sky130_osu_sc_t12"] path = sky130/sky130_osu_sc_t12 url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12/ -[submodule "sky130/sky130_osu_sc_t15"] - path = sky130/sky130_osu_sc_t15 - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t15/ -[submodule "sky130/sky130_osu_sc_t18"] - path = sky130/sky130_osu_sc_t18 - url = https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t18/ diff --git a/sky130/sky130_osu_sc_t15 b/sky130/sky130_osu_sc_t15 deleted file mode 160000 index dae3c2282..000000000 --- a/sky130/sky130_osu_sc_t15 +++ /dev/null @@ -1 +0,0 @@ -Subproject commit dae3c2282e10d72f57af61d1dd73a1b0aead63f9 diff --git a/sky130/sky130_osu_sc_t18 b/sky130/sky130_osu_sc_t18 deleted file mode 160000 index 6c20402bf..000000000 --- a/sky130/sky130_osu_sc_t18 +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 6c20402bf853e6bf3985fce49fe88ca25502cc63 From cc42655789b68f14a819ce76023ded6940a311b5 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 15 Feb 2021 10:10:50 -0500 Subject: [PATCH 15/33] More memory interface, ALU testgen --- wally-pipelined/src/ebu/ahblite.sv | 127 ++++++++++----- wally-pipelined/src/generic/flop.sv | 10 ++ wally-pipelined/src/hazard/hazard.sv | 4 +- wally-pipelined/src/ifu/ifu.sv | 10 +- wally-pipelined/src/privileged/csr.sv | 2 +- wally-pipelined/src/privileged/csrsr.sv | 4 +- wally-pipelined/src/privileged/privileged.sv | 10 +- wally-pipelined/src/uncore/dtim.sv | 81 +++------ ...=> testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py} | 37 ++++- .../testgen/testgen-SLL-SRL-SRA.py | 154 ++++++++++++++++++ 10 files changed, 317 insertions(+), 122 deletions(-) rename wally-pipelined/testgen/{testgen-ADD-SUB.py => testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py} (82%) create mode 100755 wally-pipelined/testgen/testgen-SLL-SRL-SRA.py diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv index 368824288..e917b6680 100644 --- a/wally-pipelined/src/ebu/ahblite.sv +++ b/wally-pipelined/src/ebu/ahblite.sv @@ -38,9 +38,8 @@ module ahblite ( // Signals from Instruction Cache input logic [`XLEN-1:0] InstrPAdrF, // *** rename these to match block diagram input logic InstrReadF, - input logic ResolveBranchD, +// input logic ResolveBranchD, output logic [31:0] InstrRData, -// output logic IReady, // Signals from Data Cache input logic [`XLEN-1:0] MemPAdrM, input logic MemReadM, MemWriteM, @@ -48,7 +47,6 @@ module ahblite ( input logic [1:0] MemSizeM, // Return from bus output logic [`XLEN-1:0] ReadDataW, -// output logic DReady, // AHB-Lite external signals input logic [`AHBW-1:0] HRDATA, input logic HREADY, HRESP, @@ -61,14 +59,12 @@ module ahblite ( output logic [3:0] HPROT, output logic [1:0] HTRANS, output logic HMASTLOCK, - // Delayed signals for subword write + // Delayed signals for writes output logic [2:0] HADDRD, output logic [3:0] HSIZED, output logic HWRITED, - // Acknowledge - output logic InstrAckD, MemAckW, // Stalls - output logic InstrStall, DataStall + output logic InstrStall,/*InstrUpdate, */DataStall ); logic GrantData; @@ -81,12 +77,61 @@ module ahblite ( assign HCLK = clk; assign HRESETn = ~reset; - // Arbitrate requests by giving data priority over instructions - assign GrantData = MemReadM | MemWriteM; - // *** initially support HABW = XLEN // track bus state + // Data accesses have priority over instructions. However, if a data access comes + // while an instruction read is occuring, the instruction read finishes before + // the data access can take place. + typedef enum {IDLE, MEMREAD, MEMWRITE, INSTRREAD, INSTRREADMEMPENDING} statetype; + statetype BusState, NextBusState; + + always_ff @(posedge HCLK, negedge HRESETn) + if (~HRESETn) BusState <= #1 IDLE; + else BusState <= #1 NextBusState; + + always_comb + case (BusState) + IDLE: if (MemReadM) NextBusState = MEMREAD; // Memory has pirority over instructions + else if (MemWriteM) NextBusState = MEMWRITE; + else if (InstrReadF) NextBusState = INSTRREAD; + else NextBusState = IDLE; + MEMREAD: if (~HREADY) NextBusState = MEMREAD; + else if (InstrReadF) NextBusState = INSTRREAD; + else NextBusState = IDLE; + MEMWRITE: if (~HREADY) NextBusState = MEMWRITE; + else if (InstrReadF) NextBusState = INSTRREAD; + else NextBusState = IDLE; + INSTRREAD: //if (~HREADY & (MemReadM | MemWriteM)) NextBusState = INSTRREADMEMPENDING; // *** shouldn't happen, delete + if (~HREADY) NextBusState = INSTRREAD; + else NextBusState = IDLE; + INSTRREADMEMPENDING: if (~HREADY) NextBusState = INSTRREADMEMPENDING; // *** shouldn't happen, delete + else if (MemReadM) NextBusState = MEMREAD; + else NextBusState = MEMWRITE; // must be write if not a read. Don't return to idle. + endcase + + // stall signals + assign #2 DataStall = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE) || (NextBusState == INSTRREADMEMPENDING); + assign #1 InstrStall = (NextBusState == INSTRREAD); + // assign InstrUpdate = (BusState == INSTRREADMEMPENDING) && (NextBusState != INSTRREADMEMPENDING); + + // bus outputs + assign #1 GrantData = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE); + assign #1 HADDR = (GrantData) ? MemPAdrM[31:0] : InstrPAdrF[31:0]; + assign #1 HSIZE = GrantData ? {1'b0, MemSizeM} : ISize; + assign HBURST = 3'b000; // Single burst only supported; consider generalizing for cache fillsfH + assign HPROT = 4'b0011; // not used; see Section 3.7 + assign HTRANS = (NextBusState != IDLE) ? 2'b10 : 2'b00; // NONSEQ if reading or writing, IDLE otherwise + assign HMASTLOCK = 0; // no locking supported + assign HWRITE = (NextBusState == MEMWRITE); + // delay write data by one cycle for + flop #(`XLEN) wdreg(HCLK, WriteDataM, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN + // delay signals for subword writes + flop #(3) adrreg(HCLK, HADDR[2:0], HADDRD); + flop #(4) sizereg(HCLK, {UnsignedLoadM, HSIZE}, HSIZED); + flop #(1) writereg(HCLK, HWRITE, HWRITED); + + /* typedef enum {IDLE, MEMREAD, MEMWRITE, INSTRREAD} statetype; statetype AdrState, DataState, NextAdrState; // what is happening in the first and second phases of the bus always_ff @(posedge HCLK, negedge HRESETn) @@ -117,13 +162,42 @@ module ahblite ( assign MemAckW = (AdrState == MEMREAD || AdrState == MEMWRITE) && HREADY; assign InstrAckD = (AdrState == INSTRREAD) && HREADY; + // State machines for stalls (probably can merge with FSM above***) + // Idle, DataBusy, InstrBusy. Stall while in busystate add suffixes + logic MemState, NextMemState, InstrState, NextInstrState; + flopr #(1) msreg(HCLK, ~HRESETn, NextMemState, MemState); + flopr #(1) isreg(HCLK, ~HRESETn, NextInstrState, InstrState); +/* always_ff @(posedge HCLK, negedge HRESETn) + if (~HRESETn) MemState <= 0; + else MemState <= NextMemState; + assign NextMemState = (MemState == 0 && InstrState == 0 && (MemReadM || MemWriteM)) || (MemState == 1 && ~MemAckW); + assign DataStall = NextMemState; +/* always_ff @(posedge HCLK, negedge HRESETn) + if (~HRESETn) InstrState <= 0; + else InstrState <= NextInstrState; + + assign NextInstrState = (InstrState == 0 && MemState == 0 && (~MemReadM && ~MemWriteM && InstrReadF)) || + (InstrState == 1 && ~InstrAckD) || + (InstrState == 1 && ResolveBranchD); // dh 2/8/2021 fixing; delete this later +/* assign NextInstrState = (InstrState == 0 && MemState == 0 && (~MemReadM && ~MemWriteM)) || + (InstrState == 1 && ~InstrAckD); // *** removed InstrReadF above dh 2/9/20 + assign InstrStall = NextInstrState | MemState | NextMemState; // *** check this, explain better + // temporarily turn off stalls and check it works + //assign DataStall = 0; + //assign InstrStall = 0; + + assign DReady = HREADY & GrantData; // ***unused? + assign IReady = HREADY & InstrReadF & ~GrantData; // maybe unused?*** + +*/ + // Choose ISize based on XLen generate //if (`AHBW == 32) assign ISize = 3'b010; // 32-bit transfers //else assign ISize = 3'b011; // 64-bit transfers assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width endgenerate - +/* // drive bus outputs assign HADDR = GrantData ? MemPAdrM[31:0] : InstrPAdrF[31:0]; //assign HWDATA = WriteDataW; @@ -134,41 +208,16 @@ module ahblite ( assign HPROT = 4'b0011; // not used; see Section 3.7 assign HTRANS = InstrReadF | MemReadM | MemWriteM ? 2'b10 : 2'b00; // NONSEQ if reading or writing, IDLE otherwise assign HMASTLOCK = 0; // no locking supported - + */ // Route signals to Instruction and Data Caches // *** assumes AHBW = XLEN assign InstrRData = HRDATAMasked[31:0]; - assign IReady = HREADY & InstrReadF & ~GrantData; // maybe unused?*** // assign ReadDataW = HRDATAMasked; assign ReadDataM = HRDATAMasked; // changed from W to M dh 2/7/2021 - flopenrc #(`XLEN) ReadDataWReg(clk, reset, FlushW, ~StallW, ReadDataM, ReadDataW); - assign DReady = HREADY & GrantData; // ***unused? + assign CaptureDataM = (BusState == MEMREAD) && (NextBusState != MEMREAD); + flopenr #(`XLEN) ReadDataWReg(clk, reset, CaptureDataM, ReadDataM, ReadDataW); - // State machines for stalls (probably can merge with FSM above***) - // Idle, DataBusy, InstrBusy. Stall while in busystate add suffixes - logic MemState, NextMemState, InstrState, NextInstrState; - flopr #(1) msreg(HCLK, ~HRESETn, NextMemState, MemState); - flopr #(1) isreg(HCLK, ~HRESETn, NextInstrState, InstrState); -/* always_ff @(posedge HCLK, negedge HRESETn) - if (~HRESETn) MemState <= 0; - else MemState <= NextMemState; */ - assign NextMemState = (MemState == 0 && InstrState == 0 && (MemReadM || MemWriteM)) || (MemState == 1 && ~MemAckW); - assign DataStall = NextMemState; -/* always_ff @(posedge HCLK, negedge HRESETn) - if (~HRESETn) InstrState <= 0; - else InstrState <= NextInstrState;*/ - - assign NextInstrState = (InstrState == 0 && MemState == 0 && (~MemReadM && ~MemWriteM && InstrReadF)) || - (InstrState == 1 && ~InstrAckD) || - (InstrState == 1 && ResolveBranchD); // dh 2/8/2021 fixing; delete this later -/* assign NextInstrState = (InstrState == 0 && MemState == 0 && (~MemReadM && ~MemWriteM)) || - (InstrState == 1 && ~InstrAckD); // *** removed InstrReadF above dh 2/9/20 */ - assign InstrStall = NextInstrState | MemState | NextMemState; // *** check this, explain better - // temporarily turn off stalls and check it works - //assign DataStall = 0; - //assign InstrStall = 0; - // stalls // Stall MEM stage if data is being accessed and bus isn't yet ready //assign DataStall = GrantData & ~HREADY; diff --git a/wally-pipelined/src/generic/flop.sv b/wally-pipelined/src/generic/flop.sv index 263a4fb90..7e954a8f8 100644 --- a/wally-pipelined/src/generic/flop.sv +++ b/wally-pipelined/src/generic/flop.sv @@ -47,6 +47,16 @@ module flopr #(parameter WIDTH = 8) ( else q <= #1 d; endmodule +// flop with enable +module flopen #(parameter WIDTH = 8) ( + input logic clk, en, + input logic [WIDTH-1:0] d, + output logic [WIDTH-1:0] q); + + always_ff @(posedge clk) + if (en) q <= #1 d; +endmodule + // flop with enable, asynchronous reset, synchronous clear module flopenrc #(parameter WIDTH = 8) ( input logic clk, reset, clear, en, diff --git a/wally-pipelined/src/hazard/hazard.sv b/wally-pipelined/src/hazard/hazard.sv index 88d78ee47..c45fb47f4 100644 --- a/wally-pipelined/src/hazard/hazard.sv +++ b/wally-pipelined/src/hazard/hazard.sv @@ -56,12 +56,12 @@ module hazard( assign BranchFlushDE = PCSrcE | RetM | TrapM; - assign StallFCause = InstrStall | CSRWritePendingDEM; // stall at fetch if unable to get the instruction, + assign StallFCause = /*InstrStall | */ CSRWritePendingDEM; // stall at fetch if unable to get the instruction, // or if a CSR will be written and may change system behavior assign StallDCause = LoadStallD; // stall in decode if instruction is a load dependent on previous assign StallECause = 0; assign StallMCause = 0; // sDataStall; // not yet used*** - assign StallWCause = DataStall; // | InstrStall; + assign StallWCause = DataStall | InstrStall; // Each stage stalls if the next stage is stalled or there is a cause to stall this stage. assign StallF = StallD | StallFCause; diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index 6c16ebd8f..3ba28a059 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -67,18 +67,20 @@ module ifu ( // *** put memory interface on here, InstrF becomes output assign InstrPAdrF = PCF; // *** no MMU - assign InstrReadF = ~StallD; // *** & ICacheMissF; add later + //assign InstrReadF = ~StallD; // *** & ICacheMissF; add later + assign InstrReadF = 1; // *** & ICacheMissF; add later assign PrivilegedChangePCM = RetM | TrapM; - assign StallExceptResolveBranchesF = StallF & ~(PCSrcE | PrivilegedChangePCM); + //assign StallExceptResolveBranchesF = StallF & ~(PCSrcE | PrivilegedChangePCM); // dh 2/8/2022 keep in instruction fetch stall mode when taking branch - flopr #(1) rbreg(clk, reset, (PCSrcE | PrivilegedChangePCM), ResolveBranchD); + //flopr #(1) rbreg(clk, reset, (PCSrcE | PrivilegedChangePCM), ResolveBranchD); mux3 #(`XLEN) pcmux(PCPlus2or4F, PCTargetE, PrivilegedNextPCM, {PrivilegedChangePCM, PCSrcE}, UnalignedPCNextF); assign PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment - flopenl #(`XLEN) pcreg(clk, reset, ~StallExceptResolveBranchesF, PCNextF, `RESET_VECTOR, PCF); +// flopenl #(`XLEN) pcreg(clk, reset, ~StallExceptResolveBranchesF, PCNextF, `RESET_VECTOR, PCF); + flopenl #(`XLEN) pcreg(clk, reset, ~StallF, PCNextF, `RESET_VECTOR, PCF); // pcadder // add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32 diff --git a/wally-pipelined/src/privileged/csr.sv b/wally-pipelined/src/privileged/csr.sv index 496b0a080..e1e76aa02 100644 --- a/wally-pipelined/src/privileged/csr.sv +++ b/wally-pipelined/src/privileged/csr.sv @@ -28,7 +28,7 @@ module csr ( input logic clk, reset, - input logic FlushW, + input logic FlushW, StallW, input logic [31:0] InstrM, input logic [`XLEN-1:0] PCM, SrcAM, input logic CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, uretM, diff --git a/wally-pipelined/src/privileged/csrsr.sv b/wally-pipelined/src/privileged/csrsr.sv index 6db96dcc5..ecfbecfda 100644 --- a/wally-pipelined/src/privileged/csrsr.sv +++ b/wally-pipelined/src/privileged/csrsr.sv @@ -27,7 +27,7 @@ `include "wally-config.vh" module csrsr ( - input logic clk, reset, + input logic clk, reset, StallW, input logic WriteMSTATUSM, WriteSSTATUSM, WriteUSTATUSM, input logic TrapM, FloatRegWriteW, input logic [1:0] NextPrivilegeModeM, PrivilegeModeW, @@ -118,7 +118,7 @@ module csrsr ( STATUS_MIE <= 0; // Per Priv 3.3 STATUS_SIE <= `S_SUPPORTED; STATUS_UIE <= `U_SUPPORTED; - end else begin + end else if (~StallW) begin if (WriteMSTATUSM) begin STATUS_SUM_INT <= CSRWriteValM[18]; STATUS_MPRV_INT <= CSRWriteValM[17]; diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv index be97b51cd..6b1249720 100644 --- a/wally-pipelined/src/privileged/privileged.sv +++ b/wally-pipelined/src/privileged/privileged.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// exceptions.sv +// privileged.sv // // Written: David_Harris@hmc.edu 5 January 2021 // Modified: @@ -45,7 +45,7 @@ module privileged ( input logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM, input logic [4:0] SetFflagsM, output logic [2:0] FRM_REGW, - input logic FlushD, FlushE, FlushM, StallD + input logic FlushD, FlushE, FlushM, StallD, StallW ); logic [1:0] NextPrivilegeModeM, PrivilegeModeW; @@ -81,8 +81,8 @@ module privileged ( // PrivilegeMode FSM always_comb - if (reset) NextPrivilegeModeM = `M_MODE; // Privilege resets to 11 (Machine Mode) - else if (mretM) NextPrivilegeModeM = STATUS_MPP; + /* if (reset) NextPrivilegeModeM = `M_MODE; // Privilege resets to 11 (Machine Mode) // moved reset to flop + else */ if (mretM) NextPrivilegeModeM = STATUS_MPP; else if (sretM) NextPrivilegeModeM = {1'b0, STATUS_SPP}; else if (uretM) NextPrivilegeModeM = `U_MODE; else if (TrapM) begin // Change privilege based on DELEG registers (see 3.1.8) @@ -96,7 +96,7 @@ module privileged ( else NextPrivilegeModeM = `M_MODE; end else NextPrivilegeModeM = PrivilegeModeW; - flop #(2) privmodereg(clk, NextPrivilegeModeM, PrivilegeModeW); + flopenl #(2) privmodereg(clk, reset, ~StallW, NextPrivilegeModeM, `M_MODE, PrivilegeModeW); /////////////////////////////////////////// // decode privileged instructions diff --git a/wally-pipelined/src/uncore/dtim.sv b/wally-pipelined/src/uncore/dtim.sv index 611183605..4216b356c 100644 --- a/wally-pipelined/src/uncore/dtim.sv +++ b/wally-pipelined/src/uncore/dtim.sv @@ -37,6 +37,7 @@ module dtim ( logic [`XLEN-1:0] RAM[0:65535]; logic [18:0] HWADDR; + logic [`XLEN-1:0] HREADTim0; // logic [`XLEN-1:0] write; logic [15:0] entry; @@ -44,27 +45,28 @@ module dtim ( logic [3:0] busycount; // busy FSM to extend READY signal -/* always_ff @(posedge HCLK, negedge HRESETn) + always_ff @(posedge HCLK, negedge HRESETn) if (~HRESETn) begin HREADYTim <= 1; end else begin if (HREADYTim & HSELTim) begin busycount <= 0; - HREADYTim <= 0; + HREADYTim <= #1 0; end else if (~HREADYTim) begin - if (busycount == 0) begin // TIM latency, for testing purposes - HREADYTim <= 1; + if (busycount == 2) begin // TIM latency, for testing purposes + HREADYTim <= #1 1; end else begin busycount <= busycount + 1; end end - end*/ - always_ff @(posedge HCLK, negedge HRESETn) + end + + /* always_ff @(posedge HCLK, negedge HRESETn) if (~HRESETn) begin HREADYTim <= 0; end else begin HREADYTim <= HSELTim; // always respond one cycle later - end + end */ assign memread = MemRWtim[1]; @@ -73,77 +75,32 @@ module dtim ( // memwrite <= MemRWtim[0]; // delay memwrite to write phase assign HRESPTim = 0; // OK // assign HREADYTim = 1; // Respond immediately; *** extend this - - // word aligned reads -/* generate - if (`XLEN==64) - assign #2 entry = HADDR[18:3]; - else - assign #2 entry = HADDR[17:2]; - endgenerate */ -// assign HREADTim = RAM[entry]; -// assign HREADTim = HREADYTim ? RAM[entry] : ~RAM[entry]; // *** temproary mess up read value before ready - // write each byte based on the byte mask - // UInstantiate a byte-writable memory here if possible - // and drop tihs masking logic. Otherwise, use the masking - // from dmem - /*generate - - if (`XLEN==64) begin - always_comb begin - write=HREADTim; - if (ByteMaskM[0]) write[7:0] = HWDATA[7:0]; - if (ByteMaskM[1]) write[15:8] = HWDATA[15:8]; - if (ByteMaskM[2]) write[23:16] = HWDATA[23:16]; - if (ByteMaskM[3]) write[31:24] = HWDATA[31:24]; - if (ByteMaskM[4]) write[39:32] = HWDATA[39:32]; - if (ByteMaskM[5]) write[47:40] = HWDATA[47:40]; - if (ByteMaskM[6]) write[55:48] = HWDATA[55:48]; - if (ByteMaskM[7]) write[63:56] = HWDATA[63:56]; - end - always_ff @(posedge clk) - if (memwrite) RAM[HADDR[18:3]] <= write; - end else begin // 32-bit - always_comb begin - write=HREADTim; - if (ByteMaskM[0]) write[7:0] = HWDATA[7:0]; - if (ByteMaskM[1]) write[15:8] = HWDATA[15:8]; - if (ByteMaskM[2]) write[23:16] = HWDATA[23:16]; - if (ByteMaskM[3]) write[31:24] = HWDATA[31:24]; - end - always_ff @(posedge clk) - if (memwrite) RAM[HADDR[17:2]] <= write; - end - endgenerate */ // Model memory read and write - // If write occurs at end of phase (rising edge of clock), - // then read of same address on next cycle won't work. Would need to bypass. - // Faking for now with negedge clock write. Will need to adjust this to - // match capabilities of FPGA or actual chip RAM. - // Also, writes occuring later than reads throws off single ported RAM that - // might be asked to write on one instruction and read on the next and would need - // to stall because both accesses happen on same cycle with AHB delay generate if (`XLEN == 64) begin - always_ff @(negedge HCLK) - if (memwrite) RAM[HWADDR[17:3]] <= HWDATA; +// always_ff @(negedge HCLK) +// if (memwrite) RAM[HWADDR[17:3]] <= HWDATA; always_ff @(posedge HCLK) begin //if (memwrite) RAM[HADDR[17:3]] <= HWDATA; HWADDR <= HADDR; - HREADTim <= RAM[HADDR[17:3]]; + HREADTim0 <= RAM[HADDR[17:3]]; + if (memwrite && HREADYTim) RAM[HWADDR[17:3]] <= HWDATA; end end else begin - always_ff @(negedge HCLK) - if (memwrite) RAM[HWADDR[17:2]] <= HWDATA; +// always_ff @(negedge HCLK) +// if (memwrite) RAM[HWADDR[17:2]] <= HWDATA; always_ff @(posedge HCLK) begin //if (memwrite) RAM[HADDR[17:2]] <= HWDATA; HWADDR <= HADDR; - HREADTim <= RAM[HADDR[17:2]]; + HREADTim0 <= RAM[HADDR[17:2]]; + if (memwrite && HREADYTim) RAM[HWADDR[17:2]] <= HWDATA; end end endgenerate + + assign HREADTim = HREADYTim ? HREADTim0 : 'bz; endmodule diff --git a/wally-pipelined/testgen/testgen-ADD-SUB.py b/wally-pipelined/testgen/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py similarity index 82% rename from wally-pipelined/testgen/testgen-ADD-SUB.py rename to wally-pipelined/testgen/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py index 16e02be6b..9f795036b 100755 --- a/wally-pipelined/testgen/testgen-ADD-SUB.py +++ b/wally-pipelined/testgen/testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py @@ -1,6 +1,6 @@ #!/usr/bin/python3 ################################## -# testgen-ADD-SUB.py +# testgen-ADD-SUB-SLT-SLTU-XOR-OR-AND.py # # David_Harris@hmc.edu 19 January 2021 # @@ -19,11 +19,34 @@ from random import getrandbits # functions ################################## -def computeExpected(a, b, test): +def twoscomp(a): + amsb = a >> (xlen-1) + alsbs = ((1 << (xlen-1)) - 1) & a + if (amsb): + asigned = a - (1<> (xlen-1) + alsbs = ((1 << (xlen-1)) - 1) & a + if (amsb): + asigned = a - (1<> b + elif (test == "SRA"): + return asigned >> b + else: + die("bad test name ", test) + # exit(1) + +def randRegs(): + reg1 = randint(1,31) + reg2 = randint(1,31) + reg3 = randint(1,31) + if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2): + return randRegs() + else: + return reg1, reg2, reg3 + +def writeVector(a, b, storecmd, xlen): + global testnum + expected = computeExpected(a, b, test, xlen) + expected = expected % 2**xlen # drop carry if necessary + if (expected < 0): # take twos complement + expected = 2**xlen + expected + reg1, reg2, reg3 = randRegs() + lines = "\n# Testcase " + str(testnum) + ": rs1:x" + str(reg1) + "(" + formatstr.format(a) + lines = lines + "), rs2:x" + str(reg2) + "(" +formatstr.format(b) + lines = lines + "), result rd:x" + str(reg3) + "(" + formatstr.format(expected) +")\n" + lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n" + lines = lines + "li x" + str(reg2) + ", MASK_XLEN(" + formatstr.format(b) + ")\n" + lines = lines + test + " x" + str(reg3) + ", x" + str(reg1) + ", x" + str(reg2) + "\n" + lines = lines + storecmd + " x" + str(reg3) + ", " + str(wordsize*testnum) + "(x6)\n" + lines = lines + "RVTEST_IO_ASSERT_GPR_EQ(x7, " + str(reg3) +", "+formatstr.format(expected)+")\n" + f.write(lines) + if (xlen == 32): + line = formatrefstr.format(expected)+"\n" + else: + line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n" + r.write(line) + testnum = testnum+1 + +################################## +# main body +################################## + +# change these to suite your tests +tests = ["SLL", "SRL", "SRA"] +author = "David_Harris@hmc.edu" +xlens = [32, 64] +numrand = 48 + +# setup +seed(0) # make tests reproducible + +# generate files for each test +for xlen in xlens: + formatstrlen = str(int(xlen/4)) + formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number + formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x + if (xlen == 32): + storecmd = "sw" + wordsize = 4 + else: + storecmd = "sd" + wordsize = 8 + for test in tests: + corners = [0, 1, 2, 0xFF, 0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1, + 2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1] + if (xlen == 32): + shamt = [0, 1, 2, 3, 4, 8, 15, 16, 29, 30, 31] + else: + shamt = [0, 1, 3, 8, 15, 16, 29, 31, 32, 47, 48, 62, 63] + + imperaspath = "../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "i/" + basename = "WALLY-" + test + fname = imperaspath + "src/" + basename + ".S" + refname = imperaspath + "references/" + basename + ".reference_output" + testnum = 0 + + # print custom header part + f = open(fname, "w") + r = open(refname, "w") + line = "///////////////////////////////////////////\n" + f.write(line) + lines="// "+fname+ "\n// " + author + "\n" + f.write(lines) + line ="// Created " + str(datetime.now()) + f.write(line) + + # insert generic header + h = open("testgen_header.S", "r") + for line in h: + f.write(line) + + # print directed and random test vectors + for a in corners: + for b in shamt: + writeVector(a, b, storecmd, xlen) + for i in range(0,numrand): + a = getrandbits(xlen) + b = getrandbits(xlen) + writeVector(a, b, storecmd, xlen) + + + # print footer + h = open("testgen_footer.S", "r") + for line in h: + f.write(line) + + # Finish + lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n" + lines = lines + "\nRV_COMPLIANCE_DATA_END\n" + f.write(lines) + f.close() + r.close() + + + + From 87ad559a909cb69817dbf5c66224723082a13b51 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 18 Feb 2021 08:13:08 -0500 Subject: [PATCH 18/33] Updated creation date of mul --- wally-pipelined/src/muldiv/mul.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/src/muldiv/mul.sv b/wally-pipelined/src/muldiv/mul.sv index 2fee66e65..e7a13be54 100644 --- a/wally-pipelined/src/muldiv/mul.sv +++ b/wally-pipelined/src/muldiv/mul.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // mul.sv // -// Written: David_Harris@hmc.edu 9 January 2021 +// Written: David_Harris@hmc.edu 16 February 2021 // Modified: // // Purpose: Multiply instructions From f372e2b8e8d75270af6c0ea52b933967f4f71e4f Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 22 Feb 2021 13:48:30 -0500 Subject: [PATCH 19/33] Debugging Bus interface --- wally-pipelined/src/ebu/ahblite.sv | 25 +++++++++++++------ wally-pipelined/src/uncore/clint.sv | 5 ++++ .../testbench/testbench-imperas.sv | 7 +++--- 3 files changed, 26 insertions(+), 11 deletions(-) diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv index e917b6680..655714762 100644 --- a/wally-pipelined/src/ebu/ahblite.sv +++ b/wally-pipelined/src/ebu/ahblite.sv @@ -69,7 +69,7 @@ module ahblite ( logic GrantData; logic [2:0] ISize; - logic [`AHBW-1:0] HRDATAMasked, ReadDataM; + logic [`AHBW-1:0] HRDATAMasked, ReadDataM, ReadDataPreW; logic IReady, DReady; // logic [3:0] HSIZED; // size delayed by one cycle for reads // logic [2:0] HADDRD; // address delayed for subword reads @@ -114,6 +114,12 @@ module ahblite ( assign #2 DataStall = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE) || (NextBusState == INSTRREADMEMPENDING); assign #1 InstrStall = (NextBusState == INSTRREAD); // assign InstrUpdate = (BusState == INSTRREADMEMPENDING) && (NextBusState != INSTRREADMEMPENDING); + + // DH 2/20/22: A cyclic path presently exists + // HREADY->NextBusState->GrantData->HSIZE->HSELUART->HREADY + // This is because the peripherals assert HREADY on the same cycle + // When memory is working, also fix the peripherals to respond on the subsequent cycle + // and this path should be fixed. // bus outputs assign #1 GrantData = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE); @@ -131,6 +137,16 @@ module ahblite ( flop #(4) sizereg(HCLK, {UnsignedLoadM, HSIZE}, HSIZED); flop #(1) writereg(HCLK, HWRITE, HWRITED); + // Route signals to Instruction and Data Caches + // *** assumes AHBW = XLEN + assign InstrRData = HRDATAMasked[31:0]; +// assign ReadDataW = HRDATAMasked; + assign ReadDataM = HRDATAMasked; // changed from W to M dh 2/7/2021 + assign CaptureDataM = (BusState == MEMREAD) && (NextBusState != MEMREAD); + flopenr #(`XLEN) ReadDataPreWReg(clk, reset, CaptureDataM, ReadDataM, ReadDataPreW); // *** this may break when there is no instruction read after data read + flopenr #(`XLEN) ReadDataWReg(clk, reset, ~StallW, ReadDataPreW, ReadDataW); + + /* typedef enum {IDLE, MEMREAD, MEMWRITE, INSTRREAD} statetype; statetype AdrState, DataState, NextAdrState; // what is happening in the first and second phases of the bus @@ -209,13 +225,6 @@ module ahblite ( assign HTRANS = InstrReadF | MemReadM | MemWriteM ? 2'b10 : 2'b00; // NONSEQ if reading or writing, IDLE otherwise assign HMASTLOCK = 0; // no locking supported */ - // Route signals to Instruction and Data Caches - // *** assumes AHBW = XLEN - assign InstrRData = HRDATAMasked[31:0]; -// assign ReadDataW = HRDATAMasked; - assign ReadDataM = HRDATAMasked; // changed from W to M dh 2/7/2021 - assign CaptureDataM = (BusState == MEMREAD) && (NextBusState != MEMREAD); - flopenr #(`XLEN) ReadDataWReg(clk, reset, CaptureDataM, ReadDataM, ReadDataW); // stalls diff --git a/wally-pipelined/src/uncore/clint.sv b/wally-pipelined/src/uncore/clint.sv index 00804a480..e3fc1ea04 100644 --- a/wally-pipelined/src/uncore/clint.sv +++ b/wally-pipelined/src/uncore/clint.sv @@ -54,6 +54,11 @@ module clint ( assign #2 entry = {HADDR[15:2], 2'b00}; endgenerate + // DH 2/20/21: Eventually allow MTIME to run off a separate clock + // This will require synchronizing MTIME to the system clock + // before it is read or compared to MTIMECMP. + // It will also require synchronizing the write to MTIMECMP. + // Use req and ack signals synchronized across the clock domains. // register access generate diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index cad2d68d2..fd49fee0a 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -75,6 +75,7 @@ string tests64iNOc[] = { "rv64i/I-MISALIGN_JMP-01","2000" }; string tests64i[] = '{ + "rv64i/I-ECALL-01", "2000", "rv64i/I-ENDIANESS-01", "2010", "rv64i/I-ADD-01", "3000", "rv64i/I-ADDI-01", "3000", @@ -90,8 +91,8 @@ string tests64iNOc[] = { "rv64i/I-BLTU-01", "4000", "rv64i/I-BNE-01", "4000", "rv64i/I-DELAY_SLOTS-01", "2000", - "rv64i/I-EBREAK-01", "2000", - "rv64i/I-ECALL-01", "2000", +// "rv64i/I-EBREAK-01", "2000", +// "rv64i/I-ECALL-01", "2000", "rv64i/I-ENDIANESS-01", "2010", "rv64i/I-IO-01", "2050", "rv64i/I-JAL-01", "3000", @@ -104,7 +105,7 @@ string tests64iNOc[] = { "rv64i/I-LUI-01", "2000", "rv64i/I-LW-01", "4110", "rv64i/I-LWU-01", "4110", - "rv64i/I-MISALIGN_LDST-01", "2010", + //"rv64i/I-MISALIGN_LDST-01", "2010", "rv64i/I-NOP-01", "2000", "rv64i/I-OR-01", "3000", "rv64i/I-ORI-01", "3000", From 7737b0f7093f276c5b7afdc4a10058742e076639 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 23 Feb 2021 09:08:57 -0500 Subject: [PATCH 20/33] Fixed fetch stall after jump in bus unit --- wally-pipelined/src/hazard/hazard.sv | 6 +++++- wally-pipelined/src/privileged/csr.sv | 4 +++- wally-pipelined/testbench/testbench-imperas.sv | 11 ++++------- 3 files changed, 12 insertions(+), 9 deletions(-) diff --git a/wally-pipelined/src/hazard/hazard.sv b/wally-pipelined/src/hazard/hazard.sv index c45fb47f4..a6cdd82cf 100644 --- a/wally-pipelined/src/hazard/hazard.sv +++ b/wally-pipelined/src/hazard/hazard.sv @@ -56,7 +56,11 @@ module hazard( assign BranchFlushDE = PCSrcE | RetM | TrapM; - assign StallFCause = /*InstrStall | */ CSRWritePendingDEM; // stall at fetch if unable to get the instruction, + // changed 2/22/21 harris to turn off stallF when RetM or TrapM + // changed 2/23/21 harris to BranchFlushDEM to solve bug in ECALL about JAL being ignored +// assign StallFCause = /*InstrStall | */ CSRWritePendingDEM; // stall at fetch if unable to get the instruction, +// assign StallFCause = /*InstrStall | */ CSRWritePendingDEM & ~(RetM | TrapM); // stall at fetch if unable to get the instruction, + assign StallFCause = /*InstrStall | */ CSRWritePendingDEM & ~(BranchFlushDE); // stall at fetch if unable to get the instruction, // or if a CSR will be written and may change system behavior assign StallDCause = LoadStallD; // stall in decode if instruction is a load dependent on previous assign StallECause = 0; diff --git a/wally-pipelined/src/privileged/csr.sv b/wally-pipelined/src/privileged/csr.sv index e1e76aa02..bee0ba86c 100644 --- a/wally-pipelined/src/privileged/csr.sv +++ b/wally-pipelined/src/privileged/csr.sv @@ -102,7 +102,9 @@ module csr ( // merge CSR Reads assign CSRReadValM = CSRUReadValM | CSRSReadValM | CSRMReadValM | CSRCReadValM | CSRNReadValM; - floprc #(`XLEN) CSRValWReg(clk, reset, FlushW, CSRReadValM, CSRReadValW); + // *** add W stall 2/22/21 dh to try fixing memory stalls +// floprc #(`XLEN) CSRValWReg(clk, reset, FlushW, CSRReadValM, CSRReadValW); + flopenrc #(`XLEN) CSRValWReg(clk, reset, FlushW, ~StallW, CSRReadValM, CSRReadValW); // merge illegal accesses: illegal if none of the CSR addresses is legal or privilege is insufficient assign InsufficientCSRPrivilegeM = (CSRAdrM[9:8] == 2'b11 && PrivilegeModeW != `M_MODE) || diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index fd49fee0a..491301cd6 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -75,8 +75,6 @@ string tests64iNOc[] = { "rv64i/I-MISALIGN_JMP-01","2000" }; string tests64i[] = '{ - "rv64i/I-ECALL-01", "2000", - "rv64i/I-ENDIANESS-01", "2010", "rv64i/I-ADD-01", "3000", "rv64i/I-ADDI-01", "3000", "rv64i/I-ADDIW-01", "3000", @@ -91,8 +89,8 @@ string tests64iNOc[] = { "rv64i/I-BLTU-01", "4000", "rv64i/I-BNE-01", "4000", "rv64i/I-DELAY_SLOTS-01", "2000", -// "rv64i/I-EBREAK-01", "2000", -// "rv64i/I-ECALL-01", "2000", + "rv64i/I-EBREAK-01", "2000", + "rv64i/I-ECALL-01", "2000", "rv64i/I-ENDIANESS-01", "2010", "rv64i/I-IO-01", "2050", "rv64i/I-JAL-01", "3000", @@ -105,7 +103,7 @@ string tests64iNOc[] = { "rv64i/I-LUI-01", "2000", "rv64i/I-LW-01", "4110", "rv64i/I-LWU-01", "4110", - //"rv64i/I-MISALIGN_LDST-01", "2010", + "rv64i/I-MISALIGN_LDST-01", "2010", "rv64i/I-NOP-01", "2000", "rv64i/I-OR-01", "3000", "rv64i/I-ORI-01", "3000", @@ -140,7 +138,6 @@ string tests64iNOc[] = { "rv64i/WALLY-SUB", "4000" }; string tests32ic[] = '{ -// "rv32ic/WALLY-C-ADHOC-01", "2000", "rv32ic/I-C-ADD-01", "2000", "rv32ic/I-C-ADDI-01", "2000", "rv32ic/I-C-AND-01", "2000", @@ -239,7 +236,7 @@ string tests32i[] = { initial if (`XLEN == 64) begin // RV64 tests = {tests64i}; - if (`C_SUPPORTED % 2 == 1) tests = {tests, tests64ic}; + if (`C_SUPPORTED % 2 == 1) tests = {tests64ic, tests}; else tests = {tests, tests64iNOc}; end else begin // RV32 tests = {tests32i}; From 906ec30339723828a58b4241cb1b1a91a951732b Mon Sep 17 00:00:00 2001 From: Katherine Parry Date: Tue, 23 Feb 2021 20:19:12 +0000 Subject: [PATCH 21/33] inital FMA push --- wally-pipelined/src/fpu/FMA/add.v | 61 + wally-pipelined/src/fpu/FMA/align.v | 99 + wally-pipelined/src/fpu/FMA/array.sv | 114 + wally-pipelined/src/fpu/FMA/booth.sv | 55 + wally-pipelined/src/fpu/FMA/bypass.v | 30 + wally-pipelined/src/fpu/FMA/compressors.sv | 90 + wally-pipelined/src/fpu/FMA/expgen.v | 135 + wally-pipelined/src/fpu/FMA/flag.v | 85 + wally-pipelined/src/fpu/FMA/fmac.v | 130 + wally-pipelined/src/fpu/FMA/lop.v | 41 + wally-pipelined/src/fpu/FMA/normalize.v | 63 + wally-pipelined/src/fpu/FMA/round.v | 106 + wally-pipelined/src/fpu/FMA/sign.v | 93 + wally-pipelined/src/fpu/FMA/special.v | 70 + wally-pipelined/src/fpu/FMA/tb.v | 2824 ++++++++++++ .../src/fpu/FMA/tbgen/StineVectors | 1997 +++++++++ wally-pipelined/src/fpu/FMA/tbgen/ans | 199 + wally-pipelined/src/fpu/FMA/tbgen/output | 199 + wally-pipelined/src/fpu/FMA/tbgen/results.dat | 1 + wally-pipelined/src/fpu/FMA/tbgen/tb | Bin 0 -> 13120 bytes wally-pipelined/src/fpu/FMA/tbgen/tb.c | 116 + wally-pipelined/src/fpu/FMA/tbgen/tb.v | 3952 +++++++++++++++++ wally-pipelined/src/fpu/FMA/tbgen/tbgen | Bin 0 -> 13048 bytes wally-pipelined/src/fpu/FMA/tbgen/tbhead.v | 36 + wally-pipelined/src/fpu/FMA/tbgen/testMini | 1000 +++++ wally-pipelined/src/fpu/FMA/tbgen/test_gen.sh | 1 + .../src/fpu/FMA/tbgen/tstFlMult.awk | 1 + 27 files changed, 11498 insertions(+) create mode 100644 wally-pipelined/src/fpu/FMA/add.v create mode 100644 wally-pipelined/src/fpu/FMA/align.v create mode 100644 wally-pipelined/src/fpu/FMA/array.sv create mode 100644 wally-pipelined/src/fpu/FMA/booth.sv create mode 100644 wally-pipelined/src/fpu/FMA/bypass.v create mode 100644 wally-pipelined/src/fpu/FMA/compressors.sv create mode 100644 wally-pipelined/src/fpu/FMA/expgen.v create mode 100644 wally-pipelined/src/fpu/FMA/flag.v create mode 100644 wally-pipelined/src/fpu/FMA/fmac.v create mode 100644 wally-pipelined/src/fpu/FMA/lop.v create mode 100644 wally-pipelined/src/fpu/FMA/normalize.v create mode 100644 wally-pipelined/src/fpu/FMA/round.v create mode 100644 wally-pipelined/src/fpu/FMA/sign.v create mode 100644 wally-pipelined/src/fpu/FMA/special.v create mode 100644 wally-pipelined/src/fpu/FMA/tb.v create mode 100644 wally-pipelined/src/fpu/FMA/tbgen/StineVectors create mode 100644 wally-pipelined/src/fpu/FMA/tbgen/ans create mode 100644 wally-pipelined/src/fpu/FMA/tbgen/output create mode 100644 wally-pipelined/src/fpu/FMA/tbgen/results.dat create mode 100755 wally-pipelined/src/fpu/FMA/tbgen/tb create mode 100644 wally-pipelined/src/fpu/FMA/tbgen/tb.c create mode 100644 wally-pipelined/src/fpu/FMA/tbgen/tb.v create mode 100755 wally-pipelined/src/fpu/FMA/tbgen/tbgen create mode 100644 wally-pipelined/src/fpu/FMA/tbgen/tbhead.v create mode 100644 wally-pipelined/src/fpu/FMA/tbgen/testMini create mode 100755 wally-pipelined/src/fpu/FMA/tbgen/test_gen.sh create mode 100755 wally-pipelined/src/fpu/FMA/tbgen/tstFlMult.awk diff --git a/wally-pipelined/src/fpu/FMA/add.v b/wally-pipelined/src/fpu/FMA/add.v new file mode 100644 index 000000000..9fc6a78dd --- /dev/null +++ b/wally-pipelined/src/fpu/FMA/add.v @@ -0,0 +1,61 @@ +//////////////////////////////////////////////////////////////////////////////// +// +// Block Name: add.v +// Author: David Harris +// Date: 11/12/1995 +// +// Block Description: +// This block performs the addition of the product and addend. It also +// contains logic necessary to adjust the signs for effective subtracts +// and negative results. +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +module add(r[105:0], s[105:0], t[157:0], sum[157:0], + negsum, invz, selsum1, killprod, negsum0, negsum1, proddenorm); +//////////////////////////////////////////////////////////////////////////////// + + input [105:0] r; // partial product 1 + input [105:0] s; // partial product 2 + input [157:0] t; // aligned addend + input invz; // invert addend + input selsum1; // select +1 mode of compound adder + input killprod; // z >> product + input negsum; // Negate sum + input proddenorm; + output [157:0] sum; // sum + output negsum0; // sum was negative in +0 mode + output negsum1; // sum was negative in +1 mode + + // Internal nodes + + wire [105:0] r2; // partial product possibly zeroed out + wire [105:0] s2; // partial product possibly zeroed out + wire [157:0] t2; // addend after inversion if necessary + wire [157:0] sum0; // sum of compound adder +0 mode + wire [157:0] sum1; // sum of compound adder +1 mode + + // Invert addend if necessary + + assign t2 = invz ? -t : t; + + // Zero out product if Z >> product or product really should be zero + + assign r2 = ~proddenorm & killprod ? 106'b0 : r; + assign s2 = ~proddenorm & killprod ? 106'b0 : s; + + // Compound adder + // Consists of 3:2 CSA followed by long compound CPA + + assign sum0 = {52'b0, r2} + {52'b0, s2} + t2 + 158'b0; + assign sum1 = {52'b0, r2} + {52'b0, s2} + t2 + 158'b1; + + // Check sign bits in +0/1 modes + assign negsum0 = sum0[157]; + assign negsum1 = sum1[157]; + + // Mux proper result (+Oil mode and inversion) using 4:1 mux + + assign sum = selsum1 ? (negsum ? ~sum1 : sum1) : (negsum ? ~sum0 : sum0); + +endmodule diff --git a/wally-pipelined/src/fpu/FMA/align.v b/wally-pipelined/src/fpu/FMA/align.v new file mode 100644 index 000000000..dd0c86f7d --- /dev/null +++ b/wally-pipelined/src/fpu/FMA/align.v @@ -0,0 +1,99 @@ +/////////////////////////////////////////////////////////////////////////////// +// Block Name: align.v +// Author: David Harris +// Date: 11/2/1995 +// +// Block Description: +// This block implements the alignment shifter. It is responsible for +// adjusting the fraction portion of the addend relative to the fraction +// produced in the multiplier array. +// +///////////////////////////////////////////////////////////////////////////// + +///////////////////////////////////////////////////////////////////////////// +module align(z[51:0], ae[12:0], aligncnt, xzero, yzero, zzero, zdenorm, proddenorm, t[157:0], bs, ps, + killprod, bypsel[1], bypplus1, byppostnorm); +///////////////////////////////////////////////////////////////////////////// + + input [51:0] z; // Fraction of addend z; + input [12:0] ae; // sign of exponent of addend z; + input [11:0] aligncnt; // amount to shift + input xzero; // Input X = 0 + input yzero; // Input Y = 0 + input zzero; // Input Z = 0 + input zdenorm; // Input Z = denorm + input proddenorm; + input [1:1] bypsel; // Select bypass to X or Z + input bypplus1; // Add one to bypassed result + input byppostnorm; // Postnormalize bypassed result + output [157:0] t; // aligned addend (54 bits left of bpt) + output bs; // sticky bit of addend + output ps; // sticky bit of product + output killprod; // Z >> product + + // Internal nodes + + reg [157:0] t; // aligned addend from shifter + reg killprod; // Z >> product + reg bs; // sticky bit of addend + reg ps; // sticky bit of product + reg [7:0] i; // temp storage for finding sticky bit + wire [52:0] z1; // Z plus 1 + wire [51:0] z2; // Z selected after handling rounds + wire [11:0] align104; // alignment count + 104 + + // Increment fraction of Z by one if necessary for prerounded bypass + // This incrementor delay is masked by the alignment count computation + + assign z1 = z + 1; + assign z2 = bypsel[1] && bypplus1 ? (byppostnorm ? z1[52:1] : z1[51:0]): z; + + // Compute sign of aligncnt + 104 to check for shifting too far right + + assign align104 = aligncnt+104; + + // Shift addend by alignment count. Generate sticky bits from + // addend on right shifts. Handle special cases of shifting + // by too much. + + always @(z2 or aligncnt or align104 or zzero or xzero or yzero or zdenorm) + begin + + // Default to clearing sticky bits + bs = 0; + ps = 0; + + // And to using product as primary operand in adder I exponent gen + killprod = 0; + + if(zzero) begin + t = 158'b0; + if (xzero || yzero) killprod = 1; + end else if ((aligncnt > 53 && ~aligncnt[11]) || xzero || yzero) begin + // Left shift by huge amount + // or product = 0 + t = {53'b0, ~zzero, z2, 52'b0}; + killprod = 1; + ps = ~xzero && ~yzero; + end else if ((ae[12] && align104[11])) begin //***fix the if statement + // KEP if the multiplier's exponent overflows + t = {53'b0, ~zzero, z2, 52'b0}; + killprod = 1; + ps = ~xzero && ~yzero; + end else if(align104[11]) begin // Right shift by huge amount + bs = ~zzero; + t = 0; + end else if (~aligncnt[11]) begin // Left shift by reasonable amount + t = {53'b0, ~zzero, z2, 52'b0} << aligncnt; + end else begin // Otherwise right shift + t = {53'b0, ~zzero, z2, 52'b0} >> -aligncnt; + + // use some behavioral code to find sticky bit. This is really + // done by hardware in the shifter. + if (aligncnt < 0) + for (i=0; i<-aligncnt-52; i = i+1) + bs = bs || z2[i]; + end + end + +endmodule diff --git a/wally-pipelined/src/fpu/FMA/array.sv b/wally-pipelined/src/fpu/FMA/array.sv new file mode 100644 index 000000000..1c216e44e --- /dev/null +++ b/wally-pipelined/src/fpu/FMA/array.sv @@ -0,0 +1,114 @@ + +module array(x, y, xdenorm, ydenorm, r, s, bypsel, bypplus1); +///////////////////////////////////////////////////////////////////////////// + + input [51:0] x; // Fraction of multiplicand x + input [51:0] y; // Fraction of multiplicand y + input xdenorm; // is x denormalized + input ydenorm; // is y denormalized + input bypsel; // Bypass X + input bypplus1; // Add 1 to X to handle rounding + output [105:0] r; // partial product 1 + output [105:0] s; // partial product 2 + + wire [51:0] xnorm; + wire [51:0] ynorm; + + wire [54:0] yExt; //y with appended 0 and assumed 1 + wire [53:0] xExt; //y with assumed 1 + wire [26:0][1:0] add1; + wire [26:0][54:0] pp; + wire [26:0] e; + logic [17:0][105:0] lv1add; + logic [11:0][105:0] lv2add; + logic [7:0][105:0] lv3add; + logic [3:0][105:0] lv4add; + logic [21:0][106:0] carryTmp; + wire [26:0][105:0] acc; + // wire [105:0] acc + genvar i; + + assign xnorm = xdenorm ? {x[50:0], 1'b0} : x; // normalization of denormalized numbers + assign ynorm = ydenorm ? {y[50:0], 1'b0} : y; + assign yExt = {2'b01,ynorm,1'b0}; // y extended and added assumed 1 + assign xExt = {2'b01,xnorm}; // x with added assumed 1 + + + //booth encoding + + generate + for(i=0; i<27; i=i+1) begin + booth booth(.xExt(xExt), .choose(yExt[(i*2)+2:i*2]), .add1(add1[i]), .e(e[i]), .pp(pp[i])); + end + endgenerate + + assign acc[0] = {49'b0,~e[0],e[0],e[0],pp[0]}; + assign acc[1] = {50'b01,~e[1],pp[1],add1[0]}; + assign acc[2] = {48'b01,~e[2],pp[2],add1[1], 2'b0}; + assign acc[3] = {46'b01,~e[3],pp[3],add1[2], 4'b0}; + assign acc[4] = {44'b01,~e[4],pp[4],add1[3], 6'b0}; + assign acc[5] = {42'b01,~e[5],pp[5],add1[4], 8'b0}; + assign acc[6] = {40'b01,~e[6],pp[6],add1[5], 10'b0}; + assign acc[7] = {38'b01,~e[7],pp[7],add1[6], 12'b0}; + assign acc[8] = {36'b01,~e[8],pp[8],add1[7], 14'b0}; + assign acc[9] = {34'b01,~e[9],pp[9],add1[8], 16'b0}; + assign acc[10] = {32'b01,~e[10],pp[10],add1[9], 18'b0}; + assign acc[11] = {30'b01,~e[11],pp[11],add1[10], 20'b0}; + assign acc[12] = {28'b01,~e[12],pp[12],add1[11], 22'b0}; + assign acc[13] = {26'b01,~e[13],pp[13],add1[12], 24'b0}; + assign acc[14] = {24'b01,~e[14],pp[14],add1[13], 26'b0}; + assign acc[15] = {22'b01,~e[15],pp[15],add1[14], 28'b0}; + assign acc[16] = {20'b01,~e[16],pp[16],add1[15], 30'b0}; + assign acc[17] = {18'b01,~e[17],pp[17],add1[16], 32'b0}; + assign acc[18] = {16'b01,~e[18],pp[18],add1[17], 34'b0}; + assign acc[19] = {14'b01,~e[19],pp[19],add1[18], 36'b0}; + assign acc[20] = {12'b01,~e[20],pp[20],add1[19], 38'b0}; + assign acc[21] = {10'b01,~e[21],pp[21],add1[20], 40'b0}; + assign acc[22] = {8'b01,~e[22],pp[22],add1[21], 42'b0}; + assign acc[23] = {6'b01,~e[23],pp[23],add1[22], 44'b0}; + assign acc[24] = {4'b01,~e[24],pp[24],add1[23], 46'b0}; + assign acc[25] = {~e[25],pp[25],add1[24], 48'b0}; + assign acc[26] = {pp[26],add1[25], 50'b0}; + + //*** resize adders + generate + for(i=0; i<9; i=i+1) begin + add3comp2 #(.BITS(106)) add1(.a(acc[i*3]), .b(acc[i*3+1]), .c(acc[i*3+2]), + .carry(carryTmp[i][105:0]), .sum(lv1add[i*2+1])); + assign lv1add[i*2] = {carryTmp[i][104:0], 1'b0}; + end + endgenerate + + generate + for(i=0; i<6; i=i+1) begin + add3comp2 #(.BITS(106)) add2(.a(lv1add[i*3]), .b(lv1add[i*3+1]), .c(lv1add[i*3+2]), + .carry(carryTmp[i+9][105:0]), .sum(lv2add[i*2+1])); + assign lv2add[i*2] = {carryTmp[i+9][104:0], 1'b0}; + end + endgenerate + + generate + for(i=0; i<4; i=i+1) begin + add3comp2 #(.BITS(106)) add3(.a(lv2add[i*3]), .b(lv2add[i*3+1]), .c(lv2add[i*3+2]), + .carry(carryTmp[i+15][105:0]), .sum(lv3add[i*2+1])); + assign lv3add[i*2] = {carryTmp[i+15][104:0], 1'b0}; + end + endgenerate + + + generate + for(i=0; i<2; i=i+1) begin + add4comp2 #(.BITS(106)) add4(.a(lv3add[i*4]), .b(lv3add[i*4+1]), .c(lv3add[i*4+2]), .d(lv3add[i*4+3]), + .carry(carryTmp[i+19]), .sum(lv4add[i*2+1])); + assign lv4add[i*2] = {carryTmp[i+19][104:0], 1'b0}; + end + endgenerate + + add4comp2 #(.BITS(106)) add5(.a(lv4add[0]), .b(lv4add[1]), .c(lv4add[2]), .d(lv4add[3]) , + .carry(carryTmp[21]), .sum(s)); + assign r = {carryTmp[21][104:0], 1'b0}; + + // assign r = 106'b0; + // assign s = ({54'b1,xnorm} + (bypsel && bypplus1)) * {54'b1,ynorm}; + +endmodule diff --git a/wally-pipelined/src/fpu/FMA/booth.sv b/wally-pipelined/src/fpu/FMA/booth.sv new file mode 100644 index 000000000..46ad22e58 --- /dev/null +++ b/wally-pipelined/src/fpu/FMA/booth.sv @@ -0,0 +1,55 @@ +module booth(xExt, choose, add1, e, pp); +///////////////////////////////////////////////////////////////////////////// + + input [53:0] xExt; // multiplicand xExt + input [2:0] choose; // bits needed to choose which encoding + output [1:0] add1; // do you add 1 + output e; + output [54:0] pp; // the resultant encoding + + logic [54:0] pp, temp; + logic e; + logic [1:0] add1; + logic [53:0] negx; + //logic temp; + + assign negx = ~xExt; + + always @(choose, xExt, negx) + case (choose) + 3'b000 : pp = 55'b0; // 0 + 3'b001 : pp = {xExt[53], xExt}; // 1 + 3'b010 : pp = {xExt[53], xExt}; // 1 + 3'b011 : pp = {xExt, 1'b0}; // 2 + 3'b100 : pp = {negx, 1'b0}; // -2 + 3'b101 : pp = {negx[53], negx}; // -1 + 3'b110 : pp = {negx[53], negx}; // -1 + 3'b111 : pp = 55'hfffffffffffffff; // -0 + endcase + + always @(choose, xExt, negx) + case (choose) + 3'b000 : e = 0; // 0 + 3'b001 : e = xExt[53]; // 1 + 3'b010 : e = xExt[53]; // 1 + 3'b011 : e = xExt[53]; // 2 + 3'b100 : e = negx[53]; // -2 + 3'b101 : e = negx[53]; // -1 + 3'b110 : e = negx[53]; // -1 + 3'b111 : e = 1; // -0 + endcase + // assign add1 = (choose[2] == 1'b1) ? ((choose[1:0] == 2'b11) ? 1'b0 : 1'b1) : 1'b0; + // assign add1 = choose[2]; + always @(choose) + case (choose) + 3'b000 : add1 = 2'b0; // 0 + 3'b001 : add1 = 2'b0; // 1 + 3'b010 : add1 = 2'b0; // 1 + 3'b011 : add1 = 2'b0; // 2 + 3'b100 : add1 = 2'b10; // -2 + 3'b101 : add1 = 2'b1; // -1 + 3'b110 : add1 = 2'b1; // -1 + 3'b111 : add1 = 2'b1; // -0 + endcase + +endmodule diff --git a/wally-pipelined/src/fpu/FMA/bypass.v b/wally-pipelined/src/fpu/FMA/bypass.v new file mode 100644 index 000000000..4a035c1ba --- /dev/null +++ b/wally-pipelined/src/fpu/FMA/bypass.v @@ -0,0 +1,30 @@ +///////////////////////////////////////////////////////////////////////////// +// +// Block Name: bypass.v +// Author: David Harris +// Date: 11/2/1995 +// +// Block Description: +// This block contains the bypass muxes which allow fast prerounded +// bypass to the X and Z inputs of the FMAC +// +///////////////////////////////////////////////////////////////////////////// + +///////////////////////////////////////////////////////////////////////////// +module bypass(xrf[63:0], zrf[63:0], wbypass[63:0], bypsel[1:0], + x[63:0], z[63:0]); +///////////////////////////////////////////////////////////////////////////// + + input [63:0] xrf; // X from register file + input [63:0] zrf; // Z from register file + input [63:0] wbypass; // Prerounded result for bypass + input [1:0] bypsel; // Select bypass to X or Z + output [63:0] x; // Source X + output [63:0] z; // Source Z + + // If bypass select is asserted, bypass source, else take reg file value + + assign x = bypsel[0] ? wbypass : xrf; + assign z = bypsel[1] ? wbypass : zrf; + +endmodule diff --git a/wally-pipelined/src/fpu/FMA/compressors.sv b/wally-pipelined/src/fpu/FMA/compressors.sv new file mode 100644 index 000000000..9dd3fc116 --- /dev/null +++ b/wally-pipelined/src/fpu/FMA/compressors.sv @@ -0,0 +1,90 @@ +module add3comp2(a, b, c, carry, sum); +///////////////////////////////////////////////////////////////////////////// +//look into diffrent implementations of the compressors? + + parameter BITS = 4; + input [BITS-1:0] a; + input [BITS-1:0] b; + input [BITS-1:0] c; + output [BITS-1:0] carry; + output [BITS-1:0] sum; + genvar i; + + generate + for(i= 0; i> product + input sumzero; // sum exactly equals zero + input postnormalize; // postnormalize rounded result + input [8:0] normcnt; // normalization shift count + input infinity; // generate infinity on overflow + input invalid; // Result invalid + input overflow; // Result overflowed + input underflow; // Result underflowed + input inf; // Some input is infinity + input nan; // Some input is NaN + input xnan; // X is NaN + input ynan; // Y is NaN + input znan; // Z is NaN + input zdenorm; // Z is denorm + input specialsel; // Select special result + output [11:0] aligncnt; // shift count for alignment shifter + output [62:52] w; // Exponent of result + output [62:52] wbypass; // Prerounded exponent for bypass + output prodof; // X*Y exponent out of bounds + output sumof; // X*Y+Z exponent out of bounds + output sumuf; // X*Y+Z exponent underflows + output denorm0; // exponent = 0 for denorm + output [12:0] ae; //exponent of multiply + + // Internal nodes + + wire [12:0] aetmp; // Exponent of Multiply + wire [12:0] aligncnt0; // Shift count for alignment + wire [12:0] aligncnt1; // Shift count for alignment + wire [12:0] be; // Exponent of multiply + wire [12:0] de0; // Normalized exponent + wire [12:0] de1; // Normalized exponent + wire [12:0] de; // Normalized exponent + wire [10:0] infinityres; // Infinity or max number + wire [10:0] nanres; // Nan propagated or generated + wire [10:0] specialres; // Exceptional case result + + // Compute exponent of multiply + // Note that the exponent does not have to be incremented on a postrounding + // normalization of X because the mantissa was already increased. Report + // if exponent is out of bounds + assign ae = x + y - 1023; + + assign prodof = (ae > 2046 && ~ae[12] && ~killprod); + + // Compute alignment shift count + // Adjust for postrounding normalization of Z. + // This should not increas the critical path because the time to + // check if a round overflows is shorter than the actual round and + // is masked by the bypass mux and two 10 bit adder delays. + + assign aligncnt0 = z - ae[10:0] + 13'b0; + assign aligncnt1 = z - ae[10:0] + 13'b1; + assign aligncnt = bypsel[1] && byppostnorm ? aligncnt1 : aligncnt0; + + // Select exponent (usually from product except in case of huge addend) + + assign be = killprod ? z : ae; + + // Adjust exponent based on normalization + // A compound adder takes care of the case of post-rounding normalization + // requiring an extra increment + + assign de0 = sumzero ? 13'b0 : be + 53 - normcnt; + assign de1 = sumzero ? 13'b0 : be + 53 - normcnt + 13'b1; + + // If the exponent becomes exactly zero (denormalized) + // signal such to adjust R bit before rounding + + assign denorm0 = (de0 == 0); + + // check for exponent out of bounds after add + + assign de = postnormalize ? de1 : de0; + assign sumof = de > 2046 && ~de[12]; + assign sumuf = (de == 0 || de[12]) && ~sumzero && ~zdenorm;//KEP ~zdenorm to prevent underflow flag + + // bypass occurs before rounding or taking early results + + assign wbypass = de0[10:0]; + + // In a non-critical special mux, we combine the early result from other + // FPU blocks with the results of exceptional conditions. Overflow + // produces either infinity or the largest finite number, depending on the + // rounding mode. NaNs are propagated or generated. + + assign specialres = earlyressel ? earlyres : + invalid ? nanres : + overflow ? infinityres : + inf ? 11'b11111111111 : + underflow ? 11'b0 : 11'bx; + + assign infinityres = infinity ? 11'b11111111111 : 11'b11111111110; + + assign nanres = xnan ? x : (ynan ? y : (znan? z : 11'b11111111111)); + + // A mux selects the early result from other FPU blocks or the + // normalized FMAC result. Special cases are also detected. + + assign w = specialsel ? specialres[10:0] : de; +endmodule + diff --git a/wally-pipelined/src/fpu/FMA/flag.v b/wally-pipelined/src/fpu/FMA/flag.v new file mode 100644 index 000000000..d7765c540 --- /dev/null +++ b/wally-pipelined/src/fpu/FMA/flag.v @@ -0,0 +1,85 @@ +/////////////////////////////////////////////////////////////////////////////// +// Block Name: flag.v +// Author: David Harris +// Date: 12/6/1995 +// +// Block Description: +// This block generates the flags: invalid, overflow, underflow, inexact. +///////////////////////////////////////////////////////////////////////////// + +///////////////////////////////////////////////////////////////////////////// +module flag(xnan, ynan, znan, xinf, yinf, zinf, prodof, sumof, sumuf, + psign, zsign, xzero, yzero, v[1:0], + inf, nan, invalid, overflow, underflow, inexact); +///////////////////////////////////////////////////////////////////////////// + + input xnan; // X is NaN + input ynan; // Y is NaN + input znan; // Z is NaN + input xinf; // X is Inf + input yinf; // Y is Inf + input zinf; // Z is Inf + input prodof; // X*Y overflows exponent + input sumof; // X*Y + z underflows exponent + input sumuf; // X*Y + z underflows exponent + input psign; // Sign of product + input zsign; // Sign of z + input xzero; // x = 0 + input yzero; // y = 0 + input [1:0] v; // R and S bits of result + output inf; // Some source is Inf + output nan; // Some source is NaN + output invalid; // Result is invalid + output overflow; // Result overflowed + output underflow; // Result underflowed + output inexact; // Result is not an exact number + + // Internal nodes + + wire prodinf; // X*Y larger than max possible + wire suminf; // X*Y+Z larger than max possible + + // If any input is NaN, propagate the NaN + + assign nan = xnan || ynan || znan; + + // Same with infinity (inf - inf and O * inf don't propagate inf + // but it's ok becaue illegal op takes higher precidence) + + assign inf= xinf || yinf || zinf; + + // Generate infinity checks + + assign prodinf = prodof && ~xnan && ~ynan; + assign suminf = sumof && ~xnan && ~ynan && ~znan; + + // Set invalid flag for following cases: + // 1) Inf - Inf + // 2) 0 * Inf + // 3) Output = NaN (this is not part of the IEEE spec, only 486 proj) + + assign invalid = (xinf || yinf || prodinf) && zinf && (psign ^ zsign) || + xzero && yinf || yzero && xinf || + nan; + + // Set the overflow flag for the following cases: + // 1) Rounded multiply result would be out of bounds + // 2) Rounded add result would be out of bounds + + assign overflow = suminf && ~inf; + + // Set the underflow flag for the following cases: + // 1) Any input is denormalized + // 2) Output would be denormalized or smaller + + assign underflow = (sumuf && ~inf && ~prodinf && ~nan); + + + // Set the inexact flag for the following cases: + // 1) Multiplication inexact + // 2) Addition inexact + // One of these cases occurred if the R or S bit is set + + assign inexact = (v[0] || v[1] || suminf) && ~(inf || nan); + +endmodule diff --git a/wally-pipelined/src/fpu/FMA/fmac.v b/wally-pipelined/src/fpu/FMA/fmac.v new file mode 100644 index 000000000..30e1f039a --- /dev/null +++ b/wally-pipelined/src/fpu/FMA/fmac.v @@ -0,0 +1,130 @@ + //////////////////////////////////////////////////////////////////////////////// +// Block Name: fmac.v +// Author: David Harris +// Date: 11/2/1995 +// +// Block Description: +// This is the top level block of a floating-point multiply/accumulate +// unit(FMAC). It instantiates the following sub-blocks: +// +// array Booth encoding, partial product generation, product summation +// expgen Exponent summation, compare, and adjust +// align Alignment shifter +// add Carry-save adder for accumulate, carry propagate adder +// lza Leading zero anticipator to control normalization shifter +// normalize Normalization shifter +// round Rounding of result +// exception Handles exceptional cases +// bypass Handles bypass of result to X or Z inputs +// sign One bit sign handling block +// special Catch special cases (inputs = 0 / infinity / etc.) +// +// The FMAC computes W=X*Y+Z, rounded with the mode specified by +// RN, RZ, RM, or RP. The result is optionally bypassed back to +// the X or Z inputs for use on the next cycle. In addition, four signals +// are produced: trap, overflow, underflow, and inexact. Trap indicates +// an infinity, NaN, or denormalized number to be handled in software; +// the other three signals are IEEE flags. +// +///////////////////////////////////////////////////////////////////////////// + +///////////////////////////////////////////////////////////////////////////// +module fmac(xrf, y, zrf, rn, rz, rp, rm, + earlyres, earlyressel, bypsel, bypplus1, byppostnorm, + w, wbypass, invalid, overflow, underflow, inexact); +///////////////////////////////////////////////////////////////////////////// + + input [63:0] xrf; // input X from reg file + input [63:0] y; // input Y + input [63:0] zrf; // input Z from reg file + input rn; // Round to Nearest + input rz; // Round toward zero + input rm; // Round toward minus infinity + input rp; // Round toward plus infinity + input [63:0] earlyres; // Early result from other FP logic + input earlyressel; // Select early result, not W + input [1:0] bypsel; // Select W bypass to X, or z + input bypplus1; // Add one in bypass + input byppostnorm; // postnormalize in bypass + output [63:0] w; // output W=X*Y+Z + output [63:0] wbypass; // prerounded output W=X*Y+Z for bypass + output invalid; // Result is invalid + output overflow; // Result overflowed + output underflow; // Result underflowed + output inexact; // Result is not an exact number + +// Internal nodes + + wire [63:0] x; // input X after bypass mux + wire [63:0] z; // input Z after bypass mux + wire [105:0] r; // one result of partial product sum + wire [105:0] s; // other result of partial products + wire [157:0] t; // output of alignment shifter + wire [157:0] sum; // output of carry prop adder + wire [53:0] v; // normalized sum, R, S bits + wire [11:0] aligncnt; // shift count for alignment + wire [8:0] normcnt; // shift count for normalizer + wire [12:0] ae; // multiplier expoent + wire bs; // sticky bit of addend + wire ps; // sticky bit of product + wire killprod; // Z >> product + wire negsum; // negate sum + wire invz; // invert addend + wire selsum1; // select +1 mode of sum + wire negsum0; // sum +0 < 0 + wire negsum1; // sum +1 < 0 + wire sumzero; // sum = 0 + wire infinity; // generate infinity on overflow + wire prodof; // X*Y out of range + wire sumof; // result out of range + +// Instantiate fraction datapath + + array array(x[51:0], y[51:0], xdenorm, ydenorm, r[105:0], s[105:0], + bypsel[0], bypplus1); + align align(z[51:0], ae, aligncnt, xzero, yzero, zzero, zdenorm, proddenorm, + t[157:0], bs, ps, killprod, + bypsel[1], bypplus1, byppostnorm); + add add(r[105:0], s[105:0], t[157:0], sum[157:0], + negsum, invz, selsum1, killprod, negsum0, negsum1, proddenorm); + lop lop(sum, normcnt, sumzero); + normalize normalize(sum[157:0], normcnt, sumzero, bs, ps, denorm0, zdenorm, + v[53:0]); + round round(v[53:0], earlyres[51:0], earlyressel, rz, rn, rp, rm, w[63], + invalid, overflow, underflow, inf, nan, xnan, ynan, znan, + x[51:0], y[51:0], z[51:0], + w[51:0], postnorrnalize, infinity, specialsel); + bypass bypass(xrf[63:0], zrf[63:0], wbypass[63:0], bypsel[1:0], + x[63:0], z[63:0]); + +// Instantiate exponent datapath + + expgen expgen(x[62:52], y[62:52], z[62:52], + earlyres[62:52], earlyressel, bypsel[1], byppostnorm, + killprod, sumzero, postnorrnalize, normcnt, + infinity, invalid, overflow, underflow, + inf, nan, xnan, ynan, znan, zdenorm, specialsel, + aligncnt, w[62:52], wbypass[62:52], + prodof, sumof, sumuf, denorm0, ae); +// Instantiate special case detection across datapath & exponent path + + special special(x[63:0], y[63:0], z[63:0], ae, xzero, yzero, zzero, + xnan, ynan, znan, xdenorm, ydenorm, zdenorm, proddenorm, + xinf, yinf, zinf); + +// Produce W for bypass + +assign wbypass[51:0] = v[53:2]; +assign wbypass[63] = w[63]; + +// Instantiate control logic + +sign sign(x[63], y[63], z[63], negsum0, negsum1, bs, ps, + killprod, rm, sumzero, nan, invalid, xinf, yinf, inf, + w[63], invz, negsum, selsum1, psign); +flag flag(xnan, ynan, znan, xinf, yinf, zinf, prodof, sumof, sumuf, + psign, z[63], xzero, yzero, v[1:0], + inf, nan, invalid, overflow, underflow, inexact); + +endmodule + diff --git a/wally-pipelined/src/fpu/FMA/lop.v b/wally-pipelined/src/fpu/FMA/lop.v new file mode 100644 index 000000000..af496dfcc --- /dev/null +++ b/wally-pipelined/src/fpu/FMA/lop.v @@ -0,0 +1,41 @@ +/////////////////////////////////////////////////////////////////////////////// +// Block Name: lop.v +// Author: David Harris +// Date: 11/2/1995 +// +// Block Description: +// This block implements a Leading One Predictor used to determine +// the normalization shift count. +/////////////////////////////////////////////////////////////////////////////// + +///////////////////////////////////////////////////////////////////////////// +module lop(sum, normcnt, sumzero); +///////////////////////////////////////////////////////////////////////////// + + input [157:0] sum; // sum + output [8:0] normcnt; // normalization shift count + output sumzero; // sum = 0 + + // Internal nodes + + reg [8:0] i; // loop index + reg [8:0] normcnt; // normalization shift count + + // A real LOP uses a fast carry chain to find only the first 0. + // It is an example of a parallel prefix algorithm. For the sake + // of simplicity, this model is behavioral instead. + // A real LOP would also operate on the sources of the adder, not + // the result! + + always @ ( sum) + begin + i = 0; + while (~sum[157-i] && i < 157) i = i+1; // search for leading one + normcnt = i; // compute shift count + end + + // Also check if sum is zero + assign sumzero = ~(|sum); + +endmodule + diff --git a/wally-pipelined/src/fpu/FMA/normalize.v b/wally-pipelined/src/fpu/FMA/normalize.v new file mode 100644 index 000000000..c92736d8a --- /dev/null +++ b/wally-pipelined/src/fpu/FMA/normalize.v @@ -0,0 +1,63 @@ +/////////////////////////////////////////////////////////////////////////////// +// Block Name: normalize.v +// Author: David Harris +// Date: 11/2/1995 +// +// Block Description: +// This block performs the normalization shift. It also +// generates the Rands bits for rounding. Finally, it +// handles the special case of a zero sum. +// +// v[53:2] is the fraction component of the prerounded result. +// It can be bypassed back to the X or Z inputs of the FMAC +// for back-to-back operations. +///////////////////////////////////////////////////////////////////////////// + +///////////////////////////////////////////////////////////////////////////// +module normalize(sum[157:0], normcnt, sumzero, bs, ps, denorm0, zdenorm, v[53:0]); +///////////////////////////////////////////////////////////////////////////// + input [157:0] sum; // sum + input [8:0] normcnt; // normalization shift count + input sumzero; // sum is zero + input bs; // sticky bit for addend + input ps; // sticky bit for product + input denorm0; // exponent = -1023 + input zdenorm; // Input Z is denormalized + output [53:0] v; // normalized sum, R, S bits + + // Internal nodes + + reg [53:0] v; // normalized sum, R, S bits + wire [157:0] sumshifted; // shifted sum + + // When the sum is zero, normalization does not apply and only the + // sticky bit must be computed. Otherwise, the sum is right-shifted + // and the Rand S bits (v[1] and v[O], respectively) are assigned. + + // The R bit is also set on denormalized numbers where the exponent + // was computed to be exactly -1023 and the L bit was set. This + // is required for correct rounding up of multiplication results. + + // The sticky bit calculation is actually built into the shifter and + // does not require a true subtraction shown in the model. + + always @(sum or normcnt or sumzero or bs or ps or sumshifted or denorm0) + begin + if (sumzero) begin // special case + v[53:1] = 0; + v[0] = ps || bs ; + end else begin // extract normalized bits + v[53:3] = sumshifted[156:106]; + // KEP prevent plus1 in round.v when z is denormalized. + v[2] = sumshifted[105] || sumshifted[106] && denorm0 && ~zdenorm; + v[1] = sumshifted[104] || sumshifted[105] && denorm0 && ~zdenorm; + v[0] = |(sumshifted[103:0]) || ps || bs; + end + end + + + // shift sum left by normcnt, filling the right with zeros + assign sumshifted = sum << normcnt; + +endmodule + diff --git a/wally-pipelined/src/fpu/FMA/round.v b/wally-pipelined/src/fpu/FMA/round.v new file mode 100644 index 000000000..217f33ad6 --- /dev/null +++ b/wally-pipelined/src/fpu/FMA/round.v @@ -0,0 +1,106 @@ +///////////////////////////////////////////////////////////////////////////// +// Block Name: round.v +// Author: David Harris +// Date: 11/2/1995 +// +// Block Description: +// This block is responsible for rounding the normalized result of // the FMAC. Because prenormalized results may be bypassed back to // the FMAC X and z inputs, rounding does not appear in the critical // path of most floating point code. This is good because rounding // requires an entire 52 bit carry-propagate half-adder delay. +// +// The results from other FPU blocks (e.g. FCVT, FDIV, etc) are also +// muxed in to form the actual result for register file writeback. This +// saves a mux from the writeback path. +// +///////////////////////////////////////////////////////////////////////////// + +///////////////////////////////////////////////////////////////////////////// +module round(v[53:0], earlyres[51:0], earlyressel, rz, rn, rp, rm, wsign, + invalid, overflow, underflow, inf, nan, xnan, ynan, znan, + x[51:0], y[51:0], z[51:0], + w[51:0], postnormalize, infinity, specialsel); +///////////////////////////////////////////////////////////////////////////// + + input [53:0] v; // normalized sum, R, S bits + input [51:0] earlyres; // result from other FPU blocks + input earlyressel; // use result from other FPU blocks + input rz; // Round toward zero + input rn; // Round toward nearest + input rp; // Round toward plus infinity + input rm; // Round toward minus infinity + input wsign; // Sign of result + input invalid; // Trap on infinity, NaN, denorm + input overflow; // Result overflowed + input underflow; // Result underflowed + input inf; // Some input is infinity + input nan; // Some input is NaN + input xnan; // X is NaN + input ynan; // Y is NaN + input znan; // Z is NaN + input [51:0] x; // Input X + input [51:0] y; // Input Y + input [51:0] z; // Input Z + output [51:0] w; // rounded result of FMAC + output postnormalize; // Right shift 1 for post-rounding norm + output infinity; // Generate infinity on overflow + output specialsel; // Select special result + + // Internal nodes + + wire plus1; // Round by adding one + wire [52:0] v1; // Result + 1 (for rounding) + wire [51:0] specialres; // Result of exceptional case + wire [51:0] infinityres; // Infinity or largest real number + wire [51:0] nanres; // Propagated or generated NaN + + // Compute if round should occur. This equation is derived from + // the rounding tables. + + + assign plus1 = rn && ((v[1] && v[0]) || (v[2] && (v[1]))) || + rp && ~wsign && (v[1] || v[0]) || + rm && wsign && (v[1] || v[0]); + + // Compute rounded result + assign v1 = v[53:2] + 1; + // Determine if postnormalization is necessary + // Predicted by all bits =1 before round +1 + + assign postnormalize = &(v[53:2]) && plus1; + + // Determine special result in event of of selection of a result from + // another FPU functional unit, infinity, NAN, or underflow + // The special result mux is a 4:1 mux that should not appear in the + // critical path of the machine. It is not priority encoded, despite + // the code below suggesting otherwise. Also, several of the identical data + // inputs to the wide muxes can be combined at the expense of more + // complicated non-critical control in the circuit implementation. + + assign specialsel = earlyressel || overflow || underflow || invalid || + nan || inf; + assign specialres = earlyressel ? earlyres : + invalid ? nanres : + overflow ? infinityres : + inf ? 52'b0 : + underflow ? 52'b0 : 52'bx; // default to undefined + + // Overflow is handled differently for different rounding modes + // Round is to either infinity or to maximum finite number + + assign infinity = rn || (rp && ~wsign) || (rm && wsign); + assign infinityres = infinity ? 52'b0 : {52{1'b1}}; + + // Invalid operations produce a quiet NaN. The result should + // propagate an input if the input is NaN. Since we assume all + // NaN inputs are already quiet, we don't have to force them quiet. + + // assign nanres = xnan ? x: (ynan ? y : (znan ? z : {1'b1, 51'b0})); // original + assign nanres = xnan ? {1'b1, x[50:0]}: (ynan ? {1'b1, y[50:0]} : (znan ? {1'b1, z[50:0]} : {1'b1, 51'b0}));// KEP 210112 add the 1 to make NaNs quiet + + // Select result with 4:1 mux + // If the sum is zero and we round up, there is a special case in + // which we produce a massive loss of significance and trap to software. + // It is handled in the exception unit. + + assign w = specialsel ? specialres : (plus1 ? v1[51:0] : v[53:2]); + +endmodule + diff --git a/wally-pipelined/src/fpu/FMA/sign.v b/wally-pipelined/src/fpu/FMA/sign.v new file mode 100644 index 000000000..9503847f4 --- /dev/null +++ b/wally-pipelined/src/fpu/FMA/sign.v @@ -0,0 +1,93 @@ +/////////////////////////////////////////////////////////////////////////////// +// Block Name: sign.v +// Author: David Harris +// Date: 12/1/1995 +// +// Block Description: +// This block manages the signs of the numbers. +// 1 = negative +// +///////////////////////////////////////////////////////////////////////////// + +///////////////////////////////////////////////////////////////////////////// +module sign(xsign, ysign, zsign, negsum0, negsum1, bs, ps, killprod, rm, + sumzero, nan, invalid, xinf, yinf, inf, wsign, invz, negsum, selsum1, psign); +////////////////////////////////////////////////////////////////////////////I + + input xsign; // Sign of X + input ysign; // Sign of Y + input zsign; // Sign of Z + input negsum0; // Sum in +O mode is negative + input negsum1; // Sum in +1 mode is negative + input bs; // sticky bit from addend + input ps; // sticky bit from product + input killprod; // Product forced to zero + input rm; // Round toward minus infinity + input sumzero; // Sum = O + input nan; // Some input is NaN + input invalid; // Result invalid + input xinf; // X = Inf + input yinf; // Y = Inf + input inf; // Some input = Inf + output wsign; // Sign of W + output invz; // Invert addend into adder + output negsum; // Negate result of adder + output selsum1; // Select +1 mode from compound adder + output psign; // sign of product X * Y + + // Internal nodes + + wire zerosign; // sign if result= 0 + wire infsign; // sign if result= Inf + reg negsum; // negate result of adder + reg selsum1; // select +1 mode from compound adder + + // Compute sign of product + + assign psign = xsign ^ ysign; + + // Invert addend if sign of Z is different from sign of product assign invz = zsign ^ psign; + assign invz = zsign ^ psign; + // Select +l mode for adder and compute if result must be negated + // This is done according to cases based on the sticky bit. + + always @(invz or negsum0 or negsum1 or bs or ps) + begin + if (~invz) begin // both inputs have same sign + negsum = 0; + selsum1 = 0; + end else if (bs) begin // sticky bit set on addend + selsum1 = 0; + negsum = negsum0; + end else if (ps) begin // sticky bit set on product + selsum1 = 1; + negsum = negsum1; + end else begin // both sticky bits clear + selsum1 = negsum1; // KEP 210113-10:44 Selsum1 was adding 1 to values that were multiplied by 0 + // selsum1 = ~negsum1; //original + negsum = negsum1; + end + end + + // Compute sign of result + // This involves a special case when the sum is zero: + // x+x retains the same sign as x even when x = +/- 0. + // otherwise, x-x = +O unless in the RM mode when x-x = -0 + // There is also a special case for NaNs and invalid results; + // the sign of the NaN produced is forced to be 0. + // Sign calculation is not in the critical path so the cases + // can be tolerated. + // IEEE 754-2008 section 6.3 states + // "When ether an input or result is NaN, this standard does not interpret the sign of a NaN." + // also pertaining to negZero it states: + // "When the sum/difference of two operands with opposite signs is exactly zero, the sign of that sum/difference + // shall be +0 in all rounding attributes EXCEPT roundTowardNegative. Under that attribute, the sign of an exact zero + // sum/difference shall be -0. However, x+x = x-(-X) retains the same sign as x even when x is zero." + + assign zerosign = (~invz && killprod) ? zsign : rm; + assign infsign = psign; //KEP 210112 keep the correct sign when result is infinity + // assign infsign = xinf ? (yinf ? psign : xsign) : yinf ? ysign : zsign;//original + assign wsign =invalid? 0 : (inf ? infsign: + (sumzero ? zerosign : psign ^ negsum)); + +endmodule diff --git a/wally-pipelined/src/fpu/FMA/special.v b/wally-pipelined/src/fpu/FMA/special.v new file mode 100644 index 000000000..ec588ca9a --- /dev/null +++ b/wally-pipelined/src/fpu/FMA/special.v @@ -0,0 +1,70 @@ +/////////////////////////////////////////////////////////////////////////////// +// Block Name: special.v +// Author: David Harris +// Date: 12/2/1995 +// +// Block Description: +// This block implements special case handling for unusual operands (e.g. +// 0, NaN, denormalize, infinity). The block consists of zero/one detectors. +// +///////////////////////////////////////////////////////////////////////////// + +///////////////////////////////////////////////////////////////////////////// +module special(x[63:0], y[63:0], z[63:0], ae, xzero, yzero, zzero, + xnan, ynan, znan, xdenorm, ydenorm, zdenorm, proddenorm, xinf, yinf, zinf); +///////////////////////////////////////////////////////////////////////////// + + input [63:0] x; // Input x + input [63:0] y; // Input Y + input [63:0] z; // Input z + input [12:0] ae; // exponent of product + output xzero; // Input x = 0 + output yzero; // Input y = 0 + output zzero; // Input z = 0 + output xnan; // x is NaN + output ynan; // y is NaN + output znan; // z is NaN + output xdenorm; // x is denormalized + output ydenorm; // y is denormalized + output zdenorm; // z is denormalized + output proddenorm; // product is denormalized + output xinf; // x is infinity + output yinf; // y is infinity + output zinf; // z is infinity + + // In the actual circuit design, the gates looking at bits + // 51:0 and at bits 62:52 should be shared among the various detectors. + + // Check if input is NaN + + assign xnan = &x[62:52] && |x[51:0]; + assign ynan = &y[62:52] && |y[51:0]; + assign znan = &z[62:52] && |z[51:0]; + + // Check if input is denormalized + + assign xdenorm = ~(|x[62:52]) && |x[51:0]; + assign ydenorm = ~(|y[62:52]) && |y[51:0]; + assign zdenorm = ~(|z[62:52]) && |z[51:0]; + assign proddenorm = &ae & ~xzero & ~yzero; //KEP is the product denormalized + + // Check if input is infinity + + assign xinf = &x[62:52] && ~(|x[51:0]); + assign yinf = &y[62:52] && ~(|y[51:0]); + assign zinf = &z[62:52] && ~(|z[51:0]); + + // Check if inputs are all zero + // Also forces denormalized inputs to zero. + // In the circuit implementation, this can be optimized + // to just check if the exponent is zero. + + // KATHERINE - commented following (21/01/11) + // assign xzero = ~(|x[62:0]) || xdenorm; + // assign yzero = ~(|y[62:0]) || ydenorm; + // assign zzero = ~(|z[62:0]) || zdenorm; + // KATHERINE - removed denorm to prevent outputing zero when computing with a denormalized number + assign xzero = ~(|x[62:0]); + assign yzero = ~(|y[62:0]); + assign zzero = ~(|z[62:0]); + endmodule diff --git a/wally-pipelined/src/fpu/FMA/tb.v b/wally-pipelined/src/fpu/FMA/tb.v new file mode 100644 index 000000000..a28e3c4d2 --- /dev/null +++ b/wally-pipelined/src/fpu/FMA/tb.v @@ -0,0 +1,2824 @@ +`timescale 1 ns/10 ps +module tb; + + + reg [63:0] xrf; + reg [63:0] y; + reg [63:0] zrf; + reg rn; + reg rz; + reg rm; + reg rp; + reg [63:0] earlyres; + reg earlyressel; + reg [1:0] bypsel; + reg bypplus1; + reg byppostnorm; + wire [63:0] w; + wire [63:0] wbypass; + wire invalid; + wire overflow; + wire underflow; + wire inexact; + +reg [5:0] i; +integer fp; + +localparam period = 20; +fmac UUT(.xrf(xrf), .y(y), .zrf(zrf), .rn(rn), .rz(rz), .rp(rp), .rm(rm), + .earlyres(earlyres), .earlyressel(earlyressel), .bypsel(bypsel), .bypplus1(bypplus1), .byppostnorm(byppostnorm), + .w(w), .wbypass(wbypass), .invalid(invalid), .overflow(overflow), .underflow(underflow), .inexact(inexact)); + + +initial + begin +fp = $fopen("output","w"); + xrf = 64'hc22000007fffffff; + y = 64'h24700000ffffffef; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hbfc00000000011fe; + y = 64'h3fdfffffffffff03; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'ha83100000007fffe; + y = 64'h41e0000effffffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0000000000000000; + y = 64'h001ffffffffffffe; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h400327ca64d70ec7; + y = 64'h3ca0000000000001; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0000000000000000; + y = 64'h43e207ffffffffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0000000000000000; + y = 64'h3fd0000000000000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0000000000000000; + y = 64'h3fdfffffffffffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0000000000000000; + y = 64'h3fe0000000000000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc870200000010000; + y = 64'h3fefffffffffffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc00aaa4fd557ef13; + y = 64'hc3b8917384eb32d0; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0000000000000000; + y = 64'h7ffc000000000000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0000000000000000; + y = 64'hc18aca47203438e2; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0000000000000000; + y = 64'h4000000000000001; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h47efff0008000000; + y = 64'hb1dcb0523546117f; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h43f000ffffff7fff; + y = 64'h22300000001fffdf; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h402ff000001fffff; + y = 64'h40759558e27de226; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0000000000000000; + y = 64'h40efdeffffffffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0000000000000000; + y = 64'h434fffffffffffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h7ffc000000000000; + y = 64'h7fe0000000000000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hb35e061abc769f3a; + y = 64'hc078000003fffffe; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h403a793cfb1e2471; + y = 64'hbff0000100007fff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h3d1ffffbfe000000; + y = 64'h216898822a24af3f; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hbfb00000001bffff; + y = 64'h7ffc000000000000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h37f0000000efffff; + y = 64'hc3d00007fffffeff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0000000000000000; + y = 64'hffefff8000080000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h3fb00200000000ff; + y = 64'hc0000000011fffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h41c0000007ffffff; + y = 64'h49103fffefffffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h407effbfffffffff; + y = 64'h3e00000040001fff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc1f00013fffffffe; + y = 64'h7ffc000000000000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc3f00004000001ff; + y = 64'hc3d00bfffffffffe; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h403b5ab30b28be12; + y = 64'hbfdfffffffffffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0000000000000000; + y = 64'hc1cfffffff87ffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0000000000000000; + y = 64'hbfe0000000000001; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h801ffc000007ffff; + y = 64'hbfeffffffffffffe; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0000000000000000; + y = 64'hffe0000005fffffe; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0000000000000000; + y = 64'hbfffffffffffffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0000000000000000; + y = 64'hc000000000000000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc3d09308769f3f51; + y = 64'hc00fffffffffffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0000000000000000; + y = 64'h402ffffdfefffffe; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0000000000000000; + y = 64'hc010000000000001; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc01fffffffc00fff; + y = 64'hc01ffffffffffffe; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc025e14360f49046; + y = 64'h412fff0000000003; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0000000000000000; + y = 64'h43ee59a2f1155c8b; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h3fe0000000008fff; + y = 64'h802ffffff7fffff6; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0000000000000000; + y = 64'hffefffffffffffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h40401007fffffffe; + y = 64'hfff0000000000000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0000000000000000; + y = 64'hc0045abb4860cbf3; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0000000000000000; + y = 64'h7ffc000000000000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hbffffffec0000000; + y = 64'hc000000000003eff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h48000000004001ff; + y = 64'h41f331de979ac49e; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h3d0fffffbff7ffff; + y = 64'h7ffc000000000000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h43d3ffffff000000; + y = 64'h3caffffffffffffe; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h7ffc000000000000; + y = 64'h43dfff8004000000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hbcaffe0000000008; + y = 64'h3fd00008000000ff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h404ffbfffffffffc; + y = 64'hc34ffff8003fffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h43e0000000000082; + y = 64'h3db000003ffffeff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc1d004000ffffffe; + y = 64'h4000000000000000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc00fffffc000007e; + y = 64'hc02ffffdfffffbff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h409dfffbffffffff; + y = 64'h4010000000000001; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc120000003ffffe0; + y = 64'hc06000fffbffffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h3fd1f7ffffffffff; + y = 64'hc01000001dffffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h2e0fefdfffffffff; + y = 64'h4030000020000040; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h43c0000803ffffff; + y = 64'h3fcfffffffffffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc0afffffbffffdfe; + y = 64'h3fc07ffdffffffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc0fffffffeffffee; + y = 64'h55139bb9349e058c; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h41ffdbaf18ce06bd; + y = 64'h8010000000000000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc0e1000000080000; + y = 64'h801ffffffffffffe; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h3fbffffff0000007; + y = 64'hc807dfffffffffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc357b53537b96da5; + y = 64'hbfd0000000000000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h401fffffffffffff; + y = 64'hffebff8000000000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc7eff77bf2b59c3c; + y = 64'hbfe0000000000001; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h380c3f72cc3dec98; + y = 64'hc3fffffffbffffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hb8e0000003fbffff; + y = 64'hc503f4d44f4bf888; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h3f3ffffc001fffff; + y = 64'hc000000000000001; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc340002000004000; + y = 64'hc0db3367e0423019; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h4f60000801ffffff; + y = 64'h41c07fe000000000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc1ffffffbfefffff; + y = 64'hc340000000000001; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h404fff7fffffff7f; + y = 64'h48ab7e2aad4ec686; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h7ffc000000000000; + y = 64'hffefffffffffffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h41e189ea1a6fff97; + y = 64'h7ffc000000000000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h3ff0ee9046c9330f; + y = 64'h8479e1e79766e02b; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hd2f805130a8c11df; + y = 64'h43effffdfdfffffe; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h4f1fffbfffe00000; + y = 64'hbcd02000000007ff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hbe70000077ffffff; + y = 64'hc1efffffffffffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h41e1ffffbffffffe; + y = 64'h3caffffffffffffe; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h3bbd976272fb1d2a; + y = 64'hc06ffff80007fffe; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h434fff01ffffffff; + y = 64'h403dfeffffffffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hbe6fff7fffffffff; + y = 64'h3feffffffffffffe; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h41d007ff80000000; + y = 64'h41f0fffffffc0000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hffeef7a206029708; + y = 64'hbdcfa4109a3a5b22; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h3b6ffffffeffffc0; + y = 64'h3c7ffffe003ffffe; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc1d1ffffffbfffff; + y = 64'hbfcffffefffff800; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h2030000000000090; + y = 64'hc05e2e90015c47a1; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hbbf000000007efff; + y = 64'h001fe0000007fffe; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h41cae866712069f4; + y = 64'hc02fffffffffffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hbfce1e32ccf56348; + y = 64'h3ca1f66d4c8eeef3; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hffedfffff0000000; + y = 64'hffeffff000000800; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h37effffc3ffffffe; + y = 64'hbca0fffffffffffd; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hbc950a021bf9dee1; + y = 64'h3db0001fffdffffe; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hfd4fffffdfffffef; + y = 64'h41cffffdffffffef; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hbfc00000004007ff; + y = 64'hbcafffffffffffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc009130b80fe8274; + y = 64'hb811571307061a38; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc0600000ffffffdf; + y = 64'h7feda1b8c591f9c6; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc1e4af3f8d45e031; + y = 64'h3ca0020002000000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h3800008100000000; + y = 64'hb810000020000080; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h372ff00000003fff; + y = 64'h7fe000fdfffffffe; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h47d00021fffffffe; + y = 64'hc00fffffffffffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hbfbc9ea0c2b4884b; + y = 64'h43f4a552574073d5; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hbf1fe0000000ffff; + y = 64'hc01ffffffffffffe; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h41ffffffff7ffffb; + y = 64'h0027ffffffffeffe; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc7e040000fffffff; + y = 64'hffe0000000000000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h7ffc000000000000; + y = 64'h3fe0000ffffff7ff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc1effc1fffffffff; + y = 64'h7ffc000000000000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc0d000000001ffbf; + y = 64'hc03ba46e644e4e9c; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc4500000005fffff; + y = 64'hc03a20ab4de47fc9; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h400e00000000007e; + y = 64'h001fffffffffffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h45a01fffff7fffff; + y = 64'hc3c0020200000000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h3e8ff800000000ff; + y = 64'h3caffffffffffffe; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hbe004000000007fe; + y = 64'h3fdffff7ff7fffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hb11000007ffffe00; + y = 64'h3fe0000000000000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hb80cef50bd17db40; + y = 64'hc05fffc00000000e; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h3d4000ffffffffff; + y = 64'h3d47f68d8eb6b9a4; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hffe3fffffffffffb; + y = 64'hc03dc3321aaa5380; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h3ca3fffffffffeff; + y = 64'hbf02ffafb4e9241d; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h53598c812c3c39dd; + y = 64'h3f20000100fffffe; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc3dffffff8000001; + y = 64'h3fe0020000003ffe; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h7ba00800003fffff; + y = 64'h3ff9a9a129c791b3; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc3d0000fffffffef; + y = 64'h7fe0000000000001; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc34f80001fffffff; + y = 64'hb7fffffe0007ffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0010000000001ff8; + y = 64'h4800020000010000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h2c4c0000003fffff; + y = 64'h230ffffc00400000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h381fffffffbff7fe; + y = 64'h8010000000000000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h802d3018ea8c241d; + y = 64'hc007fdffffffffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h43e047fffffffffe; + y = 64'h4000003ffdfffffe; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc000005fffffffff; + y = 64'h403ffffffff00002; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h3fc8b60e46a80f6d; + y = 64'hbfdffffffffffffe; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hbd5fdffdffffffff; + y = 64'h5644b72ace1bbb6b; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hb80010001fffffff; + y = 64'h40e01ffffff7fffe; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h407000003ffbfffe; + y = 64'h38042862fe8e3368; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hbf8ffbfff7ffffff; + y = 64'hc00fffffffffffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hbcafc000003fffff; + y = 64'hc010000000000001; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h47eddf042473ef08; + y = 64'hb7e00000fe000000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h3fbfffff7fffffef; + y = 64'hc340ffffffffffbf; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc02f8000000007ff; + y = 64'hffe0000000000001; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h002f37ebf6c8eaec; + y = 64'hc08be464f4c81c69; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc00e800000000000; + y = 64'h7ffc000000000000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0010000000000000; + y = 64'h0000000000000000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hbfffc00000000003; + y = 64'h391001ffffffffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc1db54446247aa52; + y = 64'hbfcc001fffffffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0010000000000000; + y = 64'hc0392c59c8e48f37; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0010000000000000; + y = 64'hc0000800000001ff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0010000000000000; + y = 64'hc1d0000004000fff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h4030040000200000; + y = 64'h0017055f48beeff5; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hbc7000000000ffee; + y = 64'hc1e0001100000000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc040000000007fff; + y = 64'hc3b2a6c91c557f56; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h41ffffffff003fff; + y = 64'hc3b0000007ffffee; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h21900001dfffffff; + y = 64'hbf20000017fffffe; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0029954d0f0df5b3; + y = 64'h41e00000000003ff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hb810000020000001; + y = 64'h47ffdfffffffff80; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0010000000000000; + y = 64'hffeffff800007fff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0010000000000000; + y = 64'h4010000000000000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hbf700000000100ff; + y = 64'h401fffffffffffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h37feffffffffffff; + y = 64'h47ef8000000fffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hb80f800001fffffe; + y = 64'h44e00000ffff7fff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0010000000000000; + y = 64'h434ffffffffffffe; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h41ffffdfffff8000; + y = 64'h7fe0000000000001; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hb80a16ad02c87cd3; + y = 64'h380fffffffffe7fe; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h47f0fffffffffffb; + y = 64'h7ffc000000000000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0010000000000000; + y = 64'h41ffffffffbfff7f; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0010000000000000; + y = 64'h8000000000000000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc3d00001000001ff; + y = 64'hb7f60cb3edb38762; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0010000000000000; + y = 64'h8010000000000001; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h43c0007fffdfffff; + y = 64'h801ffffffffffffe; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc7efffffdffffbff; + y = 64'hbca0000000000001; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0010000000000000; + y = 64'hc11ff00000000003; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0010000000000000; + y = 64'hbfd0000000000000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc0ffffffffeffffe; + y = 64'hbfdfffffffffffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h6f7000000001fdff; + y = 64'h1510010000000fff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h37f002000000000f; + y = 64'hb1effcfffffffffe; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hcc3050bc013d7cd7; + y = 64'hbff0000000000000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0010000000000000; + y = 64'h87fff0000000fffe; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0010000000000000; + y = 64'hbffffffffffffffe; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h43effbfffffff7ff; + y = 64'h7fefffffff801ffe; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc015834380f2b995; + y = 64'h3f9fff0000000400; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0010000000000000; + y = 64'h41dfffffc0001000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0010000000000000; + y = 64'hc01fffffffffffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h41e010000000001f; + y = 64'hc5b04000000fffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h3b40018000000000; + y = 64'h3ea0400000000100; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0010000000000000; + y = 64'h4cdffeffff7fffff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h16dff0001ffffffe; + y = 64'h3fb500ae0796659d; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hb7e003ffffffff7f; + y = 64'hdeafffffeffffffd; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h406000001fffbfff; + y = 64'h3f20020000080000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h0010000000000000; + y = 64'h7ffc000000000000; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h439fbffffffbffff; + y = 64'hbf8454fd38ef0ba0; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hc1c000000200007e; + y = 64'hbf000001ffffffbf; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h480000000008fffe; + y = 64'h001637e790e69de2; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'hbffffffc000003fe; + y = 64'h3ca0000000000001; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + xrf = 64'h6b4848a9a8c0dcd5; + y = 64'h480ffffffffbdfff; + zrf = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + $fwrite(fp, "%h %h %h\n",xrf,y,w); + $stop; + end +endmodule \ No newline at end of file diff --git a/wally-pipelined/src/fpu/FMA/tbgen/StineVectors b/wally-pipelined/src/fpu/FMA/tbgen/StineVectors new file mode 100644 index 000000000..5014f01df --- /dev/null +++ b/wally-pipelined/src/fpu/FMA/tbgen/StineVectors @@ -0,0 +1,1997 @@ +b68ffff8000000ff_3f9080000007ffff_b6307ffbe0080080_00001 +0000000000000000_a57f319ede38f755_0000000000000000_00000 +41e00003fffbffff_bfdfffffffefffff_c1d00003fff3fffc_00001 +80251295103185ae_0000000000000000_0000000000000000_00000 +c040000000001000_802fff7fffffffc0_007fff8000001fc0_00001 +0000000000000000_0000000000000000_0000000000000000_00000 +c1dfffffffe00080_3fa48edf3623f067_c1948edf360f61da_00001 +0000000000000000_47fffffffff9fffe_0000000000000000_00000 +43d36fa3cad3f59e_802ffdfffbfffffe_84136e6cce2953e4_00001 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+ char zrf[17]; + char ans[81]; + char flags[3]; + int rn,rz,rm,rp; + { + //my_string = (char *) malloc (nbytes + 1); + //bytes_read = getline (&my_string, &nbytes, stdin); + if(getline(&ln,&nbytes,fp) < 0) break; + //fprintf(stderr,"%s\n", ln); + + strncpy(xrf, ln, 16); xrf[16]=0; + strncpy(y, &ln[17], 16); y[16]=0; + strncpy(zrf, &ln[34], 16); zrf[16]=0; + // fprintf(stdout,"[%s]\n[%s]\n", ln,zrf); + strncpy(ans, &ln[51], 16); ans[16]=0; + strncpy(flags,&ln[68],2); flags[2]=0; + + // fprintf(stdout,"[%s]\n[%s]\n", ln,zrf); + fprintf(fq," xrf = 64'h%s;\n",xrf); + fprintf(fq," y = 64'h%s;\n",y); + fprintf(fq," zrf = 64'h%s;\n",zrf); + fprintf(fq," ans = 64'h%s;\n", ans); + // fprintf(fq," flags = 5'h%s;\n", flags); + } + + { + //rn=1; rz=0; rm=0; rp=0; + fprintf(fq," rn = %d;\n",1); + fprintf(fq," rz = %d;\n", 0); + fprintf(fq," rm = %d;\n", 0); + fprintf(fq," rp = %d;\n", 0); + } + { + fprintf(fq," earlyres = 64'b0;\n"); + fprintf(fq," earlyressel = 0;\n"); + } + { + + fprintf(fq," bypsel= 2'b0;\n"); //, bysel); + fprintf(fq," bypplus1 = 0;\n"); //, byp1); + fprintf(fq," byppostnorm = 0;\n"); //, bypnorm); + } + fprintf(fq,"#10\n"); + // IEEE 754-2008 section 6.3 states "When ether an input or result is NaN, this standard does not interpret the sign of a NaN." + //fprintf(fq," $fwrite(fp, \"%%h %%h %%h %%h \",xrf,y,w, ans);\n"); + fprintf(fq," // IEEE 754-2008 section 6.3 states: \"When ether an input or result is NaN, this\n"); + fprintf(fq," // standard does not interpret the sign of a NaN.\"\n"); + fprintf(fq," nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) ||\n"); + fprintf(fq," (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) ||\n"); + fprintf(fq," (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) ||\n"); + fprintf(fq," (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff );\n"); + // fprintf(fq," if(!(~(|xrf[62:52]) && |xrf[51:0] || ~(|y[62:52]) && |y[51:0])) begin\n"); + // not looknig at negative zero results right now + //fprintf(fq," if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) && !(w == 64'h8000000000000000 && ans == 64'b0)) begin\n"); + fprintf(fq," if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin\n"); + fprintf(fq," $fwrite(fp, \"%%h %%h %%h %%h %%h Wrong \",xrf,y, zrf, w, ans);\n"); + fprintf(fq," if(w == 64'h8000000000000000) $fwrite(fp, \"w=-zero \");\n"); + fprintf(fq," if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, \"xdenorm \");\n"); + fprintf(fq," if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, \"ydenorm \");\n"); + fprintf(fq," if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, \"zdenorm \");\n"); + fprintf(fq," if(invalid != 0) $fwrite(fp, \"invld \");\n"); + fprintf(fq," if(overflow != 0) $fwrite(fp, \"ovrflw \");\n"); + fprintf(fq," if(underflow != 0) $fwrite(fp, \"unflw \");\n"); + fprintf(fq," if(w == 64'hFFF0000000000000) $fwrite(fp, \"w=-inf \");\n"); + fprintf(fq," if(w == 64'h7FF0000000000000) $fwrite(fp, \"w=+inf \");\n"); + fprintf(fq," if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, \"w=sigNaN \");\n"); + fprintf(fq," if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, \"w=sigNaN \");\n"); + fprintf(fq," if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, \"w=qutNaN \");\n"); + fprintf(fq," if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, \"w=qutNaN \");\n"); + + fprintf(fq," if(ans == 64'hFFF0000000000000) $fwrite(fp, \"ans=-inf \");\n"); + fprintf(fq," if(ans == 64'h7FF0000000000000) $fwrite(fp, \"ans=+inf \");\n"); + fprintf(fq," if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, \"ans=sigNaN \");\n"); + fprintf(fq," if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, \"ans=sigNaN \");\n"); + fprintf(fq," if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, \"ans=qutNaN \");\n"); + fprintf(fq," if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, \"ans=qutNaN \");\n"); + fprintf(fq," $fwrite(fp,\"%d\\n\");\n",cnt); + if(cnt == 358)fprintf(fq," $stop;\n"); + // fprintf(fq," end\n"); + fprintf(fq," end\n"); + cnt++; + + //if(cnt > 100) break; + fflush(fq); + } + + fprintf(fq, "\t$stop;\n\tend\nendmodule"); + fclose(fq); + fclose(fp); +} + diff --git a/wally-pipelined/src/fpu/FMA/tbgen/tb.v b/wally-pipelined/src/fpu/FMA/tbgen/tb.v new file mode 100644 index 000000000..136f13317 --- /dev/null +++ b/wally-pipelined/src/fpu/FMA/tbgen/tb.v @@ -0,0 +1,3952 @@ +`timescale 1 ns/10 ps +module tb; + + + reg [63:0] xrf; + reg [63:0] y; + reg [63:0] zrf; + reg [63:0] ans; + reg rn; + reg rz; + reg rm; + reg rp; + reg [63:0] earlyres; + reg earlyressel; + reg [1:0] bypsel; + reg bypplus1; + reg byppostnorm; + wire [63:0] w; + wire [63:0] wbypass; + wire invalid; + wire overflow; + wire underflow; + wire inexact; + +integer fp; +reg nan; + +localparam period = 20; +fmac UUT(.xrf(xrf), .y(y), .zrf(zrf), .rn(rn), .rz(rz), .rp(rp), .rm(rm), + .earlyres(earlyres), .earlyressel(earlyressel), .bypsel(bypsel), .bypplus1(bypplus1), .byppostnorm(byppostnorm), + .w(w), .wbypass(wbypass), .invalid(invalid), .overflow(overflow), .underflow(underflow), .inexact(inexact)); + + +initial + begin + fp = $fopen("/home/kparry/code/FMAC/tbgen/results.dat","w"); + xrf = 64'h400FEFFFFFFDFFFF; + y = 64'h4500001EFFFFFFFF; + zrf = 64'h0000000000000000; + ans = 64'h451FF03DE0FDFFF9; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"0\n"); + end + xrf = 64'h0000000000000000; + y = 64'h0000000000000000; + zrf = 64'h44223BDB544F0B29; + ans = 64'h44223BDB544F0B29; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"1\n"); + end + xrf = 64'hC2EA48415773CAAE; + y = 64'hF7FFFFFFF0000010; + zrf = 64'hC3EFFFDFFFFFFFFE; + ans = 64'h7AFA48414A4FAA0F; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"2\n"); + end + xrf = 64'h7FF8CDB067A39BAF; + y = 64'h0000000000000000; + zrf = 64'h0000000000000000; + ans = 64'h7FF8CDB067A39BAF; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"3\n"); + end + xrf = 64'h0000000000000000; + y = 64'hCFAFEFFEFFFFFFFE; + zrf = 64'hC0FFFFFFBF7FFFFE; + ans = 64'hC0FFFFFFBF7FFFFE; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"4\n"); + end + xrf = 64'h3FC00000000FFDFF; + y = 64'h0000000000000000; + zrf = 64'hBCA1570F41BFB2DC; + ans = 64'hBCA1570F41BFB2DC; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"5\n"); + end + xrf = 64'h0000000000000000; + y = 64'hBFDFFFFDFFFFFEFF; + zrf = 64'h0000000000000000; + ans = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"6\n"); + end + xrf = 64'h3FDBFFFFFFFFFF7F; + y = 64'hDE608000000001FF; + zrf = 64'h43CFED83C17EDBD0; + ans = 64'hDE4CE000000002F9; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"7\n"); + end + xrf = 64'h0000000000000000; + y = 64'h0000000000000000; + zrf = 64'h0000000000000000; + ans = 64'h0000000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"8\n"); + end + xrf = 64'hBFDC091B6B9B61DA; + y = 64'hBF41FFFFFFFFFFDE; + zrf = 64'h0000000000000001; + ans = 64'h3F2F8A3ED90ECDDA; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"9\n"); + end + xrf = 64'h0000000000000000; + y = 64'h0000000000000000; + zrf = 64'hC00FD6C97456B6F8; + ans = 64'hC00FD6C97456B6F8; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"10\n"); + end + xrf = 64'hC3E8F36E6B907786; + y = 64'h3FC5C725C515C2B9; + zrf = 64'h7FE0000040080000; + ans = 64'h7FE0000040080000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"11\n"); + end + xrf = 64'hC6E000000000BFFF; + y = 64'h0000000000000000; + zrf = 64'h0000000000000001; + ans = 64'h0000000000000001; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"12\n"); + end + xrf = 64'h0000000000000000; + y = 64'h43400000FFFEFFFF; + zrf = 64'h47E61D287E42ED93; + ans = 64'h47E61D287E42ED93; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"13\n"); + end + xrf = 64'h42BC000000003FFF; + y = 64'h0000000000000000; + zrf = 64'hB1E9BC9A428F5884; + ans = 64'hB1E9BC9A428F5884; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"14\n"); + end + xrf = 64'h0000000000000000; + y = 64'h402E266600DC8429; + zrf = 64'h0000000000000001; + ans = 64'h0000000000000001; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"15\n"); + end + xrf = 64'h3FE0000000008002; + y = 64'h7A300001FFFF8000; + zrf = 64'h151001FFFDFFFFFF; + ans = 64'h7A20000200000002; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"16\n"); + end + xrf = 64'h0000000000000000; + y = 64'h0000000000000000; + zrf = 64'h0000000000000001; + ans = 64'h0000000000000001; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"17\n"); + end + xrf = 64'h0020000803FFFFFF; + y = 64'hBFCB4181A9468E24; + zrf = 64'h000FFFFFFFFFFFFF; + ans = 64'h00092F9C2BCA0F33; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"18\n"); + end + xrf = 64'h0000000000000000; + y = 64'h0000000000000000; + zrf = 64'hC00FFFFDFFC00000; + ans = 64'hC00FFFFDFFC00000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"19\n"); + end + xrf = 64'h403FFEFFFFFDFFFF; + y = 64'h480FFFFFFFFFFBFA; + zrf = 64'h38059A71C7F5B8A0; + ans = 64'h485FFEFFFFFDFBF9; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"20\n"); + end + xrf = 64'h8FB0000BFFFFFFFF; + y = 64'h0000000000000000; + zrf = 64'h000FFFFFFFFFFFFF; + ans = 64'h000FFFFFFFFFFFFF; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"21\n"); + end + xrf = 64'h0000000000000000; + y = 64'h4010000007FEFFFE; + zrf = 64'hC05FFFF7F7FFFFFF; + ans = 64'hC05FFFF7F7FFFFFF; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"22\n"); + end + xrf = 64'h43DFFFFFFFC01FFF; + y = 64'h0000000000000000; + zrf = 64'hC010003FFFFFF7FE; + ans = 64'hC010003FFFFFF7FE; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"23\n"); + end + xrf = 64'h0000000000000000; + y = 64'hC14FFFFFFFFFF77F; + zrf = 64'h000FFFFFFFFFFFFF; + ans = 64'h000FFFFFFFFFFFFF; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"24\n"); + end + xrf = 64'hC80F0000FFFFFFFF; + y = 64'h80800003FFFFFFF6; + zrf = 64'h3FEFFFFF00000400; + ans = 64'h3FEFFFFF00000400; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"25\n"); + end + xrf = 64'h0000000000000000; + y = 64'h0000000000000000; + zrf = 64'h000FFFFFFFFFFFFF; + ans = 64'h000FFFFFFFFFFFFF; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"26\n"); + end + xrf = 64'h3FA000004000FFFF; + y = 64'hBEBBDADC34FC7443; + zrf = 64'h000FFFFFFFFFFFFE; + ans = 64'hBE6BDADCA469A2C3; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"27\n"); + end + xrf = 64'h0000000000000000; + y = 64'h0000000000000000; + zrf = 64'hBFD00000F7FFFFFF; + ans = 64'hBFD00000F7FFFFFF; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"28\n"); + end + xrf = 64'hBFCFFFFFE0000800; + y = 64'hC349D6DCD4B1B809; + zrf = 64'h2DB0000101000000; + ans = 64'h4329D6DCBADAE1AA; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"29\n"); + end + xrf = 64'h37EF000040000000; + y = 64'h0000000000000000; + zrf = 64'h000FFFFFFFFFFFFE; + ans = 64'h000FFFFFFFFFFFFE; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"30\n"); + end + xrf = 64'h0000000000000000; + y = 64'h40B1D54BCBAB279F; + zrf = 64'h0DF0400000000FFF; + ans = 64'h0DF0400000000FFF; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"31\n"); + end + xrf = 64'hC1C0000002000007; + y = 64'h0000000000000000; + zrf = 64'h7FF0020007FFFFFF; + ans = 64'h7FF8020007FFFFFF; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"32\n"); + end + xrf = 64'h0000000000000000; + y = 64'hFFD00001FFFFEFFF; + zrf = 64'h000FFFFFFFFFFFFE; + ans = 64'h000FFFFFFFFFFFFE; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"33\n"); + end + xrf = 64'hB89FFE0000800000; + y = 64'hC000000008000010; + zrf = 64'h40BFFFF000000000; + ans = 64'h40BFFFF000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"34\n"); + end + xrf = 64'h0000000000000000; + y = 64'h0000000000000000; + zrf = 64'h000FFFFFFFFFFFFE; + ans = 64'h000FFFFFFFFFFFFE; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"35\n"); + end + xrf = 64'h7FFFFFE0000FFFFF; + y = 64'h403000001EFFFFFF; + zrf = 64'h0010000000000000; + ans = 64'h7FFFFFE0000FFFFF; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"36\n"); + end + xrf = 64'h0000000000000000; + y = 64'h0000000000000000; + zrf = 64'hC1E00000003FFF00; + ans = 64'hC1E00000003FFF00; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"37\n"); + end + xrf = 64'h41DF6C9ACFECE989; + y = 64'hDDD000007FF80000; + zrf = 64'h3811FFFFBFFFFFFF; + ans = 64'hDFBF6C9BCB4209BB; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"38\n"); + end + xrf = 64'hBFE000007F7FFFFE; + y = 64'h0000000000000000; + zrf = 64'h0010000000000000; + ans = 64'h0010000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"39\n"); + end + xrf = 64'h0000000000000000; + y = 64'h7FDFFFFFF7FFF7FF; + zrf = 64'hC0ED55FCCA2B50EB; + ans = 64'hC0ED55FCCA2B50EB; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"40\n"); + end + xrf = 64'h3D20800000000007; + y = 64'h0000000000000000; + zrf = 64'hC7FB24E113B21D95; + ans = 64'hC7FB24E113B21D95; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"41\n"); + end + xrf = 64'h0000000000000000; + y = 64'h38F53256F1FD8142; + zrf = 64'h0010000000000000; + ans = 64'h0010000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"42\n"); + end + xrf = 64'hC7F01FFFFFFFDFFF; + y = 64'hC1ABF0533F99CA52; + zrf = 64'hC7AFFFFFFFBFFFBF; + ans = 64'h49AC2833E5F8C604; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"43\n"); + end + xrf = 64'h0000000000000000; + y = 64'h0000000000000000; + zrf = 64'h0010000000000000; + ans = 64'h0010000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"44\n"); + end + xrf = 64'hC3C000800000001E; + y = 64'hC00000004000FFFE; + zrf = 64'h0010000000000001; + ans = 64'h43D0008040030024; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"45\n"); + end + xrf = 64'h0000000000000000; + y = 64'h0000000000000000; + zrf = 64'h38069508D6E94770; + ans = 64'h38069508D6E94770; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"46\n"); + end + xrf = 64'h47ED0C441E79F5B4; + y = 64'h3FEB3443F10FF3AF; + zrf = 64'h381314487C5CB930; + ans = 64'h47E8B1CB14E9E948; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"47\n"); + end + xrf = 64'hE27F800000001FFF; + y = 64'h0000000000000000; + zrf = 64'h0010000000000001; + ans = 64'h0010000000000001; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"48\n"); + end + xrf = 64'h0000000000000000; + y = 64'h3FDF58F9EF4BA87A; + zrf = 64'h47E0001FFFFFC000; + ans = 64'h47E0001FFFFFC000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"49\n"); + end + xrf = 64'h405FFFFFFFFF7DFF; + y = 64'h0000000000000000; + zrf = 64'hB80FFFFFDFFF7FFF; + ans = 64'hB80FFFFFDFFF7FFF; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"50\n"); + end + xrf = 64'h0000000000000000; + y = 64'h4CA00000000020FF; + zrf = 64'h0010000000000001; + ans = 64'h0010000000000001; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"51\n"); + end + xrf = 64'h4F7FFFFFFFFFE008; + y = 64'hBD9FFBF7FFFFFFFE; + zrf = 64'h3CA9EF3DF0B18874; + ans = 64'hCD2FFBF7FFFFE00A; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"52\n"); + end + xrf = 64'h0000000000000000; + y = 64'h0000000000000000; + zrf = 64'h0010000000000001; + ans = 64'h0010000000000001; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"53\n"); + end + xrf = 64'h43D001FFFFFEFFFE; + y = 64'hB3B001FFFC000000; + zrf = 64'h001FFFFFFFFFFFFF; + ans = 64'hB79004003BFE7FDE; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"54\n"); + end + xrf = 64'h0000000000000000; + y = 64'h0000000000000000; + zrf = 64'hBFE42B7098B68BA8; + ans = 64'hBFE42B7098B68BA8; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"55\n"); + end + xrf = 64'h985FFFFFBFFFFFF7; + y = 64'h3FBBEEC107717254; + zrf = 64'hBFD0100000001FFF; + ans = 64'hBFD0100000001FFF; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"56\n"); + end + xrf = 64'hB81FFFFFFFFFE000; + y = 64'h0000000000000000; + zrf = 64'h001FFFFFFFFFFFFF; + ans = 64'h001FFFFFFFFFFFFF; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"57\n"); + end + xrf = 64'h0000000000000000; + y = 64'h2BDD9A85D2E4683C; + zrf = 64'hFFDFFFFFE0000004; + ans = 64'hFFDFFFFFE0000004; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"58\n"); + end + xrf = 64'h380FFFFFFF8001FF; + y = 64'h0000000000000000; + zrf = 64'h1B5B3B4837FBA184; + ans = 64'h1B5B3B4837FBA184; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"59\n"); + end + xrf = 64'h0000000000000000; + y = 64'h43DF7FFFFFFFFFC0; + zrf = 64'h001FFFFFFFFFFFFF; + ans = 64'h001FFFFFFFFFFFFF; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"60\n"); + end + xrf = 64'hB7E49210AC9E1B87; + y = 64'hBF3FFFFFFE001FFF; + zrf = 64'hB23FFFFCFFFFFFFE; + ans = 64'h37349210AB550F0E; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"61\n"); + end + xrf = 64'h0000000000000000; + y = 64'h0000000000000000; + zrf = 64'h001FFFFFFFFFFFFF; + ans = 64'h001FFFFFFFFFFFFF; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"62\n"); + end + xrf = 64'h403251D97A5E1D0C; + y = 64'h404705F7FFDBD87F; + zrf = 64'h001FFFFFFFFFFFFE; + ans = 64'h408A5C7E285F0A79; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"63\n"); + end + xrf = 64'h0000000000000000; + y = 64'h0000000000000000; + zrf = 64'hFFEFFFFFFFFFF7EE; + ans = 64'hFFEFFFFFFFFFF7EE; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"64\n"); + end + xrf = 64'h402017FFFFFFFFFF; + y = 64'h3831000FFFFFFFFF; + zrf = 64'h38159741BD9D38BC; + ans = 64'h3861C64A25ECE9C4; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"65\n"); + end + xrf = 64'h3FBFEFFFFFFFFFF0; + y = 64'h0000000000000000; + zrf = 64'h001FFFFFFFFFFFFE; + ans = 64'h001FFFFFFFFFFFFE; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"66\n"); + end + xrf = 64'h0000000000000000; + y = 64'h43226FDD109DA24F; + zrf = 64'hD9BFFC01FFFFFFFF; + ans = 64'hD9BFFC01FFFFFFFF; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"67\n"); + end + xrf = 64'h5590001EFFFFFFFF; + y = 64'h0000000000000000; + zrf = 64'h0FB4EBC00336E272; + ans = 64'h0FB4EBC00336E272; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"68\n"); + end + xrf = 64'h0000000000000000; + y = 64'h3FB2B6972F81C429; + zrf = 64'h001FFFFFFFFFFFFE; + ans = 64'h001FFFFFFFFFFFFE; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"69\n"); + end + xrf = 64'hB6EFFFFFFFFFFDDF; + y = 64'h7FD100000000003E; + zrf = 64'hC070000000003FF6; + ans = 64'hF6D0FFFFFFFFFF1C; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"70\n"); + end + xrf = 64'h0000000000000000; + y = 64'h0000000000000000; + zrf = 64'h001FFFFFFFFFFFFE; + ans = 64'h001FFFFFFFFFFFFE; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"71\n"); + end + xrf = 64'h418023FFFFFFFFFF; + y = 64'h41D077FFFFFFFFFE; + zrf = 64'h3CA0000000000000; + ans = 64'h43609D0DFFFFFFFD; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"72\n"); + end + xrf = 64'h0000000000000000; + y = 64'h0000000000000000; + zrf = 64'h3D20000020100000; + ans = 64'h3D20000020100000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"73\n"); + end + xrf = 64'h3FDFFFFFFFFFC03F; + y = 64'hC1EFFFFFFFFFFC3F; + zrf = 64'hC00000007FFEFFFE; + ans = 64'hC1E00000003FDE41; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"74\n"); + end + xrf = 64'h41C0000000000002; + y = 64'h0000000000000000; + zrf = 64'h3CA0000000000000; + ans = 64'h3CA0000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"75\n"); + end + xrf = 64'h0000000000000000; + y = 64'h403978692A8E71A0; + zrf = 64'hC05EA17BB565F286; + ans = 64'hC05EA17BB565F286; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"76\n"); + end + xrf = 64'h47E70A2E50D58207; + y = 64'h0000000000000000; + zrf = 64'h3C13ABADB322843E; + ans = 64'h3C13ABADB322843E; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"77\n"); + end + xrf = 64'h0000000000000000; + y = 64'hBE8FFFFC00800000; + zrf = 64'h3CA0000000000000; + ans = 64'h3CA0000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"78\n"); + end + xrf = 64'hBFF000101FFFFFFE; + y = 64'hC00BFFFFFFFFFF7F; + zrf = 64'h3F1BAA5CC75710E9; + ans = 64'h400C00538CB98E2A; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"79\n"); + end + xrf = 64'h0000000000000000; + y = 64'h0000000000000000; + zrf = 64'h3CA0000000000000; + ans = 64'h3CA0000000000000; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"80\n"); + end + xrf = 64'hBE303FFFFF7FFFFF; + y = 64'hC7E0100FFFFFFFFE; + zrf = 64'h3CA0000000000001; + ans = 64'h462050503F7F7F7D; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"81\n"); + end + xrf = 64'h0000000000000000; + y = 64'h0000000000000000; + zrf = 64'hC1D007FFFFFBFFFE; + ans = 64'hC1D007FFFFFBFFFE; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"82\n"); + end + xrf = 64'h46D0400FFFFFFFFE; + y = 64'hC0B6AB0CA0885B97; + zrf = 64'h3FD0000080000000; + ans = 64'hC79705CF7E171D8B; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"83\n"); + end + xrf = 64'hCFB00000080FFFFF; + y = 64'h0000000000000000; + zrf = 64'h3CA0000000000001; + ans = 64'h3CA0000000000001; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"84\n"); + end + xrf = 64'h0000000000000000; + y = 64'h3FC000000000403F; + zrf = 64'hC1F0000000000107; + ans = 64'hC1F0000000000107; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"85\n"); + end + xrf = 64'h8160000200020000; + y = 64'h0000000000000000; + zrf = 64'hC3C00000002FFFFE; + ans = 64'hC3C00000002FFFFE; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"86\n"); + end + xrf = 64'h0000000000000000; + y = 64'h43401000000001FF; + zrf = 64'h3CA0000000000001; + ans = 64'h3CA0000000000001; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"87\n"); + end + xrf = 64'h4289103C0B784F2D; + y = 64'h4030000001FFFFFE; + zrf = 64'hC7F61FD7734A9B57; + ans = 64'hC7F61FD7734A9B57; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"88\n"); + end + xrf = 64'h0000000000000000; + y = 64'h0000000000000000; + zrf = 64'h3CA0000000000001; + ans = 64'h3CA0000000000001; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans > 64'hFFF8000000000000 && ans < 64'hFFF8000000000000 ) $fwrite(fp, "ans=sigNaN "); + if(ans >= 64'h7FF8000000000000 && ans <= 64'h7FFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + if(ans >= 64'hFFF8000000000000 && ans <= 64'hFFFfffffffffffff ) $fwrite(fp, "ans=qutNaN "); + $fwrite(fp,"89\n"); + end + xrf = 64'h880E1FFFFFFFFFFE; + y = 64'h8CDFFFFF7FF7FFFF; + zrf = 64'h3CAFFFFFFFFFFFFF; + ans = 64'h3CAFFFFFFFFFFFFF; + rn = 1; + rz = 0; + rm = 0; + rp = 0; + earlyres = 64'b0; + earlyressel = 0; + bypsel= 2'b0; + bypplus1 = 0; + byppostnorm = 0; +#10 + // IEEE 754-2008 section 6.3 states: "When ether an input or result is NaN, this + // standard does not interpret the sign of a NaN." + nan = (w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000) || + (w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) || + (w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) || + (w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ); + if( (nan && (w[62:0] != ans[62:0])) || (!nan && (w != ans)) ) begin + $fwrite(fp, "%h %h %h %h %h Wrong ",xrf,y, zrf, w, ans); + if(w == 64'h8000000000000000) $fwrite(fp, "w=-zero "); + if(~(|xrf[62:52]) && |xrf[51:0]) $fwrite(fp, "xdenorm "); + if(~(|y[62:52]) && |y[51:0]) $fwrite(fp, "ydenorm "); + if(~(|zrf[62:52]) && |zrf[51:0]) $fwrite(fp, "zdenorm "); + if(invalid != 0) $fwrite(fp, "invld "); + if(overflow != 0) $fwrite(fp, "ovrflw "); + if(underflow != 0) $fwrite(fp, "unflw "); + if(w == 64'hFFF0000000000000) $fwrite(fp, "w=-inf "); + if(w == 64'h7FF0000000000000) $fwrite(fp, "w=+inf "); + if(w > 64'h7FF0000000000000 && w < 64'h7FF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w > 64'hFFF8000000000000 && w < 64'hFFF8000000000000 ) $fwrite(fp, "w=sigNaN "); + if(w >= 64'h7FF8000000000000 && w <= 64'h7FFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(w >= 64'hFFF8000000000000 && w <= 64'hFFFfffffffffffff ) $fwrite(fp, "w=qutNaN "); + if(ans == 64'hFFF0000000000000) $fwrite(fp, "ans=-inf "); + if(ans == 64'h7FF0000000000000) $fwrite(fp, "ans=+inf "); + if(ans > 64'h7FF0000000000000 && ans < 64'h7FF8000000000000 ) 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ns/10 ps +module tb; + + + reg [63:0] xrf; + reg [63:0] y; + reg [63:0] zrf; + reg [63:0] ans; + reg rn; + reg rz; + reg rm; + reg rp; + reg [63:0] earlyres; + reg earlyressel; + reg [1:0] bypsel; + reg bypplus1; + reg byppostnorm; + wire [63:0] w; + wire [63:0] wbypass; + wire invalid; + wire overflow; + wire underflow; + wire inexact; + +integer fp; +reg nan; + +localparam period = 20; +fmac UUT(.xrf(xrf), .y(y), .zrf(zrf), .rn(rn), .rz(rz), .rp(rp), .rm(rm), + .earlyres(earlyres), .earlyressel(earlyressel), .bypsel(bypsel), .bypplus1(bypplus1), .byppostnorm(byppostnorm), + .w(w), .wbypass(wbypass), .invalid(invalid), .overflow(overflow), .underflow(underflow), .inexact(inexact)); + + +initial + begin + fp = $fopen("/home/kparry/code/FMAC/tbgen/results.dat","w"); diff --git a/wally-pipelined/src/fpu/FMA/tbgen/testMini b/wally-pipelined/src/fpu/FMA/tbgen/testMini new file mode 100644 index 000000000..c2cf277cc --- /dev/null +++ b/wally-pipelined/src/fpu/FMA/tbgen/testMini @@ -0,0 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+000FFFFFFFFFFFFF_871000000003FBFF_8000000000000000 +000FFFFFFFFFFFFF_C00FFFFFFFFFFFFF_802FFFFFFFFFFFFD +CF66989323B8CA6C_7FF0001FFFFFFFFF_7FF8001FFFFFFFFF +BF4000001FFFFFFE_C00FFFFFFFFFFFFE_3F6000001FFFFFFD +000FFFFFFFFFFFFF_4030000020000003_0050000020000002 +000FFFFFFFFFFFFF_C00FFFFFFFFFFFFE_802FFFFFFFFFFFFC +43CFFFFFC0000007_CCF3EAA6A1B6FA2E_D0D3EAA679E1ACEF +BF27000000000000_C010000000000000_3F47000000000000 +000FFFFFFFFFFFFF_C010000000001FFE_8030000000001FFD +000FFFFFFFFFFFFF_C010000000000000_802FFFFFFFFFFFFE +C27D3655B9D22134_3FB0200000002000_C23D70C26545FFE3 +3FE01FFFFFFFFFFE_C010000000000001_C0001FFFFFFFFFFF diff --git a/wally-pipelined/src/fpu/FMA/tbgen/test_gen.sh b/wally-pipelined/src/fpu/FMA/tbgen/test_gen.sh new file mode 100755 index 000000000..0a4918470 --- /dev/null +++ b/wally-pipelined/src/fpu/FMA/tbgen/test_gen.sh @@ -0,0 +1 @@ +testfloat_gen f64_mulAdd -n 6133248 -rnear_even -seed 113355 -level 1 >> testFloat \ No newline at end of file diff --git a/wally-pipelined/src/fpu/FMA/tbgen/tstFlMult.awk b/wally-pipelined/src/fpu/FMA/tbgen/tstFlMult.awk new file mode 100755 index 000000000..3675cab5a --- /dev/null +++ b/wally-pipelined/src/fpu/FMA/tbgen/tstFlMult.awk @@ -0,0 +1 @@ +awk 'BEGIN {FS = " "; OFS = "_"} {if ($3 == "0000000000000000") print $1, $2, $4;}' testFloat | head -n 1000 > testMini \ No newline at end of file From 38b8cc652c39ff396b66bed4e854d81c364171fe Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 24 Feb 2021 07:25:03 -0500 Subject: [PATCH 22/33] All tests passing with bus interface --- wally-pipelined/src/ebu/ahblite.sv | 9 ++++++--- wally-pipelined/src/ifu/ifu.sv | 17 ++++++++++++++--- wally-pipelined/src/uncore/imem.sv | 3 ++- wally-pipelined/src/wally/wallypipelinedhart.sv | 6 ++++-- wally-pipelined/src/wally/wallypipelinedsoc.sv | 1 + wally-pipelined/testbench/testbench-imperas.sv | 2 +- 6 files changed, 28 insertions(+), 10 deletions(-) diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv index 655714762..ef26a8004 100644 --- a/wally-pipelined/src/ebu/ahblite.sv +++ b/wally-pipelined/src/ebu/ahblite.sv @@ -39,7 +39,7 @@ module ahblite ( input logic [`XLEN-1:0] InstrPAdrF, // *** rename these to match block diagram input logic InstrReadF, // input logic ResolveBranchD, - output logic [31:0] InstrRData, + output logic [`XLEN-1:0] InstrRData, // Signals from Data Cache input logic [`XLEN-1:0] MemPAdrM, input logic MemReadM, MemWriteM, @@ -71,6 +71,7 @@ module ahblite ( logic [2:0] ISize; logic [`AHBW-1:0] HRDATAMasked, ReadDataM, ReadDataPreW; logic IReady, DReady; + logic CaptureDataM; // logic [3:0] HSIZED; // size delayed by one cycle for reads // logic [2:0] HADDRD; // address delayed for subword reads @@ -139,8 +140,10 @@ module ahblite ( // Route signals to Instruction and Data Caches // *** assumes AHBW = XLEN - assign InstrRData = HRDATAMasked[31:0]; -// assign ReadDataW = HRDATAMasked; + + // fix harris 2/24/21 to read all WLEN bits directly for instruction + assign InstrRData = HRDATA; + assign ReadDataM = HRDATAMasked; // changed from W to M dh 2/7/2021 assign CaptureDataM = (BusState == MEMREAD) && (NextBusState != MEMREAD); flopenr #(`XLEN) ReadDataPreWReg(clk, reset, CaptureDataM, ReadDataM, ReadDataPreW); // *** this may break when there is no instruction read after data read diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index 3ba28a059..3deb64255 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -31,7 +31,7 @@ module ifu ( input logic StallF, StallD, StallE, StallM, StallW, input logic FlushD, FlushE, FlushM, FlushW, // Fetch - input logic [31:0] InstrF, + input logic [`XLEN-1:0] InstrInF, output logic [`XLEN-1:0] PCF, output logic [`XLEN-1:0] InstrPAdrF, output logic InstrReadF, @@ -53,7 +53,9 @@ module ifu ( input logic IllegalBaseInstrFaultD, output logic IllegalIEUInstrFaultD, output logic InstrMisalignedFaultM, - output logic [`XLEN-1:0] InstrMisalignedAdrM + output logic [`XLEN-1:0] InstrMisalignedAdrM, + // bogus + input logic [15:0] rd2 ); logic [`XLEN-1:0] UnalignedPCNextF, PCNextF; @@ -62,7 +64,7 @@ module ifu ( logic IllegalCompInstrD; logic [`XLEN-1:0] PCPlusUpperF, PCPlus2or4F, PCD, PCW, PCLinkD, PCLinkE, PCLinkM; logic CompressedF; - logic [31:0] InstrRawD, InstrE, InstrW; + logic [31:0] InstrF, InstrRawD, InstrE, InstrW; logic [31:0] nop = 32'h00000013; // instruction for NOP // *** put memory interface on here, InstrF becomes output @@ -94,6 +96,15 @@ module ifu ( else PCPlus2or4F = {PCF[`XLEN-1:2], 2'b10}; else PCPlus2or4F = {PCPlusUpperF, PCF[1:0]}; // add 4 + // harris 2/23/21 Add code to fetch instruction split across two words + generate + if (`XLEN==32) begin + assign InstrF = PCF[1] ? {rd2[15:0], InstrInF[31:16]} : InstrInF; + end else begin + assign InstrF = PCF[2] ? (PCF[1] ? {rd2[15:0], InstrInF[63:48]} : InstrInF[63:32]) + : (PCF[1] ? InstrInF[47:16] : InstrInF[31:0]); + end + endgenerate // Decode stage pipeline register and logic flopenl #(32) InstrDReg(clk, reset, ~StallD, (FlushD ? nop : InstrF), nop, InstrRawD); diff --git a/wally-pipelined/src/uncore/imem.sv b/wally-pipelined/src/uncore/imem.sv index 274be7dbf..09a6c2ce8 100644 --- a/wally-pipelined/src/uncore/imem.sv +++ b/wally-pipelined/src/uncore/imem.sv @@ -28,6 +28,7 @@ module imem ( input logic [`XLEN-1:1] AdrF, output logic [31:0] InstrF, + output logic [15:0] rd2, // bogus, delete when real multicycle fetch works output logic InstrAccessFaultF); /* verilator lint_off UNDRIVEN */ @@ -35,7 +36,7 @@ module imem ( /* verilator lint_on UNDRIVEN */ logic [15:0] adrbits; logic [`XLEN-1:0] rd; - logic [15:0] rd2; +// logic [15:0] rd2; generate if (`XLEN==32) assign adrbits = AdrF[17:2]; diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 56c98d386..2819ec0a6 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -35,6 +35,7 @@ module wallypipelinedhart ( input logic InstrAccessFaultF, input logic DataAccessFaultM, // Bus Interface + input logic [15:0] rd2, // bogus, delete when real multicycle fetch works input logic [`AHBW-1:0] HRDATA, input logic HREADY, HRESP, output logic HCLK, HRESETn, @@ -90,11 +91,12 @@ module wallypipelinedhart ( logic [`XLEN-1:0] MemAdrM, MemPAdrM, WriteDataM; logic [`XLEN-1:0] ReadDataW; logic [`XLEN-1:0] InstrPAdrF; + logic [`XLEN-1:0] InstrRData; logic InstrReadF; logic DataStall, InstrStall; logic InstrAckD, MemAckW; - ifu ifu(.*); // instruction fetch unit: PC, branch prediction, instruction cache + ifu ifu(.InstrInF(InstrRData), .*); // instruction fetch unit: PC, branch prediction, instruction cache ieu ieu(.*); // inteber execution unit: integer register file, datapath and controller dmem dmem(.*); // data cache unit @@ -102,7 +104,7 @@ module wallypipelinedhart ( ahblite ebu( //.InstrReadF(1'b0), - .InstrRData(InstrF), // hook up InstrF later + //.InstrRData(InstrF), // hook up InstrF later .MemSizeM(Funct3M[1:0]), .UnsignedLoadM(Funct3M[2]), .*); diff --git a/wally-pipelined/src/wally/wallypipelinedsoc.sv b/wally-pipelined/src/wally/wallypipelinedsoc.sv index bdb621726..7b8883c57 100644 --- a/wally-pipelined/src/wally/wallypipelinedsoc.sv +++ b/wally-pipelined/src/wally/wallypipelinedsoc.sv @@ -67,6 +67,7 @@ module wallypipelinedsoc ( logic [2:0] HADDRD; logic [3:0] HSIZED; logic HWRITED; + logic [15:0] rd2; // bogus, delete when real multicycle fetch works // instantiate processor and memories wallypipelinedhart hart(.*); diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index 491301cd6..8ccad1caa 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -236,7 +236,7 @@ string tests32i[] = { initial if (`XLEN == 64) begin // RV64 tests = {tests64i}; - if (`C_SUPPORTED % 2 == 1) tests = {tests64ic, tests}; + if (`C_SUPPORTED % 2 == 1) tests = {tests, tests64ic}; else tests = {tests, tests64iNOc}; end else begin // RV32 tests = {tests32i}; From cfd45a46c3bb04d5454dc5ed9ed2bf5bdcf4f801 Mon Sep 17 00:00:00 2001 From: Teo Ene Date: Wed, 24 Feb 2021 20:07:07 -0600 Subject: [PATCH 23/33] Added provisional coremark files from work with Elizabeth --- .../config/coremark/wally-config.vh | 90 +++++++++ wally-pipelined/regression/wally-coremark.do | 20 +- .../testbench/testbench-coremark.sv | 187 ++++++++++++++++-- 3 files changed, 277 insertions(+), 20 deletions(-) create mode 100644 wally-pipelined/config/coremark/wally-config.vh diff --git a/wally-pipelined/config/coremark/wally-config.vh b/wally-pipelined/config/coremark/wally-config.vh new file mode 100644 index 000000000..11058a47f --- /dev/null +++ b/wally-pipelined/config/coremark/wally-config.vh @@ -0,0 +1,90 @@ +////////////////////////////////////////// +// wally-config.vh +// +// Written: David_Harris@hmc.edu 4 January 2021 +// Modified: +// +// Purpose: Specify which features are configured +// Macros to determine which modes are supported based on MISA +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +// RV32 or RV64: XLEN = 32 or 64 +`define XLEN 64 + +//`define MISA (32'h00000104) +`define MISA (32'h00000104 | 1<<5 | 1<<18 | 1 << 20 | 1 << 12) +`define A_SUPPORTED ((`MISA >> 0) % 2 == 1) +`define C_SUPPORTED ((`MISA >> 2) % 2 == 1) +`define D_SUPPORTED ((`MISA >> 3) % 2 == 1) +`define F_SUPPORTED ((`MISA >> 5) % 2 == 1) +`define M_SUPPORTED ((`MISA >> 12) % 2 == 1) +`define S_SUPPORTED ((`MISA >> 18) % 2 == 1) +`define U_SUPPORTED ((`MISA >> 20) % 2 == 1) +`define ZCSR_SUPPORTED 1 +`define ZCOUNTERS_SUPPORTED 1 +// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21 +//`define N_SUPPORTED ((MISA >> 13) % 2 == 1) +`define N_SUPPORTED 0 + +`define M_MODE (2'b11) +`define S_MODE (2'b01) +`define U_MODE (2'b00) + +// Microarchitectural Features +`define UARCH_PIPELINED 1 +`define UARCH_SUPERSCALR 0 +`define UARCH_SINGLECYCLE 0 +`define MEM_DCACHE 0 +`define MEM_DTIM 1 +`define MEM_ICACHE 0 +`define MEM_VIRTMEM 0 + +// Address space +//`define RESET_VECTOR 64'h0000000080000000 +`define RESET_VECTOR 64'h0000000000000000 + +// Bus Interface width +`define AHBW 64 + +// Peripheral Addresses +// Peripheral memory space extends from BASE to BASE+RANGE +// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits + +`define TIMBASE 32'h80000000 +`define TIMRANGE 32'h0007FFFF +`define CLINTBASE 32'h02000000 +`define CLINTRANGE 32'h0000FFFF +`define GPIOBASE 32'h10012000 +`define GPIORANGE 32'h000000FF +`define UARTBASE 32'h10000000 +`define UARTRANGE 32'h00000007 + +// Test modes + +// Tie GPIO outputs back to inputs +`define GPIO_LOOPBACK_TEST 0 + + +// Hardware configuration +`define UART_PRESCALE 1 + +/* verilator lint_off STMTDLY */ +/* verilator lint_off WIDTH */ +/* verilator lint_off ASSIGNDLY */ +/* verilator lint_off PINCONNECTEMPTY */ diff --git a/wally-pipelined/regression/wally-coremark.do b/wally-pipelined/regression/wally-coremark.do index e564990f9..44667d53d 100644 --- a/wally-pipelined/regression/wally-coremark.do +++ b/wally-pipelined/regression/wally-coremark.do @@ -7,11 +7,11 @@ # # Takes 1:10 to run RV64IC tests using gui -# Use this wally-pipelined.do file to run this example. +# Use this wally-coremark.do file to run this example. # Either bring up ModelSim and type the following at the "ModelSim>" prompt: -# do wally-pipelined.do +# do wally-coremark.do # or, to run from a shell, type the following at the shell prompt: -# vsim -do wally-pipelined.do -c +# vsim -do wally-coremark.do -c # (omit the "-c" to see the GUI while running from the shell) onbreak {resume} @@ -27,12 +27,9 @@ vlib work # "Extra checking for conflicts with always_comb done at vopt time" # because vsim will run vopt -# default to config/rv64ic, but allow this to be overridden at the command line. For example: -# do wally-pipelined.do ../config/rv32ic -switch $argc { - 0 {vlog +incdir+../config/rv64ic ../testbench/testbench-coremark.sv ../src/*/*.sv -suppress 2583} - 1 {vlog +incdir+$1 ../testbench/testbench-coremark.sv ../src/*/*.sv -suppress 2583} -} +# default to config/coremark, but allow this to be overridden at the command line. For example: +vlog +incdir+../config/coremark ../testbench/testbench-coremark.sv ../src/*/*.sv -suppress 2583 + # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals vopt +acc work.testbench -o workopt @@ -58,11 +55,14 @@ add wave /testbench/dut/hart/FlushW add wave -divider add wave -hex /testbench/dut/hart/ifu/PCF add wave -hex /testbench/dut/hart/ifu/InstrF +add wave /testbench/InstrFName #add wave -hex /testbench/dut/hart/ifu/PCD add wave -hex /testbench/dut/hart/ifu/InstrD +add wave /testbench/InstrDName add wave -divider #add wave -hex /testbench/dut/hart/ifu/PCE #add wave -hex /testbench/dut/hart/ifu/InstrE +add wave /testbench/InstrEName add wave -hex /testbench/dut/hart/ieu/dp/SrcAE add wave -hex /testbench/dut/hart/ieu/dp/SrcBE add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE @@ -70,11 +70,13 @@ add wave /testbench/dut/hart/ieu/dp/PCSrcE add wave -divider #add wave -hex /testbench/dut/hart/ifu/PCM #add wave -hex /testbench/dut/hart/ifu/InstrM +add wave /testbench/InstrMName add wave /testbench/dut/uncore/dtim/memwrite add wave -hex /testbench/dut/uncore/HADDR add wave -hex /testbench/dut/uncore/HWDATA add wave -divider add wave -hex /testbench/dut/hart/ifu/PCW +add wave /testbench/InstrWName add wave /testbench/dut/hart/ieu/dp/RegWriteW add wave -hex /testbench/dut/hart/ieu/dp/ResultW add wave -hex /testbench/dut/hart/ieu/dp/RdW diff --git a/wally-pipelined/testbench/testbench-coremark.sv b/wally-pipelined/testbench/testbench-coremark.sv index fe2dbf239..4aef5e408 100644 --- a/wally-pipelined/testbench/testbench-coremark.sv +++ b/wally-pipelined/testbench/testbench-coremark.sv @@ -1,11 +1,40 @@ +/////////////////////////////////////////// +// testbench-imperas.sv +// +// Written: David_Harris@hmc.edu 9 January 2021 +// Modified: +// +// Purpose: Wally Testbench and helper modules +// Applies test programs from the Imperas suite +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// `include "wally-config.vh" - module testbench(); logic clk; logic reset; - - string memfilename; - + int test, i, errors, totalerrors; + logic [31:0] sig32[0:10000]; + logic [`XLEN-1:0] signature[0:10000]; + logic [`XLEN-1:0] testadr; + string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; + logic [31:0] InstrW; + logic [`XLEN-1:0] meminit; + string tests[]; logic [`AHBW-1:0] HRDATAEXT; logic HREADYEXT, HRESPEXT; logic [31:0] HADDR; @@ -17,31 +46,167 @@ module testbench(); logic [1:0] HTRANS; logic HMASTLOCK; logic HCLK, HRESETn; - + + // pick tests based on modes supported + initial + tests = {"../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.memfile", "1000"}; + string signame, memfilename; logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; logic UARTSin, UARTSout; - // instantiate device to be tested assign GPIOPinsIn = 0; assign UARTSin = 1; assign HREADYEXT = 1; assign HRESPEXT = 0; assign HRDATAEXT = 0; - - wallypipelinedsoc dut(.*); - + wallypipelinedsoc dut(.*); + // Track names of instructions + instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE, + dut.hart.ifu.InstrD, dut.hart.ifu.InstrE, + dut.hart.ifu.InstrM, InstrW, + InstrDName, InstrEName, InstrMName, InstrWName); // initialize tests initial begin - memfilename = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.memfile"; + totalerrors = 0; + // read test vectors into memory + memfilename = tests[0]; $readmemh(memfilename, dut.imem.RAM); $readmemh(memfilename, dut.uncore.dtim.RAM); reset = 1; # 22; reset = 0; end - // generate clock to sequence tests always begin clk = 1; # 5; clk = 0; # 5; end + +endmodule +/* verilator lint_on STMTDLY */ +/* verilator lint_on WIDTH */ +module instrTrackerTB( + input logic clk, reset, FlushE, + input logic [31:0] InstrD, + input logic [31:0] InstrE, InstrM, + output logic [31:0] InstrW, + output string InstrDName, InstrEName, InstrMName, InstrWName); + + // stage Instr to Writeback for visualization + flopr #(32) InstrWReg(clk, reset, InstrM, InstrW); + instrNameDecTB ddec(InstrD, InstrDName); + instrNameDecTB edec(InstrE, InstrEName); + instrNameDecTB mdec(InstrM, InstrMName); + instrNameDecTB wdec(InstrW, InstrWName); +endmodule +// decode the instruction name, to help the test bench +module instrNameDecTB( + input logic [31:0] instr, + output string name); + logic [6:0] op; + logic [2:0] funct3; + logic [6:0] funct7; + logic [11:0] imm; + assign op = instr[6:0]; + assign funct3 = instr[14:12]; + assign funct7 = instr[31:25]; + assign imm = instr[31:20]; + // it would be nice to add the operands to the name + // create another variable called decoded + always_comb + casez({op, funct3}) + 10'b0000000_000: name = "BAD"; + 10'b0000011_000: name = "LB"; + 10'b0000011_001: name = "LH"; + 10'b0000011_010: name = "LW"; + 10'b0000011_011: name = "LD"; + 10'b0000011_100: name = "LBU"; + 10'b0000011_101: name = "LHU"; + 10'b0000011_110: name = "LWU"; + 10'b0010011_000: if (instr[31:15] == 0 && instr[11:7] ==0) name = "NOP/FLUSH"; + else name = "ADDI"; + 10'b0010011_001: if (funct7[6:1] == 6'b000000) name = "SLLI"; + else name = "ILLEGAL"; + 10'b0010011_010: name = "SLTI"; + 10'b0010011_011: name = "SLTIU"; + 10'b0010011_100: name = "XORI"; + 10'b0010011_101: if (funct7[6:1] == 6'b000000) name = "SRLI"; + else if (funct7[6:1] == 6'b010000) name = "SRAI"; + else name = "ILLEGAL"; + 10'b0010011_110: name = "ORI"; + 10'b0010011_111: name = "ANDI"; + 10'b0010111_???: name = "AUIPC"; + 10'b0100011_000: name = "SB"; + 10'b0100011_001: name = "SH"; + 10'b0100011_010: name = "SW"; + 10'b0100011_011: name = "SD"; + 10'b0011011_000: name = "ADDIW"; + 10'b0011011_001: name = "SLLIW"; + 10'b0011011_101: if (funct7 == 7'b0000000) name = "SRLIW"; + else if (funct7 == 7'b0100000) name = "SRAIW"; + else name = "ILLEGAL"; + 10'b0111011_000: if (funct7 == 7'b0000000) name = "ADDW"; + else if (funct7 == 7'b0100000) name = "SUBW"; + else if (funct7 == 7'b0000001) name = "MULW"; + else name = "ILLEGAL"; + 10'b0111011_001: if (funct7 == 7'b0000000) name = "SLLW"; + else if (funct7 == 7'b0000001) name = "DIVW"; + else name = "ILLEGAL"; + 10'b0111011_101: if (funct7 == 7'b0000000) name = "SRLW"; + else if (funct7 == 7'b0100000) name = "SRAW"; + else if (funct7 == 7'b0000001) name = "DIVUW"; + else name = "ILLEGAL"; + 10'b0111011_110: if (funct7 == 7'b0000001) name = "REMW"; + else name = "ILLEGAL"; + 10'b0111011_111: if (funct7 == 7'b0000001) name = "REMUW"; + else name = "ILLEGAL"; + 10'b0110011_000: if (funct7 == 7'b0000000) name = "ADD"; + else if (funct7 == 7'b0000001) name = "MUL"; + else if (funct7 == 7'b0100000) name = "SUB"; + else name = "ILLEGAL"; + 10'b0110011_001: if (funct7 == 7'b0000000) name = "SLL"; + else if (funct7 == 7'b0000001) name = "MULH"; + else name = "ILLEGAL"; + 10'b0110011_010: if (funct7 == 7'b0000000) name = "SLT"; + else if (funct7 == 7'b0000001) name = "MULHSU"; + else name = "ILLEGAL"; + 10'b0110011_011: if (funct7 == 7'b0000000) name = "SLTU"; + else if (funct7 == 7'b0000001) name = "MULHU"; + else name = "ILLEGAL"; + 10'b0110011_100: if (funct7 == 7'b0000000) name = "XOR"; + else if (funct7 == 7'b0000001) name = "DIV"; + else name = "ILLEGAL"; + 10'b0110011_101: if (funct7 == 7'b0000000) name = "SRL"; + else if (funct7 == 7'b0000001) name = "DIVU"; + else if (funct7 == 7'b0100000) name = "SRA"; + else name = "ILLEGAL"; + 10'b0110011_110: if (funct7 == 7'b0000000) name = "OR"; + else if (funct7 == 7'b0000001) name = "REM"; + else name = "ILLEGAL"; + 10'b0110011_111: if (funct7 == 7'b0000000) name = "AND"; + else if (funct7 == 7'b0000001) name = "REMU"; + else name = "ILLEGAL"; + 10'b0110111_???: name = "LUI"; + 10'b1100011_000: name = "BEQ"; + 10'b1100011_001: name = "BNE"; + 10'b1100011_100: name = "BLT"; + 10'b1100011_101: name = "BGE"; + 10'b1100011_110: name = "BLTU"; + 10'b1100011_111: name = "BGEU"; + 10'b1100111_000: name = "JALR"; + 10'b1101111_???: name = "JAL"; + 10'b1110011_000: if (imm == 0) name = "ECALL"; + else if (imm == 1) name = "EBREAK"; + else if (imm == 2) name = "URET"; + else if (imm == 258) name = "SRET"; + else if (imm == 770) name = "MRET"; + else name = "ILLEGAL"; + 10'b1110011_001: name = "CSRRW"; + 10'b1110011_010: name = "CSRRS"; + 10'b1110011_011: name = "CSRRC"; + 10'b1110011_101: name = "CSRRWI"; + 10'b1110011_110: name = "CSRRSI"; + 10'b1110011_111: name = "CSRRCI"; + 10'b0001111_???: name = "FENCE"; + default: name = "ILLEGAL"; + endcase endmodule From 8491deb1a98422f46b918351fb78b2e72119707f Mon Sep 17 00:00:00 2001 From: Teo Ene Date: Thu, 25 Feb 2021 09:58:54 -0600 Subject: [PATCH 25/33] Changed .do file back to run all --- wally-pipelined/regression/wally-coremark.do | 2 +- wally-pipelined/regression/wally-pipelined.do | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/wally-pipelined/regression/wally-coremark.do b/wally-pipelined/regression/wally-coremark.do index 44667d53d..d56122384 100644 --- a/wally-pipelined/regression/wally-coremark.do +++ b/wally-pipelined/regression/wally-coremark.do @@ -42,7 +42,7 @@ view wave add wave /testbench/clk add wave /testbench/reset add wave -divider -add wave /testbench/dut/hart/ebu/IReadF +#add wave /testbench/dut/hart/ebu/IReadF add wave /testbench/dut/hart/DataStall add wave /testbench/dut/hart/InstrStall add wave /testbench/dut/hart/StallF diff --git a/wally-pipelined/regression/wally-pipelined.do b/wally-pipelined/regression/wally-pipelined.do index 227ea3770..b8e72968b 100644 --- a/wally-pipelined/regression/wally-pipelined.do +++ b/wally-pipelined/regression/wally-pipelined.do @@ -105,6 +105,6 @@ configure wave -childrowmargin 2 set DefaultRadix hexadecimal -- Run the Simulation -run 2000 -#run -all +#run 2000 +run -all #quit From b9701293a0b7f0ebd9ccb946cada7a16b6ac6742 Mon Sep 17 00:00:00 2001 From: Teo Ene Date: Thu, 25 Feb 2021 11:03:41 -0600 Subject: [PATCH 26/33] Changed TIMBASE in coremark config file --- wally-pipelined/config/coremark/wally-config.vh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/config/coremark/wally-config.vh b/wally-pipelined/config/coremark/wally-config.vh index 11058a47f..906373f90 100644 --- a/wally-pipelined/config/coremark/wally-config.vh +++ b/wally-pipelined/config/coremark/wally-config.vh @@ -66,7 +66,7 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define TIMBASE 32'h80000000 +`define TIMBASE 32'h00000000 `define TIMRANGE 32'h0007FFFF `define CLINTBASE 32'h02000000 `define CLINTRANGE 32'h0000FFFF From 5fee65231e13f7b7fe3561980c32542b835bf0ac Mon Sep 17 00:00:00 2001 From: Teo Ene Date: Thu, 25 Feb 2021 11:23:01 -0600 Subject: [PATCH 27/33] Edited imem to account for TIMBASE==0; still hard-coded and needs to be improved, but works with coremark config now. --- wally-pipelined/src/uncore/imem.sv | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/wally-pipelined/src/uncore/imem.sv b/wally-pipelined/src/uncore/imem.sv index 09a6c2ce8..1d8146cd3 100644 --- a/wally-pipelined/src/uncore/imem.sv +++ b/wally-pipelined/src/uncore/imem.sv @@ -57,7 +57,11 @@ module imem ( end else begin assign InstrF = AdrF[2] ? (AdrF[1] ? {rd2[15:0], rd[63:48]} : rd[63:32]) : (AdrF[1] ? rd[47:16] : rd[31:0]); - assign InstrAccessFaultF = (|AdrF[`XLEN-1:32]) | ~AdrF[31] | (|AdrF[30:16]); // memory mapped to 0x80000000-0x8000FFFF] + if(`TIMBASE==0) begin + assign InstrAccessFaultF = 0; + end else begin + assign InstrAccessFaultF = (|AdrF[`XLEN-1:32]) | ~AdrF[31] | (|AdrF[30:16]); // memory mapped to 0x80000000-0x8000FFFF] + end end endgenerate endmodule From a35fdac75b56cbe4cfcb3ed7b96eeb640628daef Mon Sep 17 00:00:00 2001 From: Teo Ene Date: Thu, 25 Feb 2021 11:24:44 -0600 Subject: [PATCH 28/33] Fixed previous commit --- wally-pipelined/src/uncore/imem.sv | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/wally-pipelined/src/uncore/imem.sv b/wally-pipelined/src/uncore/imem.sv index 1d8146cd3..86d235564 100644 --- a/wally-pipelined/src/uncore/imem.sv +++ b/wally-pipelined/src/uncore/imem.sv @@ -53,7 +53,11 @@ module imem ( generate if (`XLEN==32) begin assign InstrF = AdrF[1] ? {rd2[15:0], rd[31:16]} : rd; - assign InstrAccessFaultF = ~AdrF[31] | (|AdrF[30:16]); // memory mapped to 0x80000000-0x8000FFFF + if(`TIMBASE==0) begin + assign InstrAccessFaultF = 0; + end else begin + assign InstrAccessFaultF = ~AdrF[31] | (|AdrF[30:16]); // memory mapped to 0x80000000-0x8000FFFF + end end else begin assign InstrF = AdrF[2] ? (AdrF[1] ? {rd2[15:0], rd[63:48]} : rd[63:32]) : (AdrF[1] ? rd[47:16] : rd[31:0]); From b0a5052bcfb146d8dc9fccab005b122f66d3228b Mon Sep 17 00:00:00 2001 From: Brett Mathis Date: Thu, 25 Feb 2021 14:32:36 -0600 Subject: [PATCH 29/33] FPU Assembly tests --- wally-pipelined/src/fpu/fcsr.sv | 29 ++ wally-pipelined/src/fpu/fctrl.sv | 143 +++++++++ wally-pipelined/src/fpu/fputop.sv | 59 ++++ wally-pipelined/src/fpu/freg.sv | 513 ++++++++++++++++++++++++++++++ 4 files changed, 744 insertions(+) create mode 100644 wally-pipelined/src/fpu/fcsr.sv create mode 100644 wally-pipelined/src/fpu/fctrl.sv create mode 100644 wally-pipelined/src/fpu/fputop.sv create mode 100644 wally-pipelined/src/fpu/freg.sv diff --git a/wally-pipelined/src/fpu/fcsr.sv b/wally-pipelined/src/fpu/fcsr.sv new file mode 100644 index 000000000..64f3f7b92 --- /dev/null +++ b/wally-pipelined/src/fpu/fcsr.sv @@ -0,0 +1,29 @@ +`include "../../config/rv64icfd/wally-config.vh" + +module fcsr( + input logic [2:0] frm, + input logic reset, + input logic clear, + input logic clk, + input logic write, + input logic [4:0] flags, + output logic [31:0] readData); + + //register I/O assignment + logic [31:0] regInput; + logic [31:0] regOutput; + + //no L instruction support + //only last 8 bits used for FCSR + + //latching input to write signal + //AND clk and write and remove latch + //for clk-based write + assign regInput = (write) ? {24'h0,frm,flags} : regInput; + + floprc #(32) (.clk(clk), .reset(reset), .clear(clear), .d(regInput), .q(regOutput)); + + assign readData = regOutput; + + +endmodule diff --git a/wally-pipelined/src/fpu/fctrl.sv b/wally-pipelined/src/fpu/fctrl.sv new file mode 100644 index 000000000..13451165d --- /dev/null +++ b/wally-pipelined/src/fpu/fctrl.sv @@ -0,0 +1,143 @@ +`include "../../config/rv64icfd/wally-config.vh" + +module fctrl ( + input logic [6:0] Funct7D, + input logic [6:0] OpD, + input logic [4:0] Rs2D, + input logic [4:0] Rs1D, + input logic [2:0] FrmW, + output logic WriteEnD, + output logic DivSqrtStartD, + output logic [2:0] regSelD, + output logic [2:0] writeSelD, + output logic [3:0] OpCtrlD, + output logic FmtD, + output logic WriteIntD); + + + + //precision is taken directly from instruction + assign FmtD = Funct7D[0]; + + //all subsequent logic is based on the table present + //in Section 5 of Wally Architecture Specification + + //write is enabled for all fp instruciton op codes + //sans fp load + logic isFP, isFPLD; + always_comb begin + //case statement is easier to modify + //in case of errors + case(OpD) + //fp instructions sans load + 7'b1010011 : begin isFP = 1'b1; isFPLD = 1'b0; end + 7'b1000011 : begin isFP = 1'b1; isFPLD = 1'b0; end + 7'b1000111 : begin isFP = 1'b1; isFPLD = 1'b0; end + 7'b1001011 : begin isFP = 1'b1; isFPLD = 1'b0; end + 7'b1001111 : begin isFP = 1'b1; isFPLD = 1'b0; end + 7'b0100111 : begin isFP = 1'b1; isFPLD = 1'b0; end + //fp load + 7'b1010011 : begin isFP = 1'b1; isFPLD = 1'b1; end + default : begin isFP = 1'b0; isFPLD = 1'b0; end + endcase + end + + assign WriteEnD = isFP & ~isFPLD; + + //useful intermediary signals + // + //(mult only not supported in current datapath) + //set third FMA operand to zero in this case + //(or equivalent) + logic isAddSub, isFMA, isMult, isDivSqrt, isCvt, isCmp, isFPSTR; + + always_comb begin + //checks all but FMA/store/load + if(OpD == 7'b1010011) begin + case(Funct7D) + //compare + 7'b10100?? : begin isAddSub = 1'b0; isFMA = 1'b0; isMult = 1'b0; isDivSqrt = 1'b0; isCvt = 1'b0; isCmp = 1'b1; isFPSTR = 1'b0; end + //div/sqrt + 7'b0?011?? : begin isAddSub = 1'b0; isFMA = 1'b0; isMult = 1'b0; isDivSqrt = 1'b1; isCvt = 1'b0; isCmp = 1'b0; isFPSTR = 1'b0; end + //add/sub + 7'b0000??? : begin isAddSub = 1'b1; isFMA = 1'b0; isMult = 1'b0; isDivSqrt = 1'b0; isCvt = 1'b0; isCmp = 1'b0; isFPSTR = 1'b0; end + //mult + 7'b00010?? : begin isAddSub = 1'b0; isFMA = 1'b0; isMult = 1'b1; isDivSqrt = 1'b0; isCvt = 1'b0; isCmp = 1'b0; isFPSTR = 1'b0; end + //convert (not precision) + 7'b110?0?? : begin isAddSub = 1'b0; isFMA = 1'b0; isMult = 1'b0; isDivSqrt = 1'b0; isCvt = 1'b1; isCmp = 1'b0; isFPSTR = 1'b0; end + //convert (precision) + 7'b010000? : begin isAddSub = 1'b0; isFMA = 1'b0; isMult = 1'b0; isDivSqrt = 1'b0; isCvt = 1'b1; isCmp = 1'b0; isFPSTR = 1'b0; end + endcase + end + //FMA/store/load + else begin + case(OpD) + //4 FMA instructions + 7'b1000011 : begin isAddSub = 1'b0; isFMA = 1'b1; isMult = 1'b0; isDivSqrt = 1'b0; isCvt = 1'b0; isCmp = 1'b0; isFPSTR = 1'b0; end + 7'b1000111 : begin isAddSub = 1'b0; isFMA = 1'b1; isMult = 1'b0; isDivSqrt = 1'b0; isCvt = 1'b0; isCmp = 1'b0; isFPSTR = 1'b0; end + 7'b1001011 : begin isAddSub = 1'b0; isFMA = 1'b1; isMult = 1'b0; isDivSqrt = 1'b0; isCvt = 1'b0; isCmp = 1'b0; isFPSTR = 1'b0; end + 7'b1001111 : begin isAddSub = 1'b0; isFMA = 1'b1; isMult = 1'b0; isDivSqrt = 1'b0; isCvt = 1'b0; isCmp = 1'b0; isFPSTR = 1'b0; end + //store (load already found) + 7'b0100111 : begin isAddSub = 1'b0; isFMA = 1'b0; isMult = 1'b0; isDivSqrt = 1'b0; isCvt = 1'b0; isCmp = 1'b0; isFPSTR = 1'b1; end + endcase + end + end + + //register is chosen based on operation performed + //---- + //write selection is chosen in the same way as + //register selection + // + + // reg/write sel logic and assignment + // + // 3'b000 = add/sub/cvt + // 3'b001 = sign + // 3'b010 = fma + // 3'b011 = cmp + // 3'b100 = div/sqrt + // + //reg select + + //this value is used enough to be shorthand + logic isSign; + assign isSign = ~Funct7D[6] & ~Funct7D[5] & Funct7D[4] & ~Funct7D[3] & ~Funct7D[2]; + + + assign regSelD[2] = isDivSqrt & ~isFMA; + assign regSelD[1] = isFMA | isCmp; + //AND of Funct7 for sign + assign regSelD[0] = isCmp | isSign; + + //write select + assign writeSelD[2] = isDivSqrt & ~isFMA; + assign writeSelD[1] = isFMA | isCmp; + //AND of Funct7 for sign + assign writeSelD[0] = isCmp | isSign; + + //if op is div/sqrt - start div/sqrt + assign DivSqrtStartD = isDivSqrt & ~isFMA; + + //operation control for each fp operation + //has to be expanded over standard to account for + //integrated fpadd/cvt + // + //will integrate FMA opcodes into design later + // + //conversion instructions will + //also need to be added later as I find the opcode + //version I used for this repo + + assign OpCtrlD[3] = 1'b0; + //if is positive sign injection OR is precision convert + assign OpCtrlD[2] = (isSign & ~FrmW[0]) | (~Funct7D[6] & Funct7D[5] & ~Funct7D[4] & ~Funct7D[3] & ~Funct7D[2] & ~Funct7D[1]); + //if is precision convert OR is sign xor + assign OpCtrlD[1] = (isSign & FrmW[1]) | (~Funct7D[6] & Funct7D[5] & ~Funct7D[4] & ~Funct7D[3] & ~Funct7D[2] & ~Funct7D[1]); + //if is sqrt OR is sub OR is single-precision cmp OR negation + assign OpCtrlD[0] = (isDivSqrt & ~isFMA & Funct7D[6]) | (isAddSub & ~isFMA & Funct7D[2]) | (isCmp & ~isFMA & Funct7D[0]) | (isSign & FrmW[0]); + + //write to integer source if conv to int occurs + //AND of Funct7 for int results + assign WriteIntD = isCvt & (Funct7D[6] & Funct7D[5] & ~Funct7D[4] & ~Funct7D[3] & ~Funct7D[2] & ~Funct7D[1]); + +endmodule diff --git a/wally-pipelined/src/fpu/fputop.sv b/wally-pipelined/src/fpu/fputop.sv new file mode 100644 index 000000000..3267ac9fa --- /dev/null +++ b/wally-pipelined/src/fpu/fputop.sv @@ -0,0 +1,59 @@ +`include "../../config/rv64icfd/wally-config.vh" + +module fputop ( + input logic [2:0] FrmW, + input logic reset, + input logic clear, + input logic clk, + input logic [31:0] InstrD, + input logic [`XLEN-1:0] SrcAE, + input logic [`XLEN-1:0] SrcAW, + output logic [31:0] FSROutW, + output logic DivSqrtDoneE, + output logic FInvalInstrD, + output logic [`XLEN-1:0] FPUResultW); + + /*fctrl (); + + //regfile instantiation and decode stage + //freg1adr (); + + //freg2adr (); + + //freg2adr (); + + //freg2adr (); + + freg3adr (); + + //can easily be merged into privledged core + //if necessary + //fcsr (); + + //E pipe and execution stage + + fpdivsqrt (); + + fma1 (); + + fpaddcvt1 (); + + fpcmp1 (); + + fpsign (); + + //M pipe and memory stage + + fma2 (); + + fpaddcvt2 (); + + fpcmp2 (); + + //W pipe and writeback stage + + //flag signal mux + + //result mux +*/ +endmodule diff --git a/wally-pipelined/src/fpu/freg.sv b/wally-pipelined/src/fpu/freg.sv new file mode 100644 index 000000000..6da116d5f --- /dev/null +++ b/wally-pipelined/src/fpu/freg.sv @@ -0,0 +1,513 @@ +`include "../../config/rv64icfd/wally-config.vh" + +module freg1adr ( + input logic [2:0] frm, + input logic reset, + input logic clear, + input logic clk, + input logic [4:0] rd, + input logic write, + input logic [4:0] adr1, + input logic [`XLEN-1:0] writeData, + output logic [`XLEN-1:0] readData); + + //note - not word aligning based on precision of + //operation (frm) + + //reg number should remain static, but it doesn't hurt + //to parameterize + parameter numRegs = 32; + + //intermediary signals - useful for debugging + //and easy instatiation of generated modules + logic [`XLEN-1:0] [numRegs-1:0] regInput; + logic [`XLEN-1:0] [numRegs-1:0] regOutput; + + //generate fp registers themselves + genvar i; + generate + for (i = 0; i < numRegs; i = i + 1) begin:register + + floprc #(`XLEN) (.clk(clk), .reset(reset), .clear(clear), .d(regInput[i][`XLEN-1:0]), .q(regOutput[i][`XLEN-1:0])); + end + + endgenerate + + //this could be done with: + // + //assign readData = regOutput[adr1]; + // + //but always_comb allows for finer control + + + //address decoder + //only 1 for this fp register set + //used with fpsign + //defaults to outputting zeroes + always_comb begin + case(adr1) + 5'b00000 : readData = regOutput[0]; + 5'b00001 : readData = regOutput[1]; + 5'b00010 : readData = regOutput[2]; + 5'b00011 : readData = regOutput[3]; + 5'b00100 : readData = regOutput[4]; + 5'b00101 : readData = regOutput[5]; + 5'b00110 : readData = regOutput[6]; + 5'b00111 : readData = regOutput[7]; + 5'b01000 : readData = regOutput[8]; + 5'b01001 : readData = regOutput[9]; + 5'b01010 : readData = regOutput[10]; + 5'b01011 : readData = regOutput[11]; + 5'b01100 : readData = regOutput[12]; + 5'b01101 : readData = regOutput[13]; + 5'b01110 : readData = regOutput[14]; + 5'b01111 : readData = regOutput[15]; + 5'b10000 : readData = regOutput[16]; + 5'b10001 : readData = regOutput[17]; + 5'b10010 : readData = regOutput[18]; + 5'b10011 : readData = regOutput[19]; + 5'b10100 : readData = regOutput[20]; + 5'b10101 : readData = regOutput[21]; + 5'b10110 : readData = regOutput[22]; + 5'b10111 : readData = regOutput[23]; + 5'b11000 : readData = regOutput[24]; + 5'b11001 : readData = regOutput[25]; + 5'b11010 : readData = regOutput[26]; + 5'b11011 : readData = regOutput[27]; + 5'b11100 : readData = regOutput[28]; + 5'b11101 : readData = regOutput[29]; + 5'b11110 : readData = regOutput[30]; + 5'b11111 : readData = regOutput[31]; + default : readData = `XLEN'h0; + endcase + end + + //destination register decoder + //only change input values on write + //defaults to undefined with invalid address + // + //note - this is an intermediary signal, so + //this is not asynch assignment. FF in flopr + //will not update data until clk pulse + always_comb begin + if(write) begin + case(rd) + 5'b00000 : regInput[0] = writeData; + 5'b00001 : regInput[1] = writeData; + 5'b00010 : regInput[2] = writeData; + 5'b00011 : regInput[3] = writeData; + 5'b00100 : regInput[4] = writeData; + 5'b00101 : regInput[5] = writeData; + 5'b00110 : regInput[6] = writeData; + 5'b00111 : regInput[7] = writeData; + 5'b01000 : regInput[8] = writeData; + 5'b01000 : regInput[9] = writeData; + 5'b01001 : regInput[10] = writeData; + 5'b01010 : regInput[11] = writeData; + 5'b01111 : regInput[12] = writeData; + 5'b01101 : regInput[13] = writeData; + 5'b01110 : regInput[14] = writeData; + 5'b01111 : regInput[15] = writeData; + 5'b10000 : regInput[16] = writeData; + 5'b10001 : regInput[17] = writeData; + 5'b10010 : regInput[18] = writeData; + 5'b10011 : regInput[19] = writeData; + 5'b10100 : regInput[20] = writeData; + 5'b10101 : regInput[21] = writeData; + 5'b10110 : regInput[22] = writeData; + 5'b10111 : regInput[23] = writeData; + 5'b11000 : regInput[24] = writeData; + 5'b11000 : regInput[25] = writeData; + 5'b11001 : regInput[26] = writeData; + 5'b11010 : regInput[27] = writeData; + 5'b11111 : regInput[28] = writeData; + 5'b11101 : regInput[29] = writeData; + 5'b11110 : regInput[30] = writeData; + 5'b11111 : regInput[31] = writeData; + default : regInput[0] = `XLEN'hx; + endcase + end + end + +endmodule + +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +//******** +//formatting separation +//******** +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +module freg2adr ( + input logic [2:0] frm, + input logic reset, + input logic clear, + input logic clk, + input logic [4:0] rd, + input logic write, + input logic [4:0] adr1, + input logic [4:0] adr2, + input logic [`XLEN-1:0] writeData, + output logic [`XLEN-1:0] readData1, + output logic [`XLEN-1:0] readData2); + + //note - not word aligning based on precision of + //operation (frm) + + //reg number should remain static, but it doesn't hurt + //to parameterize + parameter numRegs = 32; + + //intermediary signals - useful for debugging + //and easy instatiation of generated modules + logic [`XLEN-1:0] [numRegs-1:0] regInput; + logic [`XLEN-1:0] [numRegs-1:0] regOutput; + + //generate fp registers themselves + genvar i; + generate + for (i = 0; i < numRegs; i = i + 1) begin:register + + floprc #(`XLEN) (.clk(clk), .reset(reset), .clear(clear), .d(regInput[i][`XLEN-1:0]), .q(regOutput[i][`XLEN-1:0])); + end + + endgenerate + + //address decoder + //2 are used for this fp register set + //used with fpadd/cvt, fpdiv/sqrt, and fpcmp + //defaults to outputting zeroes + always_comb begin + + //adderss 1 decoder + case(adr1) + 5'b00000 : readData1 = regOutput[0]; + 5'b00001 : readData1 = regOutput[1]; + 5'b00010 : readData1 = regOutput[2]; + 5'b00011 : readData1 = regOutput[3]; + 5'b00100 : readData1 = regOutput[4]; + 5'b00101 : readData1 = regOutput[5]; + 5'b00110 : readData1 = regOutput[6]; + 5'b00111 : readData1 = regOutput[7]; + 5'b01000 : readData1 = regOutput[8]; + 5'b01001 : readData1 = regOutput[9]; + 5'b01010 : readData1 = regOutput[10]; + 5'b01011 : readData1 = regOutput[11]; + 5'b01100 : readData1 = regOutput[12]; + 5'b01101 : readData1 = regOutput[13]; + 5'b01110 : readData1 = regOutput[14]; + 5'b01111 : readData1 = regOutput[15]; + 5'b10000 : readData1 = regOutput[16]; + 5'b10001 : readData1 = regOutput[17]; + 5'b10010 : readData1 = regOutput[18]; + 5'b10011 : readData1 = regOutput[19]; + 5'b10100 : readData1 = regOutput[20]; + 5'b10101 : readData1 = regOutput[21]; + 5'b10110 : readData1 = regOutput[22]; + 5'b10111 : readData1 = regOutput[23]; + 5'b11000 : readData1 = regOutput[24]; + 5'b11001 : readData1 = regOutput[25]; + 5'b11010 : readData1 = regOutput[26]; + 5'b11011 : readData1 = regOutput[27]; + 5'b11100 : readData1 = regOutput[28]; + 5'b11101 : readData1 = regOutput[29]; + 5'b11110 : readData1 = regOutput[30]; + 5'b11111 : readData1 = regOutput[31]; + default : readData1 = `XLEN'h0; + endcase + + //address 2 decoder + case(adr2) + 5'b00000 : readData2 = regOutput[0]; + 5'b00001 : readData2 = regOutput[1]; + 5'b00010 : readData2 = regOutput[2]; + 5'b00011 : readData2 = regOutput[3]; + 5'b00100 : readData2 = regOutput[4]; + 5'b00101 : readData2 = regOutput[5]; + 5'b00110 : readData2 = regOutput[6]; + 5'b00111 : readData2 = regOutput[7]; + 5'b01000 : readData2 = regOutput[8]; + 5'b01001 : readData2 = regOutput[9]; + 5'b01010 : readData2 = regOutput[10]; + 5'b01011 : readData2 = regOutput[11]; + 5'b01100 : readData2 = regOutput[12]; + 5'b01101 : readData2 = regOutput[13]; + 5'b01110 : readData2 = regOutput[14]; + 5'b01111 : readData2 = regOutput[15]; + 5'b10000 : readData2 = regOutput[16]; + 5'b10001 : readData2 = regOutput[17]; + 5'b10010 : readData2 = regOutput[18]; + 5'b10011 : readData2 = regOutput[19]; + 5'b10100 : readData2 = regOutput[20]; + 5'b10101 : readData2 = regOutput[21]; + 5'b10110 : readData2 = regOutput[22]; + 5'b10111 : readData2 = regOutput[23]; + 5'b11000 : readData2 = regOutput[24]; + 5'b11001 : readData2 = regOutput[25]; + 5'b11010 : readData2 = regOutput[26]; + 5'b11011 : readData2 = regOutput[27]; + 5'b11100 : readData2 = regOutput[28]; + 5'b11101 : readData2 = regOutput[29]; + 5'b11110 : readData2 = regOutput[30]; + 5'b11111 : readData2 = regOutput[31]; + default : readData2 = `XLEN'h0; + endcase + end + + //destination register decoder + //only change input values on write + //defaults to undefined with invalid address + // + //note - this is an intermediary signal, so + //this is not asynch assignment. FF in flopr + //will not update data until clk pulse + always_comb begin + if(write) begin + case(rd) + 5'b00000 : regInput[0] = writeData; + 5'b00001 : regInput[1] = writeData; + 5'b00010 : regInput[2] = writeData; + 5'b00011 : regInput[3] = writeData; + 5'b00100 : regInput[4] = writeData; + 5'b00101 : regInput[5] = writeData; + 5'b00110 : regInput[6] = writeData; + 5'b00111 : regInput[7] = writeData; + 5'b01000 : regInput[8] = writeData; + 5'b01000 : regInput[9] = writeData; + 5'b01001 : regInput[10] = writeData; + 5'b01010 : regInput[11] = writeData; + 5'b01111 : regInput[12] = writeData; + 5'b01101 : regInput[13] = writeData; + 5'b01110 : regInput[14] = writeData; + 5'b01111 : regInput[15] = writeData; + 5'b10000 : regInput[16] = writeData; + 5'b10001 : regInput[17] = writeData; + 5'b10010 : regInput[18] = writeData; + 5'b10011 : regInput[19] = writeData; + 5'b10100 : regInput[20] = writeData; + 5'b10101 : regInput[21] = writeData; + 5'b10110 : regInput[22] = writeData; + 5'b10111 : regInput[23] = writeData; + 5'b11000 : regInput[24] = writeData; + 5'b11000 : regInput[25] = writeData; + 5'b11001 : regInput[26] = writeData; + 5'b11010 : regInput[27] = writeData; + 5'b11111 : regInput[28] = writeData; + 5'b11101 : regInput[29] = writeData; + 5'b11110 : regInput[30] = writeData; + 5'b11111 : regInput[31] = writeData; + default : regInput[0] = `XLEN'hx; + endcase + end + end + +endmodule + +////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +//******** +//formatting separation +//******** +///////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +module freg3adr ( + input logic [2:0] frm, + input logic reset, + input logic clear, + input logic clk, + input logic [4:0] rd, + input logic write, + input logic [4:0] adr1, + input logic [4:0] adr2, + input logic [4:0] adr3, + input logic [`XLEN-1:0] writeData, + output logic [`XLEN-1:0] readData1, + output logic [`XLEN-1:0] readData2, + output logic [`XLEN-1:0] readData3); + + //note - not word aligning based on precision of + //operation (frm) + + //reg number should remain static, but it doesn't hurt + //to parameterize + parameter numRegs = 32; + + //intermediary signals - useful for debugging + //and easy instatiation of generated modules + logic [`XLEN-1:0] [numRegs-1:0] regInput; + logic [`XLEN-1:0] [numRegs-1:0] regOutput; + + //generate fp registers themselves + genvar i; + generate + for (i = 0; i < numRegs; i = i + 1) begin:register + + floprc #(`XLEN) (.clk(clk), .reset(reset), .clear(clear), .d(regInput[i][`XLEN-1:0]), .q(regOutput[i][`XLEN-1:0])); + end + + endgenerate + + //address decoder + //3 are used for this fp register set + //used exclusively for fma + //defaults to outputting zeroes + always_comb begin + + //adderss 1 decoder + case(adr1) + 5'b00000 : readData1 = regOutput[0]; + 5'b00001 : readData1 = regOutput[1]; + 5'b00010 : readData1 = regOutput[2]; + 5'b00011 : readData1 = regOutput[3]; + 5'b00100 : readData1 = regOutput[4]; + 5'b00101 : readData1 = regOutput[5]; + 5'b00110 : readData1 = regOutput[6]; + 5'b00111 : readData1 = regOutput[7]; + 5'b01000 : readData1 = regOutput[8]; + 5'b01001 : readData1 = regOutput[9]; + 5'b01010 : readData1 = regOutput[10]; + 5'b01011 : readData1 = regOutput[11]; + 5'b01100 : readData1 = regOutput[12]; + 5'b01101 : readData1 = regOutput[13]; + 5'b01110 : readData1 = regOutput[14]; + 5'b01111 : readData1 = regOutput[15]; + 5'b10000 : readData1 = regOutput[16]; + 5'b10001 : readData1 = regOutput[17]; + 5'b10010 : readData1 = regOutput[18]; + 5'b10011 : readData1 = regOutput[19]; + 5'b10100 : readData1 = regOutput[20]; + 5'b10101 : readData1 = regOutput[21]; + 5'b10110 : readData1 = regOutput[22]; + 5'b10111 : readData1 = regOutput[23]; + 5'b11000 : readData1 = regOutput[24]; + 5'b11001 : readData1 = regOutput[25]; + 5'b11010 : readData1 = regOutput[26]; + 5'b11011 : readData1 = regOutput[27]; + 5'b11100 : readData1 = regOutput[28]; + 5'b11101 : readData1 = regOutput[29]; + 5'b11110 : readData1 = regOutput[30]; + 5'b11111 : readData1 = regOutput[31]; + default : readData1 = `XLEN'h0; + endcase + + //address 2 decoder + case(adr2) + 5'b00000 : readData2 = regOutput[0]; + 5'b00001 : readData2 = regOutput[1]; + 5'b00010 : readData2 = regOutput[2]; + 5'b00011 : readData2 = regOutput[3]; + 5'b00100 : readData2 = regOutput[4]; + 5'b00101 : readData2 = regOutput[5]; + 5'b00110 : readData2 = regOutput[6]; + 5'b00111 : readData2 = regOutput[7]; + 5'b01000 : readData2 = regOutput[8]; + 5'b01001 : readData2 = regOutput[9]; + 5'b01010 : readData2 = regOutput[10]; + 5'b01011 : readData2 = regOutput[11]; + 5'b01100 : readData2 = regOutput[12]; + 5'b01101 : readData2 = regOutput[13]; + 5'b01110 : readData2 = regOutput[14]; + 5'b01111 : readData2 = regOutput[15]; + 5'b10000 : readData2 = regOutput[16]; + 5'b10001 : readData2 = regOutput[17]; + 5'b10010 : readData2 = regOutput[18]; + 5'b10011 : readData2 = regOutput[19]; + 5'b10100 : readData2 = regOutput[20]; + 5'b10101 : readData2 = regOutput[21]; + 5'b10110 : readData2 = regOutput[22]; + 5'b10111 : readData2 = regOutput[23]; + 5'b11000 : readData2 = regOutput[24]; + 5'b11001 : readData2 = regOutput[25]; + 5'b11010 : readData2 = regOutput[26]; + 5'b11011 : readData2 = regOutput[27]; + 5'b11100 : readData2 = regOutput[28]; + 5'b11101 : readData2 = regOutput[29]; + 5'b11110 : readData2 = regOutput[30]; + 5'b11111 : readData2 = regOutput[31]; + default : readData2 = `XLEN'h0; + endcase + + //address 3 decoder + case(adr3) + 5'b00000 : readData3 = regOutput[0]; + 5'b00001 : readData3 = regOutput[1]; + 5'b00010 : readData3 = regOutput[2]; + 5'b00011 : readData3 = regOutput[3]; + 5'b00100 : readData3 = regOutput[4]; + 5'b00101 : readData3 = regOutput[5]; + 5'b00110 : readData3 = regOutput[6]; + 5'b00111 : readData3 = regOutput[7]; + 5'b01000 : readData3 = regOutput[8]; + 5'b01001 : readData3 = regOutput[9]; + 5'b01010 : readData3 = regOutput[10]; + 5'b01011 : readData3 = regOutput[11]; + 5'b01100 : readData3 = regOutput[12]; + 5'b01101 : readData3 = regOutput[13]; + 5'b01110 : readData3 = regOutput[14]; + 5'b01111 : readData3 = regOutput[15]; + 5'b10000 : readData3 = regOutput[16]; + 5'b10001 : readData3 = regOutput[17]; + 5'b10010 : readData3 = regOutput[18]; + 5'b10011 : readData3 = regOutput[19]; + 5'b10100 : readData3 = regOutput[20]; + 5'b10101 : readData3 = regOutput[21]; + 5'b10110 : readData3 = regOutput[22]; + 5'b10111 : readData3 = regOutput[23]; + 5'b11000 : readData3 = regOutput[24]; + 5'b11001 : readData3 = regOutput[25]; + 5'b11010 : readData3 = regOutput[26]; + 5'b11011 : readData3 = regOutput[27]; + 5'b11100 : readData3 = regOutput[28]; + 5'b11101 : readData3 = regOutput[29]; + 5'b11110 : readData3 = regOutput[30]; + 5'b11111 : readData3 = regOutput[31]; + default : readData3 = `XLEN'h0; + endcase + end + + //destination register decoder + //only change input values on write + //defaults to undefined with invalid address + // + //note - this is an intermediary signal, so + //this is not asynch assignment. FF in flopr + //will not update data until clk pulse + always_comb begin + if(write) begin + case(rd) + 5'b00000 : regInput[0] = writeData; + 5'b00001 : regInput[1] = writeData; + 5'b00010 : regInput[2] = writeData; + 5'b00011 : regInput[3] = writeData; + 5'b00100 : regInput[4] = writeData; + 5'b00101 : regInput[5] = writeData; + 5'b00110 : regInput[6] = writeData; + 5'b00111 : regInput[7] = writeData; + 5'b01000 : regInput[8] = writeData; + 5'b01000 : regInput[9] = writeData; + 5'b01001 : regInput[10] = writeData; + 5'b01010 : regInput[11] = writeData; + 5'b01111 : regInput[12] = writeData; + 5'b01101 : regInput[13] = writeData; + 5'b01110 : regInput[14] = writeData; + 5'b01111 : regInput[15] = writeData; + 5'b10000 : regInput[16] = writeData; + 5'b10001 : regInput[17] = writeData; + 5'b10010 : regInput[18] = writeData; + 5'b10011 : regInput[19] = writeData; + 5'b10100 : regInput[20] = writeData; + 5'b10101 : regInput[21] = writeData; + 5'b10110 : regInput[22] = writeData; + 5'b10111 : regInput[23] = writeData; + 5'b11000 : regInput[24] = writeData; + 5'b11000 : regInput[25] = writeData; + 5'b11001 : regInput[26] = writeData; + 5'b11010 : regInput[27] = writeData; + 5'b11111 : regInput[28] = writeData; + 5'b11101 : regInput[29] = writeData; + 5'b11110 : regInput[30] = writeData; + 5'b11111 : regInput[31] = writeData; + default : regInput[0] = `XLEN'hx; + endcase + end + end + +endmodule From 1b61d78ac23ae2fe5bbb5ff9a17da4509776999c Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 26 Feb 2021 00:55:41 -0500 Subject: [PATCH 31/33] Retimed peripherals for AHB interface --- wally-pipelined/src/fpu/build_temp/freg.sv | 2 +- wally-pipelined/src/fpu/{ => dev}/fcsr.sv | 2 +- wally-pipelined/src/fpu/{ => dev}/fctrl.sv | 0 wally-pipelined/src/fpu/{ => dev}/fputop.sv | 0 wally-pipelined/src/fpu/{ => dev}/freg.sv | 6 ++--- wally-pipelined/src/uncore/clint.sv | 8 +++--- wally-pipelined/src/uncore/gpio.sv | 28 +++++++++++---------- wally-pipelined/src/uncore/uart.sv | 8 +++--- 8 files changed, 30 insertions(+), 24 deletions(-) rename wally-pipelined/src/fpu/{ => dev}/fcsr.sv (87%) rename wally-pipelined/src/fpu/{ => dev}/fctrl.sv (100%) rename wally-pipelined/src/fpu/{ => dev}/fputop.sv (100%) rename wally-pipelined/src/fpu/{ => dev}/freg.sv (97%) diff --git a/wally-pipelined/src/fpu/build_temp/freg.sv b/wally-pipelined/src/fpu/build_temp/freg.sv index 6da116d5f..282610869 100644 --- a/wally-pipelined/src/fpu/build_temp/freg.sv +++ b/wally-pipelined/src/fpu/build_temp/freg.sv @@ -340,7 +340,7 @@ module freg3adr ( generate for (i = 0; i < numRegs; i = i + 1) begin:register - floprc #(`XLEN) (.clk(clk), .reset(reset), .clear(clear), .d(regInput[i][`XLEN-1:0]), .q(regOutput[i][`XLEN-1:0])); + floprc #(`XLEN) reg[i](.clk(clk), .reset(reset), .clear(clear), .d(regInput[i][`XLEN-1:0]), .q(regOutput[i][`XLEN-1:0])); end endgenerate diff --git a/wally-pipelined/src/fpu/fcsr.sv b/wally-pipelined/src/fpu/dev/fcsr.sv similarity index 87% rename from wally-pipelined/src/fpu/fcsr.sv rename to wally-pipelined/src/fpu/dev/fcsr.sv index 64f3f7b92..825da56ca 100644 --- a/wally-pipelined/src/fpu/fcsr.sv +++ b/wally-pipelined/src/fpu/dev/fcsr.sv @@ -21,7 +21,7 @@ module fcsr( //for clk-based write assign regInput = (write) ? {24'h0,frm,flags} : regInput; - floprc #(32) (.clk(clk), .reset(reset), .clear(clear), .d(regInput), .q(regOutput)); + floprc #(32) fcsrreg(.clk(clk), .reset(reset), .clear(clear), .d(regInput), .q(regOutput)); assign readData = regOutput; diff --git a/wally-pipelined/src/fpu/fctrl.sv b/wally-pipelined/src/fpu/dev/fctrl.sv similarity index 100% rename from wally-pipelined/src/fpu/fctrl.sv rename to wally-pipelined/src/fpu/dev/fctrl.sv diff --git a/wally-pipelined/src/fpu/fputop.sv b/wally-pipelined/src/fpu/dev/fputop.sv similarity index 100% rename from wally-pipelined/src/fpu/fputop.sv rename to wally-pipelined/src/fpu/dev/fputop.sv diff --git a/wally-pipelined/src/fpu/freg.sv b/wally-pipelined/src/fpu/dev/freg.sv similarity index 97% rename from wally-pipelined/src/fpu/freg.sv rename to wally-pipelined/src/fpu/dev/freg.sv index 6da116d5f..24ca439cc 100644 --- a/wally-pipelined/src/fpu/freg.sv +++ b/wally-pipelined/src/fpu/dev/freg.sv @@ -28,7 +28,7 @@ module freg1adr ( generate for (i = 0; i < numRegs; i = i + 1) begin:register - floprc #(`XLEN) (.clk(clk), .reset(reset), .clear(clear), .d(regInput[i][`XLEN-1:0]), .q(regOutput[i][`XLEN-1:0])); + floprc #(`XLEN) freg[i](.clk(clk), .reset(reset), .clear(clear), .d(regInput[i][`XLEN-1:0]), .q(regOutput[i][`XLEN-1:0])); end endgenerate @@ -167,7 +167,7 @@ module freg2adr ( generate for (i = 0; i < numRegs; i = i + 1) begin:register - floprc #(`XLEN) (.clk(clk), .reset(reset), .clear(clear), .d(regInput[i][`XLEN-1:0]), .q(regOutput[i][`XLEN-1:0])); + floprc #(`XLEN) freg[i](.clk(clk), .reset(reset), .clear(clear), .d(regInput[i][`XLEN-1:0]), .q(regOutput[i][`XLEN-1:0])); end endgenerate @@ -340,7 +340,7 @@ module freg3adr ( generate for (i = 0; i < numRegs; i = i + 1) begin:register - floprc #(`XLEN) (.clk(clk), .reset(reset), .clear(clear), .d(regInput[i][`XLEN-1:0]), .q(regOutput[i][`XLEN-1:0])); + floprc #(`XLEN) freg[i](.clk(clk), .reset(reset), .clear(clear), .d(regInput[i][`XLEN-1:0]), .q(regOutput[i][`XLEN-1:0])); end endgenerate diff --git a/wally-pipelined/src/uncore/clint.sv b/wally-pipelined/src/uncore/clint.sv index e3fc1ea04..8436cdbdf 100644 --- a/wally-pipelined/src/uncore/clint.sv +++ b/wally-pipelined/src/uncore/clint.sv @@ -44,7 +44,9 @@ module clint ( assign memread = MemRWclint[1]; assign memwrite = MemRWclint[0]; assign HRESPCLINT = 0; // OK - assign HREADYCLINT = 1; // Respond immediately +// assign HREADYCLINT = 1; // Respond immediately + always_ff @(posedge HCLK) // delay response + HREADYCLINT <= memread | memwrite; // word aligned reads generate @@ -63,7 +65,7 @@ module clint ( // register access generate if (`XLEN==64) begin - always_comb begin + always @(posedge HCLK) begin case(entry) 16'h0000: HREADCLINT = {63'b0, MSIP}; 16'h4000: HREADCLINT = MTIMECMP; @@ -85,7 +87,7 @@ module clint ( else MTIME <= MTIME + 1; end end else begin // 32-bit - always_comb begin + always @(posedge HCLK) begin case(entry) 16'h0000: HREADCLINT = {31'b0, MSIP}; 16'h4000: HREADCLINT = MTIMECMP[31:0]; diff --git a/wally-pipelined/src/uncore/gpio.sv b/wally-pipelined/src/uncore/gpio.sv index aab3c5932..ffea6c72e 100644 --- a/wally-pipelined/src/uncore/gpio.sv +++ b/wally-pipelined/src/uncore/gpio.sv @@ -45,7 +45,9 @@ module gpio ( assign memread = MemRWgpio[1]; assign memwrite = MemRWgpio[0]; assign HRESPGPIO = 0; // OK - assign HREADYGPIO = 1; // Respond immediately + always_ff @(posedge HCLK) // delay response to data cycle + HREADYGPIO <= memread | memwrite; +// assign HREADYGPIO = 1; // Respond immediately // word aligned reads generate @@ -67,12 +69,12 @@ module gpio ( // register access generate if (`XLEN==64) begin - always_comb begin + always_ff @(posedge HCLK) begin case(entry) - 8'h00: HREADGPIO = {INPUT_EN, INPUT_VAL}; - 8'h08: HREADGPIO = {OUTPUT_VAL, OUTPUT_EN}; - 8'h40: HREADGPIO = 0; // OUT_XOR reads as 0 - default: HREADGPIO = 0; + 8'h00: HREADGPIO <= {INPUT_EN, INPUT_VAL}; + 8'h08: HREADGPIO <= {OUTPUT_VAL, OUTPUT_EN}; + 8'h40: HREADGPIO <= 0; // OUT_XOR reads as 0 + default: HREADGPIO <= 0; endcase end always_ff @(posedge HCLK or negedge HRESETn) @@ -86,14 +88,14 @@ module gpio ( if (entry == 8'h40) OUTPUT_VAL <= OUTPUT_VAL ^ HWDATA[31:0]; // OUT_XOR end end else begin // 32-bit - always_comb begin + always_ff @(posedge HCLK) begin case(entry) - 8'h00: HREADGPIO = INPUT_VAL; - 8'h04: HREADGPIO = INPUT_EN; - 8'h08: HREADGPIO = OUTPUT_EN; - 8'h0C: HREADGPIO = OUTPUT_VAL; - 8'h40: HREADGPIO = 0; // OUT_XOR reads as 0 - default: HREADGPIO = 0; + 8'h00: HREADGPIO <= INPUT_VAL; + 8'h04: HREADGPIO <= INPUT_EN; + 8'h08: HREADGPIO <= OUTPUT_EN; + 8'h0C: HREADGPIO <= OUTPUT_VAL; + 8'h40: HREADGPIO <= 0; // OUT_XOR reads as 0 + default: HREADGPIO <= 0; endcase end always_ff @(posedge HCLK or negedge HRESETn) diff --git a/wally-pipelined/src/uncore/uart.sv b/wally-pipelined/src/uncore/uart.sv index ed70d0f7b..48d86e6da 100644 --- a/wally-pipelined/src/uncore/uart.sv +++ b/wally-pipelined/src/uncore/uart.sv @@ -48,11 +48,13 @@ module uart ( assign MEMWb = ~MemRWuart[0]; assign A = HADDR[2:0]; assign HRESPUART = 0; // OK - assign HREADYUART = 1; // Respond immediately + //assign HREADYUART = 1; // Respond immediately + always_ff @(posedge HCLK) // delay response to data cycle + HREADYUART <= ~MEMRb | ~MEMWb; generate if (`XLEN == 64) begin - always_comb begin + always @(posedge HCLK) begin HREADUART = {Dout, Dout, Dout, Dout, Dout, Dout, Dout, Dout}; case (HADDR) 3'b000: Din = HWDATA[7:0]; @@ -66,7 +68,7 @@ module uart ( endcase end end else begin // 32-bit - always_comb begin + always @(posedge HCLK) begin HREADUART = {Dout, Dout, Dout, Dout}; case (HADDR[1:0]) 2'b00: Din = HWDATA[7:0]; From 225102047a91667dd60d4c514eb1c9c145473b25 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 26 Feb 2021 01:03:47 -0500 Subject: [PATCH 32/33] Clean up bus interface code --- wally-pipelined/src/dmem/dmem.sv | 1 - wally-pipelined/src/ebu/ahblite.sv | 98 +--------------------------- wally-pipelined/src/hazard/hazard.sv | 16 ++--- wally-pipelined/src/ifu/ifu.sv | 5 -- 4 files changed, 6 insertions(+), 114 deletions(-) diff --git a/wally-pipelined/src/dmem/dmem.sv b/wally-pipelined/src/dmem/dmem.sv index aab74fadc..1442b93c3 100644 --- a/wally-pipelined/src/dmem/dmem.sv +++ b/wally-pipelined/src/dmem/dmem.sv @@ -65,7 +65,6 @@ module dmem ( // *** this is also the place to squash if the cache is hit assign MemReadM = MemRWM[1] & ~DataMisalignedM; assign MemWriteM = MemRWM[0] & ~DataMisalignedM; -// assign MemRWAlignedM = MemRWM & {2{~DataMisalignedM}}; // Determine if address is valid assign LoadMisalignedFaultM = DataMisalignedM & MemRWM[1]; diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv index ef26a8004..33c05ee8a 100644 --- a/wally-pipelined/src/ebu/ahblite.sv +++ b/wally-pipelined/src/ebu/ahblite.sv @@ -72,8 +72,6 @@ module ahblite ( logic [`AHBW-1:0] HRDATAMasked, ReadDataM, ReadDataPreW; logic IReady, DReady; logic CaptureDataM; -// logic [3:0] HSIZED; // size delayed by one cycle for reads -// logic [2:0] HADDRD; // address delayed for subword reads assign HCLK = clk; assign HRESETn = ~reset; @@ -114,8 +112,7 @@ module ahblite ( // stall signals assign #2 DataStall = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE) || (NextBusState == INSTRREADMEMPENDING); assign #1 InstrStall = (NextBusState == INSTRREAD); - // assign InstrUpdate = (BusState == INSTRREADMEMPENDING) && (NextBusState != INSTRREADMEMPENDING); - + // DH 2/20/22: A cyclic path presently exists // HREADY->NextBusState->GrantData->HSIZE->HSELUART->HREADY // This is because the peripherals assert HREADY on the same cycle @@ -125,6 +122,7 @@ module ahblite ( // bus outputs assign #1 GrantData = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE); assign #1 HADDR = (GrantData) ? MemPAdrM[31:0] : InstrPAdrF[31:0]; + assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width; ignored on reads anyway assign #1 HSIZE = GrantData ? {1'b0, MemSizeM} : ISize; assign HBURST = 3'b000; // Single burst only supported; consider generalizing for cache fillsfH assign HPROT = 4'b0011; // not used; see Section 3.7 @@ -141,104 +139,12 @@ module ahblite ( // Route signals to Instruction and Data Caches // *** assumes AHBW = XLEN - // fix harris 2/24/21 to read all WLEN bits directly for instruction assign InstrRData = HRDATA; - assign ReadDataM = HRDATAMasked; // changed from W to M dh 2/7/2021 assign CaptureDataM = (BusState == MEMREAD) && (NextBusState != MEMREAD); flopenr #(`XLEN) ReadDataPreWReg(clk, reset, CaptureDataM, ReadDataM, ReadDataPreW); // *** this may break when there is no instruction read after data read flopenr #(`XLEN) ReadDataWReg(clk, reset, ~StallW, ReadDataPreW, ReadDataW); - - /* - typedef enum {IDLE, MEMREAD, MEMWRITE, INSTRREAD} statetype; - statetype AdrState, DataState, NextAdrState; // what is happening in the first and second phases of the bus - always_ff @(posedge HCLK, negedge HRESETn) - if (~HRESETn) begin - AdrState <= IDLE; DataState <= IDLE; - HWDATA <= 0; // unnecessary but avoids x at startup - HSIZED <= 0; - HADDRD <= 0; - HWRITED <= 0; - end else begin - if (HREADY || (DataState == IDLE)) begin // only advance bus state if bus is idle or previous transaction returns ready - DataState <= AdrState; - AdrState <= NextAdrState; - if (HWRITE) HWDATA <= WriteDataM; - HSIZED <= {UnsignedLoadM, HSIZE}; - HADDRD <= HADDR[2:0]; - HWRITED <= HWRITE; - end - end - always_comb - if (MemReadM) NextAdrState = MEMREAD; - else if (MemWriteM) NextAdrState = MEMWRITE; - else if (InstrReadF) NextAdrState = INSTRREAD; -// else if (1) NextAdrState = INSTRREAD; // dm 2/9/2021 testing - else NextAdrState = IDLE; - - // Generate acknowledges based on bus state and ready - assign MemAckW = (AdrState == MEMREAD || AdrState == MEMWRITE) && HREADY; - assign InstrAckD = (AdrState == INSTRREAD) && HREADY; - - // State machines for stalls (probably can merge with FSM above***) - // Idle, DataBusy, InstrBusy. Stall while in busystate add suffixes - logic MemState, NextMemState, InstrState, NextInstrState; - flopr #(1) msreg(HCLK, ~HRESETn, NextMemState, MemState); - flopr #(1) isreg(HCLK, ~HRESETn, NextInstrState, InstrState); -/* always_ff @(posedge HCLK, negedge HRESETn) - if (~HRESETn) MemState <= 0; - else MemState <= NextMemState; - assign NextMemState = (MemState == 0 && InstrState == 0 && (MemReadM || MemWriteM)) || (MemState == 1 && ~MemAckW); - assign DataStall = NextMemState; -/* always_ff @(posedge HCLK, negedge HRESETn) - if (~HRESETn) InstrState <= 0; - else InstrState <= NextInstrState; - - assign NextInstrState = (InstrState == 0 && MemState == 0 && (~MemReadM && ~MemWriteM && InstrReadF)) || - (InstrState == 1 && ~InstrAckD) || - (InstrState == 1 && ResolveBranchD); // dh 2/8/2021 fixing; delete this later -/* assign NextInstrState = (InstrState == 0 && MemState == 0 && (~MemReadM && ~MemWriteM)) || - (InstrState == 1 && ~InstrAckD); // *** removed InstrReadF above dh 2/9/20 - assign InstrStall = NextInstrState | MemState | NextMemState; // *** check this, explain better - // temporarily turn off stalls and check it works - //assign DataStall = 0; - //assign InstrStall = 0; - - assign DReady = HREADY & GrantData; // ***unused? - assign IReady = HREADY & InstrReadF & ~GrantData; // maybe unused?*** - -*/ - - // Choose ISize based on XLen - generate - //if (`AHBW == 32) assign ISize = 3'b010; // 32-bit transfers - //else assign ISize = 3'b011; // 64-bit transfers - assign ISize = 3'b010; // 32 bit instructions for now; later improve for filling cache with full width - endgenerate -/* - // drive bus outputs - assign HADDR = GrantData ? MemPAdrM[31:0] : InstrPAdrF[31:0]; - //assign HWDATA = WriteDataW; - //flop #(`XLEN) wdreg(HCLK, DWDataM, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN - assign HWRITE = MemWriteM; - assign HSIZE = GrantData ? {1'b0, MemSizeM} : ISize; - assign HBURST = 3'b000; // Single burst only supported; consider generalizing for cache fillsfHPROT - assign HPROT = 4'b0011; // not used; see Section 3.7 - assign HTRANS = InstrReadF | MemReadM | MemWriteM ? 2'b10 : 2'b00; // NONSEQ if reading or writing, IDLE otherwise - assign HMASTLOCK = 0; // no locking supported - */ - - - // stalls - // Stall MEM stage if data is being accessed and bus isn't yet ready - //assign DataStall = GrantData & ~HREADY; - // Stall Fetch stage if instruction should be read but reading data or bus isn't ready - //assign InstrStall = IReadF & (GrantData | ~HREADY); - - // *** consider adding memory access faults based on HRESP being high - // InstrAccessFaultF, DataAccessFaultM, - subwordread swr(.*); endmodule diff --git a/wally-pipelined/src/hazard/hazard.sv b/wally-pipelined/src/hazard/hazard.sv index 3055c4f17..2321c6528 100644 --- a/wally-pipelined/src/hazard/hazard.sv +++ b/wally-pipelined/src/hazard/hazard.sv @@ -27,13 +27,10 @@ module hazard( // Detect hazards -// input logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW, -// input logic MemReadE, -// input logic RegWriteM, RegWriteW, input logic PCSrcE, CSRWritePendingDEM, RetM, TrapM, input logic LoadStallD, MulDivStallD, input logic InstrStall, DataStall, - // Stall outputs + // Stall & flush outputs output logic StallF, StallD, StallE, StallM, StallW, output logic FlushD, FlushE, FlushM, FlushW ); @@ -56,15 +53,10 @@ module hazard( assign BranchFlushDE = PCSrcE | RetM | TrapM; - // changed 2/22/21 harris to turn off stallF when RetM or TrapM - // changed 2/23/21 harris to BranchFlushDEM to solve bug in ECALL about JAL being ignored -// assign StallFCause = /*InstrStall | */ CSRWritePendingDEM; // stall at fetch if unable to get the instruction, -// assign StallFCause = /*InstrStall | */ CSRWritePendingDEM & ~(RetM | TrapM); // stall at fetch if unable to get the instruction, - assign StallFCause = /*InstrStall | */ CSRWritePendingDEM & ~(BranchFlushDE); // stall at fetch if unable to get the instruction, - // or if a CSR will be written and may change system behavior - assign StallDCause = LoadStallD | MulDivStallD; // stall in decode if instruction is a load dependent on previous + assign StallFCause = CSRWritePendingDEM & ~(BranchFlushDE); + assign StallDCause = LoadStallD | MulDivStallD; // stall in decode if instruction is a load/mul dependent on previous assign StallECause = 0; - assign StallMCause = 0; // sDataStall; // not yet used*** + assign StallMCause = 0; assign StallWCause = DataStall | InstrStall; // Each stage stalls if the next stage is stalled or there is a cause to stall this stage. diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index 3deb64255..f9ea91ee9 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -74,14 +74,9 @@ module ifu ( assign PrivilegedChangePCM = RetM | TrapM; - //assign StallExceptResolveBranchesF = StallF & ~(PCSrcE | PrivilegedChangePCM); - - // dh 2/8/2022 keep in instruction fetch stall mode when taking branch - //flopr #(1) rbreg(clk, reset, (PCSrcE | PrivilegedChangePCM), ResolveBranchD); mux3 #(`XLEN) pcmux(PCPlus2or4F, PCTargetE, PrivilegedNextPCM, {PrivilegedChangePCM, PCSrcE}, UnalignedPCNextF); assign PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment -// flopenl #(`XLEN) pcreg(clk, reset, ~StallExceptResolveBranchesF, PCNextF, `RESET_VECTOR, PCF); flopenl #(`XLEN) pcreg(clk, reset, ~StallF, PCNextF, `RESET_VECTOR, PCF); // pcadder From 0258901865436a9508e4ea7b3ed0c483fdf1c9ba Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 26 Feb 2021 09:17:36 -0500 Subject: [PATCH 33/33] Cleaned out unused signals --- wally-pipelined/src/ebu/ahblite.sv | 1 - wally-pipelined/src/ieu/controller.sv | 2 -- wally-pipelined/src/ieu/datapath.sv | 4 ---- wally-pipelined/src/ieu/ieu.sv | 5 ++-- wally-pipelined/src/ifu/ifu.sv | 4 +--- wally-pipelined/src/muldiv/mul.sv | 2 +- wally-pipelined/src/privileged/csrs.sv | 7 +++--- wally-pipelined/src/uncore/clint.sv | 20 ++++++++-------- wally-pipelined/src/uncore/uart.sv | 24 +++++++++---------- .../src/wally/wallypipelinedhart.sv | 2 -- .../src/wally/wallypipelinedsoc.sv | 2 +- 11 files changed, 31 insertions(+), 42 deletions(-) diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv index 33c05ee8a..10aa1f1ae 100644 --- a/wally-pipelined/src/ebu/ahblite.sv +++ b/wally-pipelined/src/ebu/ahblite.sv @@ -38,7 +38,6 @@ module ahblite ( // Signals from Instruction Cache input logic [`XLEN-1:0] InstrPAdrF, // *** rename these to match block diagram input logic InstrReadF, -// input logic ResolveBranchD, output logic [`XLEN-1:0] InstrRData, // Signals from Data Cache input logic [`XLEN-1:0] MemPAdrM, diff --git a/wally-pipelined/src/ieu/controller.sv b/wally-pipelined/src/ieu/controller.sv index 69fa23264..a369785ae 100644 --- a/wally-pipelined/src/ieu/controller.sv +++ b/wally-pipelined/src/ieu/controller.sv @@ -33,7 +33,6 @@ module controller( input logic [2:0] Funct3D, input logic [6:0] Funct7D, output logic [2:0] ImmSrcD, - input logic StallD, FlushD, input logic IllegalIEUInstrFaultD, output logic IllegalBaseInstrFaultD, // Execute stage control signals @@ -48,7 +47,6 @@ module controller( output logic MulDivE, W64E, // Memory stage control signals input logic StallM, FlushM, - input logic DataMisalignedM, output logic [1:0] MemRWM, output logic CSRWriteM, PrivilegedM, output logic [2:0] Funct3M, diff --git a/wally-pipelined/src/ieu/datapath.sv b/wally-pipelined/src/ieu/datapath.sv index db060dc2b..022cc6259 100644 --- a/wally-pipelined/src/ieu/datapath.sv +++ b/wally-pipelined/src/ieu/datapath.sv @@ -28,13 +28,11 @@ module datapath ( input logic clk, reset, // Decode stage signals - input logic StallD, FlushD, input logic [2:0] ImmSrcD, input logic [31:0] InstrD, // Execute stage signals input logic StallE, FlushE, input logic [1:0] ForwardAE, ForwardBE, - input logic PCSrcE, input logic [4:0] ALUControlE, input logic ALUSrcAE, ALUSrcBE, input logic TargetSrcE, @@ -44,8 +42,6 @@ module datapath ( output logic [`XLEN-1:0] SrcAE, SrcBE, // Memory stage signals input logic StallM, FlushM, - input logic [2:0] Funct3M, - input logic RetM, TrapM, output logic [`XLEN-1:0] SrcAM, output logic [`XLEN-1:0] WriteDataM, MemAdrM, // Writeback stage signals diff --git a/wally-pipelined/src/ieu/ieu.sv b/wally-pipelined/src/ieu/ieu.sv index 2e5305981..d0588c736 100644 --- a/wally-pipelined/src/ieu/ieu.sv +++ b/wally-pipelined/src/ieu/ieu.sv @@ -49,9 +49,8 @@ module ieu ( input logic [`XLEN-1:0] PCLinkW, output logic InstrValidW, // hazards - input logic StallF, StallD, StallE, StallM, StallW, - input logic FlushD, FlushE, FlushM, FlushW, - input logic RetM, TrapM, + input logic StallE, StallM, StallW, + input logic FlushE, FlushM, FlushW, output logic LoadStallD, MulDivStallD, output logic PCSrcE, diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index f9ea91ee9..1cddbe6dd 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -36,8 +36,6 @@ module ifu ( output logic [`XLEN-1:0] InstrPAdrF, output logic InstrReadF, // Decode - //output logic InstrStall, - output logic ResolveBranchD, // Execute input logic PCSrcE, input logic [`XLEN-1:0] PCTargetE, @@ -60,7 +58,7 @@ module ifu ( logic [`XLEN-1:0] UnalignedPCNextF, PCNextF; logic misaligned, BranchMisalignedFaultE, BranchMisalignedFaultM, TrapMisalignedFaultM; - logic StallExceptResolveBranchesF, PrivilegedChangePCM; + logic PrivilegedChangePCM; logic IllegalCompInstrD; logic [`XLEN-1:0] PCPlusUpperF, PCPlus2or4F, PCD, PCW, PCLinkD, PCLinkE, PCLinkM; logic CompressedF; diff --git a/wally-pipelined/src/muldiv/mul.sv b/wally-pipelined/src/muldiv/mul.sv index e7a13be54..6ed5490d2 100644 --- a/wally-pipelined/src/muldiv/mul.sv +++ b/wally-pipelined/src/muldiv/mul.sv @@ -61,7 +61,7 @@ module mul ( // flavor of multiplication assign MULH = (Funct3E == 2'b01); assign MULHSU = (Funct3E == 2'b10); - assign MULHU = (Funct3E == 2'b11); + // assign MULHU = (Funct3E == 2'b11); // signal unused // Handle signs assign PP1 = Pprime; // same for all flavors diff --git a/wally-pipelined/src/privileged/csrs.sv b/wally-pipelined/src/privileged/csrs.sv index 9de3723a5..8301eed51 100644 --- a/wally-pipelined/src/privileged/csrs.sv +++ b/wally-pipelined/src/privileged/csrs.sv @@ -60,15 +60,13 @@ module csrs #(parameter // Supervisor mode CSRs sometimes supported generate if (`S_SUPPORTED) begin - logic WriteSTVECM, WriteSEDELEGM, WriteSIDELEGM; + logic WriteSTVECM; logic WriteSSCRATCHM, WriteSEPCM; logic WriteSCAUSEM, WriteSTVALM, WriteSATPM, WriteSCOUNTERENM; logic [`XLEN-1:0] SSCRATCH_REGW, SCAUSE_REGW, STVAL_REGW, SATP_REGW; assign WriteSSTATUSM = CSRSWriteM && (CSRAdrM == SSTATUS); assign WriteSTVECM = CSRSWriteM && (CSRAdrM == STVEC); - assign WriteSEDELEGM = CSRSWriteM && (CSRAdrM == SEDELEG); - assign WriteSIDELEGM = CSRSWriteM && (CSRAdrM == SIDELEG); assign WriteSSCRATCHM = CSRSWriteM && (CSRAdrM == SSCRATCH); assign WriteSEPCM = STrapM | (CSRSWriteM && (CSRAdrM == SEPC)); assign WriteSCAUSEM = STrapM | (CSRSWriteM && (CSRAdrM == SCAUSE)); @@ -85,6 +83,9 @@ module csrs #(parameter flopenr #(`XLEN) SATPreg(clk, reset, WriteSATPM, CSRWriteValM, SATP_REGW); flopenl #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], allones, SCOUNTEREN_REGW); if (`N_SUPPORTED) begin + logic WriteSEDELEGM, WriteSIDELEGM; + assign WriteSEDELEGM = CSRSWriteM && (CSRAdrM == SEDELEG); + assign WriteSIDELEGM = CSRSWriteM && (CSRAdrM == SIDELEG); flopenl #(`XLEN) SEDELEGreg(clk, reset, WriteSEDELEGM, CSRWriteValM & SEDELEG_MASK, zero, SEDELEG_REGW); flopenl #(`XLEN) SIDELEGreg(clk, reset, WriteSIDELEGM, CSRWriteValM, zero, SIDELEG_REGW); end else begin diff --git a/wally-pipelined/src/uncore/clint.sv b/wally-pipelined/src/uncore/clint.sv index 8436cdbdf..215ef7df0 100644 --- a/wally-pipelined/src/uncore/clint.sv +++ b/wally-pipelined/src/uncore/clint.sv @@ -67,10 +67,10 @@ module clint ( if (`XLEN==64) begin always @(posedge HCLK) begin case(entry) - 16'h0000: HREADCLINT = {63'b0, MSIP}; - 16'h4000: HREADCLINT = MTIMECMP; - 16'hBFF8: HREADCLINT = MTIME; - default: HREADCLINT = 0; + 16'h0000: HREADCLINT <= {63'b0, MSIP}; + 16'h4000: HREADCLINT <= MTIMECMP; + 16'hBFF8: HREADCLINT <= MTIME; + default: HREADCLINT <= 0; endcase end always_ff @(posedge HCLK or negedge HRESETn) @@ -89,12 +89,12 @@ module clint ( end else begin // 32-bit always @(posedge HCLK) begin case(entry) - 16'h0000: HREADCLINT = {31'b0, MSIP}; - 16'h4000: HREADCLINT = MTIMECMP[31:0]; - 16'h4004: HREADCLINT = MTIMECMP[63:32]; - 16'hBFF8: HREADCLINT = MTIME[31:0]; - 16'hBFFC: HREADCLINT = MTIME[63:32]; - default: HREADCLINT = 0; + 16'h0000: HREADCLINT <= {31'b0, MSIP}; + 16'h4000: HREADCLINT <= MTIMECMP[31:0]; + 16'h4004: HREADCLINT <= MTIMECMP[63:32]; + 16'hBFF8: HREADCLINT <= MTIME[31:0]; + 16'hBFFC: HREADCLINT <= MTIME[63:32]; + default: HREADCLINT <= 0; endcase end always_ff @(posedge HCLK or negedge HRESETn) diff --git a/wally-pipelined/src/uncore/uart.sv b/wally-pipelined/src/uncore/uart.sv index 48d86e6da..b4854981a 100644 --- a/wally-pipelined/src/uncore/uart.sv +++ b/wally-pipelined/src/uncore/uart.sv @@ -57,24 +57,24 @@ module uart ( always @(posedge HCLK) begin HREADUART = {Dout, Dout, Dout, Dout, Dout, Dout, Dout, Dout}; case (HADDR) - 3'b000: Din = HWDATA[7:0]; - 3'b001: Din = HWDATA[15:8]; - 3'b010: Din = HWDATA[23:16]; - 3'b011: Din = HWDATA[31:24]; - 3'b100: Din = HWDATA[39:32]; - 3'b101: Din = HWDATA[47:40]; - 3'b110: Din = HWDATA[55:48]; - 3'b111: Din = HWDATA[63:56]; + 3'b000: Din <= HWDATA[7:0]; + 3'b001: Din <= HWDATA[15:8]; + 3'b010: Din <= HWDATA[23:16]; + 3'b011: Din <= HWDATA[31:24]; + 3'b100: Din <= HWDATA[39:32]; + 3'b101: Din <= HWDATA[47:40]; + 3'b110: Din <= HWDATA[55:48]; + 3'b111: Din <= HWDATA[63:56]; endcase end end else begin // 32-bit always @(posedge HCLK) begin HREADUART = {Dout, Dout, Dout, Dout}; case (HADDR[1:0]) - 2'b00: Din = HWDATA[7:0]; - 2'b01: Din = HWDATA[15:8]; - 2'b10: Din = HWDATA[23:16]; - 2'b11: Din = HWDATA[31:24]; + 2'b00: Din <= HWDATA[7:0]; + 2'b01: Din <= HWDATA[15:8]; + 2'b10: Din <= HWDATA[23:16]; + 2'b11: Din <= HWDATA[31:24]; endcase end end diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index d468283d0..6ea1a4aae 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -78,8 +78,6 @@ module wallypipelinedhart ( logic LoadMisalignedFaultM, LoadAccessFaultM; logic StoreMisalignedFaultM, StoreAccessFaultM; logic [`XLEN-1:0] InstrMisalignedAdrM; - logic [`XLEN-1:0] zero = 0; - logic ResolveBranchD; logic PCSrcE; logic CSRWritePendingDEM; diff --git a/wally-pipelined/src/wally/wallypipelinedsoc.sv b/wally-pipelined/src/wally/wallypipelinedsoc.sv index 7b8883c57..81f0faf40 100644 --- a/wally-pipelined/src/wally/wallypipelinedsoc.sv +++ b/wally-pipelined/src/wally/wallypipelinedsoc.sv @@ -56,7 +56,6 @@ module wallypipelinedsoc ( // to instruction memory *** remove later logic [`XLEN-1:0] PCF; - logic [31:0] InstrF; // Uncore signals logic [`AHBW-1:0] HRDATA; // from AHB mux in uncore @@ -68,6 +67,7 @@ module wallypipelinedsoc ( logic [3:0] HSIZED; logic HWRITED; logic [15:0] rd2; // bogus, delete when real multicycle fetch works + logic [31:0] InstrF; // instantiate processor and memories wallypipelinedhart hart(.*);