From e831baf335ee375386685a297623fb731d06a395 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 4 Feb 2023 03:42:20 -0800 Subject: [PATCH] Improved illegal NaN-box detection and formatted fsgninj --- src/fpu/fsgninj.sv | 18 +++++++++--------- src/fpu/unpack.sv | 11 +++++------ src/fpu/unpackinput.sv | 25 ++++++++++++++----------- 3 files changed, 28 insertions(+), 26 deletions(-) diff --git a/src/fpu/fsgninj.sv b/src/fpu/fsgninj.sv index d5568cabe..0db7dc2f3 100755 --- a/src/fpu/fsgninj.sv +++ b/src/fpu/fsgninj.sv @@ -29,11 +29,11 @@ `include "wally-config.vh" module fsgninj ( - input logic Xs, Ys, // X and Y sign bits - input logic [`FLEN-1:0] X, // X - input logic [`FMTBITS-1:0] Fmt, // format - input logic [1:0] OpCtrl, // operation control - output logic [`FLEN-1:0] SgnRes // result + input logic Xs, Ys, // X and Y sign bits + input logic [`FLEN-1:0] X, // X + input logic [`FMTBITS-1:0] Fmt, // format + input logic [1:0] OpCtrl, // operation control + output logic [`FLEN-1:0] SgnRes // result ); logic ResSgn; // result sign @@ -54,13 +54,13 @@ module fsgninj ( assign SgnRes = {ResSgn, X[`FLEN-2:0]}; else if (`FPSIZES == 2) assign SgnRes = {~Fmt|ResSgn, X[`FLEN-2:`LEN1], Fmt ? X[`LEN1-1] : ResSgn, X[`LEN1-2:0]}; - else if (`FPSIZES == 3) begin + else if (`FPSIZES == 3) begin logic [2:0] SgnBits; always_comb case (Fmt) - `FMT: SgnBits = {ResSgn, X[`LEN1-1], X[`LEN2-1]}; - `FMT1: SgnBits = {1'b1, ResSgn, X[`LEN2-1]}; - `FMT2: SgnBits = {2'b11, ResSgn}; + `FMT: SgnBits = {ResSgn, X[`LEN1-1], X[`LEN2-1]}; + `FMT1: SgnBits = {1'b1, ResSgn, X[`LEN2-1]}; + `FMT2: SgnBits = {2'b11, ResSgn}; default: SgnBits = {3{1'bx}}; endcase assign SgnRes = {SgnBits[2], X[`FLEN-2:`LEN1], SgnBits[1], X[`LEN1-2:`LEN2], SgnBits[0], X[`LEN2-2:0]}; diff --git a/src/fpu/unpack.sv b/src/fpu/unpack.sv index 13addc2e3..356d7e897 100644 --- a/src/fpu/unpack.sv +++ b/src/fpu/unpack.sv @@ -48,15 +48,14 @@ module unpack ( unpackinput unpackinputX (.In(X), .Fmt, .Sgn(Xs), .Exp(Xe), .Man(Xm), .En(XEn), .NaN(XNaN), .SNaN(XSNaN), .ExpNonZero(XExpNonZero), - .Zero(XZero), .Inf(XInf), .ExpMax(XExpMax), .FracZero(XFracZero)); + .Zero(XZero), .Inf(XInf), .ExpMax(XExpMax), .FracZero(XFracZero), .Subnorm(XSubnorm)); unpackinput unpackinputY (.In(Y), .Fmt, .Sgn(Ys), .Exp(Ye), .Man(Ym), .En(YEn), .NaN(YNaN), .SNaN(YSNaN), .ExpNonZero(YExpNonZero), - .Zero(YZero), .Inf(YInf), .ExpMax(YExpMax), .FracZero(YFracZero)); + .Zero(YZero), .Inf(YInf), .ExpMax(YExpMax), .FracZero(YFracZero), .Subnorm()); unpackinput unpackinputZ (.In(Z), .Fmt, .Sgn(Zs), .Exp(Ze), .Man(Zm), .En(ZEn), .NaN(ZNaN), .SNaN(ZSNaN), .ExpNonZero(ZExpNonZero), - .Zero(ZZero), .Inf(ZInf), .ExpMax(ZExpMax), .FracZero(ZFracZero)); - // is the input subnormal - assign XSubnorm = ~XExpNonZero & ~XFracZero; -endmodule \ No newline at end of file + .Zero(ZZero), .Inf(ZInf), .ExpMax(ZExpMax), .FracZero(ZFracZero), .Subnorm()); + + endmodule \ No newline at end of file diff --git a/src/fpu/unpackinput.sv b/src/fpu/unpackinput.sv index 34663bd8c..b85077d20 100644 --- a/src/fpu/unpackinput.sv +++ b/src/fpu/unpackinput.sv @@ -31,16 +31,17 @@ module unpackinput ( input logic [`FLEN-1:0] In, // inputs from register file input logic En, // enable the input input logic [`FMTBITS-1:0] Fmt, // format signal 00 - single 01 - double 11 - quad 10 - half - output logic Sgn, // sign bits of XYZ - output logic [`NE-1:0] Exp, // exponents of XYZ (converted to largest supported precision) - output logic [`NF:0] Man, // mantissas of XYZ (converted to largest supported precision) - output logic NaN, // is XYZ a NaN - output logic SNaN, // is XYZ a signaling NaN - output logic Zero, // is XYZ zero - output logic Inf, // is XYZ infinity + output logic Sgn, // sign bits of the number + output logic [`NE-1:0] Exp, // exponent of the number (converted to largest supported precision) + output logic [`NF:0] Man, // mantissa of the number (converted to largest supported precision) + output logic NaN, // is the number a NaN + output logic SNaN, // is the number a signaling NaN + output logic Zero, // is the number zero + output logic Inf, // is the number infinity output logic ExpNonZero, // is the exponent not zero output logic FracZero, // is the fraction zero - output logic ExpMax // does In have the maximum exponent (NaN or Inf) + output logic ExpMax, // does In have the maximum exponent (NaN or Inf) + output logic Subnorm // is the number subnormal ); logic [`NF-1:0] Frac; // Fraction of XYZ @@ -261,10 +262,12 @@ module unpackinput ( end // Output logic - assign FracZero = ~|Frac; // is the fraction zero? + assign FracZero = ~|Frac & ~BadNaNBox; // is the fraction zero? assign Man = {ExpNonZero, Frac}; // add the assumed one (or zero if Subnormal or zero) to create the significand assign NaN = ((ExpMax & ~FracZero)|BadNaNBox)&En; // is the input a NaN? assign SNaN = NaN&~Frac[`NF-1]&~BadNaNBox; // is the input a singnaling NaN? - assign Inf = ExpMax & FracZero &En; // is the input infinity? - assign Zero = ~ExpNonZero & FracZero; // is the input zero? + assign Inf = ExpMax & FracZero &En & ~BadNaNBox; // is the input infinity? + assign Zero = ~ExpNonZero & FracZero & ~BadNaNBox; // is the input zero? + assign Subnorm = ~ExpNonZero & ~FracZero & ~BadNaNBox; // is the input subnormal + endmodule \ No newline at end of file