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https://github.com/openhwgroup/cvw
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Added IDIV_ON_FPU flag to control whether integer division uses FPU
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@ -72,6 +72,7 @@
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// Integer Divider Configuration
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// Integer Divider Configuration
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// DIV_BITSPERCYCLE must be 1, 2, or 4
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// DIV_BITSPERCYCLE must be 1, 2, or 4
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`define DIV_BITSPERCYCLE 4
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`define DIV_BITSPERCYCLE 4
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`define IDIV_ON_FPU 0
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// Legal number of PMP entries are 0, 16, or 64
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// Legal number of PMP entries are 0, 16, or 64
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`define PMP_ENTRIES 16
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`define PMP_ENTRIES 16
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@ -74,6 +74,7 @@
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// Integer Divider Configuration
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// Integer Divider Configuration
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// DIV_BITSPERCYCLE must be 1, 2, or 4
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// DIV_BITSPERCYCLE must be 1, 2, or 4
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`define DIV_BITSPERCYCLE 4
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`define DIV_BITSPERCYCLE 4
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`define IDIV_ON_FPU 0
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// Legal number of PMP entries are 0, 16, or 64
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// Legal number of PMP entries are 0, 16, or 64
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`define PMP_ENTRIES 64
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`define PMP_ENTRIES 64
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@ -73,6 +73,7 @@
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// Integer Divider Configuration
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// Integer Divider Configuration
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// DIV_BITSPERCYCLE must be 1, 2, or 4
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// DIV_BITSPERCYCLE must be 1, 2, or 4
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`define DIV_BITSPERCYCLE 1
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`define DIV_BITSPERCYCLE 1
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`define IDIV_ON_FPU 0
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// Legal number of PMP entries are 0, 16, or 64
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// Legal number of PMP entries are 0, 16, or 64
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`define PMP_ENTRIES 0
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`define PMP_ENTRIES 0
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@ -72,6 +72,7 @@
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// Integer Divider Configuration
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// Integer Divider Configuration
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// DIV_BITSPERCYCLE must be 1, 2, or 4
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// DIV_BITSPERCYCLE must be 1, 2, or 4
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`define DIV_BITSPERCYCLE 4
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`define DIV_BITSPERCYCLE 4
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`define IDIV_ON_FPU 0
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// Legal number of PMP entries are 0, 16, or 64
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// Legal number of PMP entries are 0, 16, or 64
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`define PMP_ENTRIES 64
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`define PMP_ENTRIES 64
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@ -73,6 +73,7 @@
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// Integer Divider Configuration
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// Integer Divider Configuration
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// DIV_BITSPERCYCLE must be 1, 2, or 4
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// DIV_BITSPERCYCLE must be 1, 2, or 4
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`define DIV_BITSPERCYCLE 4
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`define DIV_BITSPERCYCLE 4
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`define IDIV_ON_FPU 0
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// Legal number of PMP entries are 0, 16, or 64
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// Legal number of PMP entries are 0, 16, or 64
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`define PMP_ENTRIES 64
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`define PMP_ENTRIES 64
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@ -72,6 +72,7 @@
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// Integer Divider Configuration
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// Integer Divider Configuration
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// DIV_BITSPERCYCLE must be 1, 2, or 4
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// DIV_BITSPERCYCLE must be 1, 2, or 4
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`define DIV_BITSPERCYCLE 4
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`define DIV_BITSPERCYCLE 4
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`define IDIV_ON_FPU 0
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// Legal number of PMP entries are 0, 16, or 64
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// Legal number of PMP entries are 0, 16, or 64
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`define PMP_ENTRIES 0
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`define PMP_ENTRIES 0
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@ -76,6 +76,7 @@
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// Integer Divider Configuration
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// Integer Divider Configuration
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// DIV_BITSPERCYCLE must be 1, 2, or 4
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// DIV_BITSPERCYCLE must be 1, 2, or 4
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`define DIV_BITSPERCYCLE 4
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`define DIV_BITSPERCYCLE 4
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`define IDIV_ON_FPU 0
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// Address space
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// Address space
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`define RESET_VECTOR 64'h0000000000001000
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`define RESET_VECTOR 64'h0000000000001000
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@ -74,6 +74,7 @@
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// Integer Divider Configuration
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// Integer Divider Configuration
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// DIV_BITSPERCYCLE must be 1, 2, or 4
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// DIV_BITSPERCYCLE must be 1, 2, or 4
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`define DIV_BITSPERCYCLE 4
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`define DIV_BITSPERCYCLE 4
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`define IDIV_ON_FPU 0
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// Legal number of PMP entries are 0, 16, or 64
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// Legal number of PMP entries are 0, 16, or 64
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`define PMP_ENTRIES 64
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`define PMP_ENTRIES 64
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@ -74,6 +74,7 @@
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// Integer Divider Configuration
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// Integer Divider Configuration
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// DIV_BITSPERCYCLE must be 1, 2, or 4
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// DIV_BITSPERCYCLE must be 1, 2, or 4
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`define DIV_BITSPERCYCLE 4
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`define DIV_BITSPERCYCLE 4
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`define IDIV_ON_FPU 0
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// Legal number of PMP entries are 0, 16, or 64
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// Legal number of PMP entries are 0, 16, or 64
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`define PMP_ENTRIES 64
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`define PMP_ENTRIES 64
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@ -74,6 +74,7 @@
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// Integer Divider Configuration
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// Integer Divider Configuration
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// DIV_BITSPERCYCLE must be 1, 2, or 4
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// DIV_BITSPERCYCLE must be 1, 2, or 4
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`define DIV_BITSPERCYCLE 4
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`define DIV_BITSPERCYCLE 4
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`define IDIV_ON_FPU 0
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// Legal number of PMP entries are 0, 16, or 64
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// Legal number of PMP entries are 0, 16, or 64
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`define PMP_ENTRIES 0
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`define PMP_ENTRIES 0
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@ -126,7 +126,11 @@ module datapath (
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if (`F_SUPPORTED) begin:fpmux
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if (`F_SUPPORTED) begin:fpmux
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mux2 #(`XLEN) resultmuxM(IEUResultM, FIntResM, FWriteIntM, IFResultM);
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mux2 #(`XLEN) resultmuxM(IEUResultM, FIntResM, FWriteIntM, IFResultM);
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mux2 #(`XLEN) cvtresultmuxW(IFResultW, FCvtIntResW, FCvtIntW, IFCvtResultW);
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mux2 #(`XLEN) cvtresultmuxW(IFResultW, FCvtIntResW, FCvtIntW, IFCvtResultW);
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mux2 #(`XLEN) divresultmuxW(MDUResultW, FPIntDivResultW, DivW, MulDivResultW);
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if (`IDIV_ON_FPU) begin
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mux2 #(`XLEN) divresultmuxW(MDUResultW, FPIntDivResultW, DivW, MulDivResultW);
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end else begin
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assign MulDivResultW = MDUResultW;
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end
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end else begin:fpmux
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end else begin:fpmux
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assign IFResultM = IEUResultM; assign IFCvtResultW = IFResultW;
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assign IFResultM = IEUResultM; assign IFCvtResultW = IFResultW;
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assign MulDivResultW = MDUResultW;
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assign MulDivResultW = MDUResultW;
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@ -60,7 +60,7 @@ module muldiv (
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// Divide
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// Divide
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// Start a divide when a new division instruction is received and the divider isn't already busy or finishing
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// Start a divide when a new division instruction is received and the divider isn't already busy or finishing
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// When F extensions are supported, use the FPU divider instead
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// When F extensions are supported, use the FPU divider instead
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if (`F_SUPPORTED) begin
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if (`IDIV_ON_FPU) begin
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assign QuotM = 0;
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assign QuotM = 0;
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assign RemM = 0;
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assign RemM = 0;
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assign DivBusyE = 0;
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assign DivBusyE = 0;
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