Can now support the following memory and bus configurations.

1. dtim/irom only
2. bus only
3. dtim/irom + bus
4. caches + bus

pipelined/config/buildroot/wally-config.vh

@@ -49,6 +49,8 @@
 `define UARCH_SINGLECYCLE 0
 `define DMEM `MEM_CACHE
 `define IMEM `MEM_CACHE
+`define DBUS 1
+`define IBUS 1
 `define VIRTMEM_SUPPORTED 1
 `define VECTORED_INTERRUPTS_SUPPORTED 1 
 

pipelined/config/fpga/wally-config.vh

@@ -49,6 +49,8 @@
 `define UARCH_SINGLECYCLE 0
 `define DMEM `MEM_CACHE
 `define IMEM `MEM_CACHE
+`define DBUS 1
+`define IBUS 1
 `define VIRTMEM_SUPPORTED 1
 `define VECTORED_INTERRUPTS_SUPPORTED 1 
 

pipelined/config/rv32e/wally-config.vh

@@ -49,8 +49,10 @@
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
 // *** replace with MEM_BUS
-`define DMEM `MEM_BUS
+`define DMEM `MEM_NONE
-`define IMEM `MEM_BUS
+`define IMEM `MEM_NONE
+`define DBUS 1
+`define IBUS 1
 `define VIRTMEM_SUPPORTED 0
 `define VECTORED_INTERRUPTS_SUPPORTED 0 
 

pipelined/config/rv32gc/wally-config.vh

@@ -49,6 +49,8 @@
 `define UARCH_SINGLECYCLE 0
 `define DMEM `MEM_CACHE
 `define IMEM `MEM_CACHE
+`define DBUS 1
+`define IBUS 1
 `define VIRTMEM_SUPPORTED 1
 `define VECTORED_INTERRUPTS_SUPPORTED 1 
 

pipelined/config/rv32ic/wally-config.vh

@@ -49,6 +49,8 @@
 `define UARCH_SINGLECYCLE 0
 `define DMEM `MEM_TIM
 `define IMEM `MEM_TIM
+`define DBUS 0
+`define IBUS 0
 `define VIRTMEM_SUPPORTED 0
 `define VECTORED_INTERRUPTS_SUPPORTED 1 
 

pipelined/config/rv64BP/wally-config.vh

@@ -51,6 +51,8 @@
 `define UARCH_SINGLECYCLE 0
 `define DMEM `MEM_CACHE
 `define IMEM `MEM_CACHE
+`define DBUS 1
+`define IBUS 1
 `define VIRTMEM_SUPPORTED 1
 `define VECTORED_INTERRUPTS_SUPPORTED 1 
 

pipelined/config/rv64gc/wally-config.vh

@@ -50,6 +50,8 @@
 `define UARCH_SINGLECYCLE 0
 `define DMEM `MEM_CACHE
 `define IMEM `MEM_CACHE
+`define DBUS 1
+`define IBUS 1
 `define VIRTMEM_SUPPORTED 1
 `define VECTORED_INTERRUPTS_SUPPORTED 1 
 

pipelined/config/rv64ic/wally-config.vh

@@ -50,6 +50,8 @@
 `define UARCH_SINGLECYCLE 0
 `define DMEM `MEM_TIM
 `define IMEM `MEM_TIM
+`define DBUS 0
+`define IBUS 0
 `define VIRTMEM_SUPPORTED 0
 `define VECTORED_INTERRUPTS_SUPPORTED 1 
 

pipelined/config/shared/wally-constants.vh

@@ -50,7 +50,7 @@
 `define SV39 8
 `define SV48 9
 
-`define MEM_BUS 1
+`define MEM_NONE 1
 `define MEM_TIM 2
 `define MEM_CACHE 3
 

pipelined/src/ifu/ifu.sv

@@ -176,11 +176,12 @@ module ifu (
   if (`IMEM == `MEM_TIM) begin : irom // *** fix up dtim taking PA_BITS rather than XLEN, *** IEUAdr is a bad name.  Probably use a ROM rather than DTIM
     dtim irom(.clk, .reset, .CPUBusy, .LSURWM(2'b10), .IEUAdrM(PCPF[31:0]), .IEUAdrE(PCNextFSpill),
               .TrapM(1'b0), .FinalWriteDataM(), .ByteMaskM('0),
-              .ReadDataWordM(AllInstrRawF), .BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead),
+              .ReadDataWordM(FinalInstrRawF), .BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead),
               .BusCommittedM(), .DCacheStallM(ICacheStallF), 
               .DCacheCommittedM(), .DCacheMiss(ICacheMiss), .DCacheAccess(ICacheAccess));
     
-  end else begin : bus
+  end 
+  if (`IBUS) begin : bus
     localparam integer   WORDSPERLINE = (CACHE_ENABLED) ? `ICACHE_LINELENINBITS/`XLEN : 1;
     localparam integer   LINELEN = (CACHE_ENABLED) ? `ICACHE_LINELENINBITS : `XLEN;
     localparam integer   LOGWPL = (`DMEM == `MEM_CACHE) ? $clog2(WORDSPERLINE) : 1;
@@ -231,6 +232,8 @@ module ifu (
       assign {ICacheFetchLine, ICacheBusAdr, ICacheStallF, FinalInstrRawF} = '0;
       assign ICacheAccess = CacheableF; assign ICacheMiss = CacheableF;
     end
+  end else begin : nobus // block: bus
+    assign AllInstrRawF = FinalInstrRawF;
   end
   
   assign IFUCacheBusStallF = ICacheStallF | BusStall;

pipelined/src/lsu/lsu.sv

@@ -82,7 +82,6 @@ module lsu (
    input var                logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // *** this one especially has a large note attached to it in pmpchecker.
   );
 
-  localparam                CACHE_ENABLED = `DMEM == `MEM_CACHE;
   logic [`XLEN+1:0]         IEUAdrExtM;
   logic [`PA_BITS-1:0]      LSUPAdrM;
   logic                     DTLBMissM;
@@ -196,9 +195,9 @@ module lsu (
               .ReadDataWordM, .BusStall, .LSUBusWrite,.LSUBusRead, .BusCommittedM,
               .DCacheStallM, .DCacheCommittedM, .ByteMaskM,
               .DCacheMiss, .DCacheAccess);
-    assign SelUncachedAdr = '0; // value does not matter.
+  end 
-    assign ReadDataWordMuxM = ReadDataWordM;
+  if (`DBUS) begin : bus  
-  end else begin : bus  
+    localparam           CACHE_ENABLED = `DMEM == `MEM_CACHE;
     localparam integer   WORDSPERLINE = (CACHE_ENABLED) ? `DCACHE_LINELENINBITS/`XLEN : 1;
     localparam integer   LINELEN = (CACHE_ENABLED) ? `DCACHE_LINELENINBITS : `XLEN;
     localparam integer   LOGWPL = (CACHE_ENABLED) ? $clog2(WORDSPERLINE) : 1;
@@ -225,7 +224,6 @@ module lsu (
     mux2 #(`XLEN) LsuBushwdataMux(.d0(ReadDataWordM), .d1(FinalWriteDataM),
       .s(SelUncachedAdr), .y(LSUBusHWDATA));
     
-
     if(CACHE_ENABLED) begin : dcache
       cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
               .NUMWAYS(`DCACHE_NUMWAYS), .LOGWPL(LOGWPL), .WORDLEN(`XLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache(
@@ -243,6 +241,9 @@ module lsu (
       assign {ReadDataWordM, DCacheStallM, DCacheCommittedM, DCacheFetchLine, DCacheWriteLine} = '0;
       assign DCacheMiss = CacheableM; assign DCacheAccess = CacheableM;
     end
+  end else begin: nobus // block: bus
+    assign {LSUBusHWDATA, SelUncachedAdr} = '0; 
+    assign ReadDataWordMuxM = ReadDataWordM;
   end
 
   subwordread subwordread(.ReadDataWordMuxM, .LSUPAdrM(LSUPAdrM[2:0]),