diff --git a/bin/regression-wally b/bin/regression-wally
index 16286c60b..67cd4815b 100755
--- a/bin/regression-wally
+++ b/bin/regression-wally
@@ -233,6 +233,7 @@ bpredtests = [
 # list of tests not supported by ImperasDV yet that should be waived during lockstep testing
 lockstepwaivers = [
     "WALLY-q-01.S_ref.elf",     # Q extension is not supported by ImperasDV
+    "coverage_tlbMisaligned.elf",  # Issue 976: ImperasDV bug disagrees with Wally related to misaligned pages when PBMT makes page uncachable
     "WALLY-cbom-01.S_ref.elf" #,  # cbom extension is not supported by ImperasDV because there is no cache model in ImperasDV
 ]
 
@@ -542,7 +543,7 @@ def main():
              num_fail+=result.get(timeout=TIMEOUT_DUR)
            except TimeoutError:
              num_fail+=1
-             print(f"{bcolors.FAIL}%s_%s: Timeout - runtime exceeded %d seconds{bcolors.ENDC}" % (config.variant, config.name, TIMEOUT_DUR))
+             print(f"{bcolors.FAIL}%s: Timeout - runtime exceeded %d seconds{bcolors.ENDC}" % (config.cmd, TIMEOUT_DUR))
 
     # Coverage report
     if args.ccov:
diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv
index 24132ab93..2a4a6d668 100644
--- a/src/privileged/csrm.sv
+++ b/src/privileged/csrm.sv
@@ -171,7 +171,7 @@ module csrm  import cvw::*;  #(parameter cvw_t P) (
   flopenr #(P.XLEN) MEPCreg(clk, reset, WriteMEPCM, NextEPCM, MEPC_REGW); 
   flopenr #(P.XLEN) MCAUSEreg(clk, reset, WriteMCAUSEM, {NextCauseM[4], {(P.XLEN-5){1'b0}}, NextCauseM[3:0]}, MCAUSE_REGW);
   flopenr #(P.XLEN) MTVALreg(clk, reset, WriteMTVALM, NextMtvalM, MTVAL_REGW);
-  flopenr #(32)   MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], MCOUNTINHIBIT_REGW);
+  flopenr #(32)   MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, {CSRWriteValM[31:2], 1'b0, CSRWriteValM[0]}, MCOUNTINHIBIT_REGW);
   if (P.U_SUPPORTED) begin: mcounteren // MCOUNTEREN only exists when user mode is supported
     flopenr #(32)   MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], MCOUNTEREN_REGW);
   end else assign MCOUNTEREN_REGW = '0;
diff --git a/tests/coverage/WALLY-init-lib.h b/tests/coverage/WALLY-init-lib.h
index edf867240..b6b4f56b1 100644
--- a/tests/coverage/WALLY-init-lib.h
+++ b/tests/coverage/WALLY-init-lib.h
@@ -127,6 +127,17 @@ write_tohost:
 
 self_loop:
     j self_loop         # wait
+
+// utility routines
+
+# put a 1 in msb of a0 (position XLEN-1); works for both RV32 and RV64
+setmsb:
+    li a0, 0x80000000   # 1 in bit 31
+    slli a1, a0, 1      # check if register is wider than 31 bits
+    beqz a1, 1f         # yes, a0 has 1 in bit 31
+    slli a0, a0, 16     # no: shift a0 to have 1 inn bit 63
+    slli a0, a0, 16     # use two shifts of 16 bits each to be compatible with compiling either RV32 or 64
+    ret                 # return to calller
     
 .section .tohost 
 tohost:                 # write to HTIF
@@ -139,6 +150,9 @@ begin_signature:
     .fill 6*(XLEN/32),4,0xdeadbeef    # 
 end_signature:
 
+scratch:
+    .fill 4,4,0x0
+
 # Initialize stack with room for 512 bytes
 .bss
     .space 512