diff --git a/pipelined/src/fpu/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrtpostproc.sv
index 1b709a320..550c6ee53 100644
--- a/pipelined/src/fpu/fdivsqrtpostproc.sv
+++ b/pipelined/src/fpu/fdivsqrtpostproc.sv
@@ -77,7 +77,5 @@ module fdivsqrtpostproc(
     else  
       if(NegSticky) QmM = FirstSM[`DIVb-(`RADIX/4):0];
       else          QmM = FirstS[`DIVb-(`RADIX/4):0];
-      //if(NegSticky) QmM = FirstQM[`DIVb-(`RADIX/4):0];
-      //else          QmM = FirstQ[`DIVb-(`RADIX/4):0];
 
 endmodule
\ No newline at end of file