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https://github.com/openhwgroup/cvw
synced 2025-02-03 02:05:21 +00:00
Restored instead of in testbench because prevents coverage analysis. Improved FPU coverage
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@ -237,11 +237,10 @@ module fctrl import cvw::*; #(parameter cvw_t P) (
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5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0; // fcvt.l.q q->l
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5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0; // fcvt.lu.q q->lu
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endcase
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// coverage on
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// coverage off
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// Not covered in testing because rv64gc is not RV64Q or RV32D
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7'b1011001: if (P.ZFA_SUPPORTED & P.XLEN == 32 & P.D_SUPPORTED & Funct3D == 3'b000)
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ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0; // fmvp.d.x (Zfa) *** untested, controls could be wrong
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// Not covered in testing because rv64gc does not support quad precision
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// coverage off
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7'b1011011: if (P.ZFA_SUPPORTED & P.XLEN == 64 & P.Q_SUPPORTED & Funct3D == 3'b000)
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ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0; // fmvp.q.x (Zfa)
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// coverage on
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@ -310,7 +310,7 @@ module testbench;
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if (TEST == "coremark")
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if (dut.core.priv.priv.EcallFaultM) begin
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$display("Benchmark: coremark is done.");
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$finish;
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$stop;
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end
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if(Validate) begin
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if (TEST == "embench") begin
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@ -347,7 +347,7 @@ module testbench;
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if (test == tests.size()) begin
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if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
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else $display("FAIL: %d test programs had errors", totalerrors);
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$finish;
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$stop; // if this is changed to $finish, wally-batch.do does not go to the next step to run coverage
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end
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end
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end
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@ -631,7 +631,7 @@ module testbench;
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errors = errors+1;
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$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h",
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TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
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$finish;
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$stop; // if this is changed to $finish, wally-batch.do does not get to the next step to run coverage
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end
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end
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if (errors) $display("%s failed with %d errors. :(", TestName, errors);
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@ -40,12 +40,24 @@ main:
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# zfa instructions (because Zfa tests aren't running yet)
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fli.d fs0, 16
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fcvtmod.w.d t0, fs0, rtz
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fminm.d fs1, fs0, fs0
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fmaxm.d fs1, fs0, fs0
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fround.d fs1, fs0
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# fminm.d fs1, fs0, fs0
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# fmaxm.d fs1, fs0, fs0
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# fltq.d t0, fs1, ft0
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# fleq.d t0, fs1, ft0
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fcvt.d.q fs1, fs0
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fcvt.h.q fs1, fs0
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fcvt.s.q fs1, fs0
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# round for now because these tests are excluded from Zfa until rounding is implemented
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fround.s fs1, fs0
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froundnx.s fs1, fs0
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fround.d fs1, fs0
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froundnx.d fs1, fs0
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fltq.d t0, fs1, ft0
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fleq.d t0, fs1, ft0
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fround.h fs1, fs0
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froundnx.h fs1, fs0
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fround.s fs1, fs0
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froundnx.s fs1, fs0
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fmvp.d.x
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#Result Sign Test Coverage
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la t0, TestData2
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