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This commit is contained in:
cturek 2022-09-03 22:09:55 +00:00
parent 648a3aae09
commit e709ad4145
2 changed files with 6 additions and 6 deletions
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4
pipelined/srt/srt.sv
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@ -163,7 +163,7 @@ module srtpreproc (
assign D = {4'b0001, Int ? PreprocB : PreprocY}; assign D = {4'b0001, Int ? PreprocB : PreprocY};
// Integer exponent and sign calculations // Integer exponent and sign calculations
assign intExp = zeroCntB - zeroCntA - Mod + (PreprocA >= PreprocB); assign intExp = zeroCntB - zeroCntA + (PreprocA >= PreprocB);
assign intSign = Signed & (SrcA[`XLEN - 1] ^ SrcB[`XLEN - 1]); assign intSign = Signed & (SrcA[`XLEN - 1] ^ SrcB[`XLEN - 1]);
// Number of cycles of divider // Number of cycles of divider
@ -462,7 +462,7 @@ module srtpostproc(
end end
assign floatRes = S[`DIVLEN] ? S[`DIVLEN:1] : S[`DIVLEN-1:0]; assign floatRes = S[`DIVLEN] ? S[`DIVLEN:1] : S[`DIVLEN-1:0];
assign intRes = intS[`DIVLEN] ? intS[`DIVLEN:1] : intS[`DIVLEN-1:0]; assign intRes = intS[`DIVLEN] ? intS[`DIVLEN:1] : intS[`DIVLEN-1:0];
assign shiftRem = (intRem >> (zeroCntD)); assign shiftRem = (intRem >> (zeroCntD+1));
always_comb begin always_comb begin
if (Int) begin if (Int) begin
if (Mod) Result = shiftRem[`DIVLEN-1:0]; if (Mod) Result = shiftRem[`DIVLEN-1:0];

8
pipelined/srt/testbench.sv
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@ -70,9 +70,9 @@ module testbench;
integer testnum, errors; integer testnum, errors;
// Equip Int, Sqrt, or IntMod test // Equip Int, Sqrt, or IntMod test
assign Int = 1'b0; assign Int = 1'b1;
assign Mod = 1'b0; assign Mod = 1'b1;
assign Sqrt = 1'b1; assign Sqrt = 1'b0;
// Divider // Divider
srt srt(.clk, .Start(req), srt srt(.clk, .Start(req),
@ -101,7 +101,7 @@ module testbench;
begin begin
testnum = 0; testnum = 0;
errors = 0; errors = 0;
$readmemh ("sqrttestvectors", Tests); $readmemh ("modtestvectors", Tests);
Vec = Tests[testnum]; Vec = Tests[testnum];
a = Vec[`mema]; a = Vec[`mema];
{asign, aExp, afrac} = a; {asign, aExp, afrac} = a;