From e6ffde61bd9dfcc3d079fbf57c148d2d06b7fb28 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Tue, 5 Mar 2024 08:54:50 -0600 Subject: [PATCH] fix module name to lc --- src/ieu/aes_common/aes_inv_mixcolumns.sv | 2 +- src/ieu/aes_common/aes_inv_sbox.sv | 2 +- src/ieu/aes_common/aes_inv_sbox_word.sv | 10 +++++----- src/ieu/aes_common/aes_inv_shiftrow.sv | 5 ++--- src/ieu/aes_common/aes_mixcolumns.sv | 5 ++--- src/ieu/aes_common/aes_sbox.sv | 2 +- src/ieu/aes_common/aes_sbox_word.sv | 10 +++++----- src/ieu/aes_common/aes_shiftrow.sv | 6 +++--- 8 files changed, 20 insertions(+), 22 deletions(-) diff --git a/src/ieu/aes_common/aes_inv_mixcolumns.sv b/src/ieu/aes_common/aes_inv_mixcolumns.sv index 7588454aa..670765349 100644 --- a/src/ieu/aes_common/aes_inv_mixcolumns.sv +++ b/src/ieu/aes_common/aes_inv_mixcolumns.sv @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_Inv_Mixcolumns (input logic [31:0] word, output logic [31:0] mixed_word); +module aes_inv_mixcolumns (input logic [31:0] word, output logic [31:0] mixed_word); // Instantiate Internal Logic logic [7:0] b0, b1, b2, b3; diff --git a/src/ieu/aes_common/aes_inv_sbox.sv b/src/ieu/aes_common/aes_inv_sbox.sv index fd24a39c5..a364f75db 100644 --- a/src/ieu/aes_common/aes_inv_sbox.sv +++ b/src/ieu/aes_common/aes_inv_sbox.sv @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_Inv_Sbox(input logic [7:0] in, +module aes_inv_sbox(input logic [7:0] in, output logic [7:0] out); always_comb diff --git a/src/ieu/aes_common/aes_inv_sbox_word.sv b/src/ieu/aes_common/aes_inv_sbox_word.sv index a96771a07..d2b18d7db 100644 --- a/src/ieu/aes_common/aes_inv_sbox_word.sv +++ b/src/ieu/aes_common/aes_inv_sbox_word.sv @@ -25,16 +25,16 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_Inv_Sbox_Word(input logic [31:0] in, +module aes_inv_sbox_word(input logic [31:0] in, output logic [31:0] out); // Declare the SBOX for (least significant) byte 0 of the input - aes_Inv_Sbox sbox_b0(.in(in[7:0]), .out(out[7:0])); + aes_inv_sbox sbox_b0(.in(in[7:0]), .out(out[7:0])); // Declare the SBOX for byte 1 of the input - aes_Inv_Sbox sbox_b1(.in(in[15:8]), .out(out[15:8])); + aes_inv_sbox sbox_b1(.in(in[15:8]), .out(out[15:8])); // Declare the SBOX for byte 2 of the input - aes_Inv_Sbox sbox_b2(.in(in[23:16]), .out(out[23:16])); + aes_inv_sbox sbox_b2(.in(in[23:16]), .out(out[23:16])); // Declare the SBOX for byte 3 of the input - aes_Inv_Sbox sbox_b3(.in(in[31:24]), .out(out[31:24])); + aes_inv_sbox sbox_b3(.in(in[31:24]), .out(out[31:24])); endmodule diff --git a/src/ieu/aes_common/aes_inv_shiftrow.sv b/src/ieu/aes_common/aes_inv_shiftrow.sv index 1ca9390d1..3f04fa225 100644 --- a/src/ieu/aes_common/aes_inv_shiftrow.sv +++ b/src/ieu/aes_common/aes_inv_shiftrow.sv @@ -25,9 +25,8 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_Inv_Shiftrow ( - input logic [127:0] DataIn, - output logic [127:0] DataOut); +module aes_inv_shiftrow(input logic [127:0] DataIn, + output logic [127:0] DataOut); assign DataOut = {DataIn[31:24], DataIn[55:48], DataIn[79:72], DataIn[103:96], DataIn[127:120], DataIn[23:16], DataIn[47:40], DataIn[71:64], diff --git a/src/ieu/aes_common/aes_mixcolumns.sv b/src/ieu/aes_common/aes_mixcolumns.sv index f1206a7a9..72a610833 100644 --- a/src/ieu/aes_common/aes_mixcolumns.sv +++ b/src/ieu/aes_common/aes_mixcolumns.sv @@ -26,9 +26,8 @@ //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_Mixcolumns ( - input logic [31:0] in, - output logic [31:0] out); +module aes_mixcolumns (input logic [31:0] in, + output logic [31:0] out); logic [7:0] in0, in1, in2, in3, out0, out1, out2, out3, t0, t1, t2, t3, temp; logic [15:0] rrot8_1, rrot8_2; diff --git a/src/ieu/aes_common/aes_sbox.sv b/src/ieu/aes_common/aes_sbox.sv index 12e32dfd6..29521b90e 100644 --- a/src/ieu/aes_common/aes_sbox.sv +++ b/src/ieu/aes_common/aes_sbox.sv @@ -25,7 +25,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_Sbox(input logic [7:0] in, +module aes_sbox(input logic [7:0] in, output logic [7:0] out); // case statement to lookup the value in the rijndael table diff --git a/src/ieu/aes_common/aes_sbox_word.sv b/src/ieu/aes_common/aes_sbox_word.sv index 2111e4eb1..17312585b 100644 --- a/src/ieu/aes_common/aes_sbox_word.sv +++ b/src/ieu/aes_common/aes_sbox_word.sv @@ -25,16 +25,16 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_Sbox_Word(input logic [31:0] in, +module aes_sbox_word(input logic [31:0] in, output logic [31:0] out); // Declare the SBOX for (least significant) byte 0 of the input - aes_Sbox sbox_b0(.in(in[7:0]), .out(out[7:0])); + aes_sbox sbox_b0(.in(in[7:0]), .out(out[7:0])); // Declare the SBOX for byte 1 of the input - aes_Sbox sbox_b1(.in(in[15:8]), .out(out[15:8])); + aes_sbox sbox_b1(.in(in[15:8]), .out(out[15:8])); // Declare the SBOX for byte 2 of the input - aes_Sbox sbox_b2(.in(in[23:16]), .out(out[23:16])); + aes_sbox sbox_b2(.in(in[23:16]), .out(out[23:16])); // Declare the SBOX for byte 3 of the input - aes_Sbox sbox_b3(.in(in[31:24]), .out(out[31:24])); + aes_sbox sbox_b3(.in(in[31:24]), .out(out[31:24])); endmodule diff --git a/src/ieu/aes_common/aes_shiftrow.sv b/src/ieu/aes_common/aes_shiftrow.sv index 0de15f2ac..991b49559 100644 --- a/src/ieu/aes_common/aes_shiftrow.sv +++ b/src/ieu/aes_common/aes_shiftrow.sv @@ -25,9 +25,9 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module aes_Shiftrow ( - input logic [127:0] DataIn, - output logic [127:0] DataOut); +module aes_shiftrow + (input logic [127:0] DataIn, + output logic [127:0] DataOut); assign DataOut = {DataIn[95:88], DataIn[55:48], DataIn[15:8], DataIn[103:96], DataIn[63:56], DataIn[23:16], DataIn[111:104], DataIn[71:64],