From 9a5023a17e28fa26ec43326d46372fd598a6511d Mon Sep 17 00:00:00 2001 From: James Stine Date: Thu, 2 Feb 2023 13:28:18 -0600 Subject: [PATCH 1/3] Modify generic/mem for rv32gc ram2 --- pipelined/src/generic/mem/ram2p1r1wbe.sv | 12 +++++ .../src/generic/mem/ram2p1r1wbe_1024x36.sv | 48 +++++++++++++++++++ .../src/generic/mem/ram2p1r1wbe_1024x68.sv | 2 +- pipelined/src/generic/mem/rom1p1r.sv | 5 +- 4 files changed, 65 insertions(+), 2 deletions(-) create mode 100755 pipelined/src/generic/mem/ram2p1r1wbe_1024x36.sv diff --git a/pipelined/src/generic/mem/ram2p1r1wbe.sv b/pipelined/src/generic/mem/ram2p1r1wbe.sv index 3c93ce868..08c232bba 100644 --- a/pipelined/src/generic/mem/ram2p1r1wbe.sv +++ b/pipelined/src/generic/mem/ram2p1r1wbe.sv @@ -64,6 +64,18 @@ module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) ( .QA(rd1), .QB()); + end if (`USE_SRAM == 1 && WIDTH == 36 && DEPTH == 1024) begin + + ram2p1r1wbe_1024x36 memory1(.CLKA(clk), .CLKB(clk), + .CEBA(~ce1), .CEBB(~ce2), + .WEBA('0), .WEBB(~we2), + .AA(ra1), .AB(wa2), + .DA('0), + .DB(wd2), + .BWEBA('0), .BWEBB('1), + .QA(rd1), + .QB()); + end else if (`USE_SRAM == 1 && WIDTH == 2 && DEPTH == 1024) begin logic [SRAMWIDTH-1:0] SRAMReadData; diff --git a/pipelined/src/generic/mem/ram2p1r1wbe_1024x36.sv b/pipelined/src/generic/mem/ram2p1r1wbe_1024x36.sv new file mode 100755 index 000000000..0aad7db4a --- /dev/null +++ b/pipelined/src/generic/mem/ram2p1r1wbe_1024x36.sv @@ -0,0 +1,48 @@ +/////////////////////////////////////////// +// ram2p1rwbe_1024x36.sv +// +// Written: james.stine@okstate.edu 2 February 2023 +// Modified: +// +// Purpose: RAM wrapper for instantiating RAM IP +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module ram2p1r1wbe_1024x36( + input logic CLKA, + input logic CLKB, + input logic CEBA, + input logic CEBB, + input logic WEBA, + input logic WEBB, + input logic [9:0] AA, + input logic [9:0] AB, + input logic [35:0] DA, + input logic [35:0] DB, + input logic [35:0] BWEBA, + input logic [35:0] BWEBB, + output logic [35:0] QA, + output logic [35:0] QB +); + + // replace "generic1024x36RAM" with "TSDN..1024X36.." module from your memory vendor + generic1024x36RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, + .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + +endmodule diff --git a/pipelined/src/generic/mem/ram2p1r1wbe_1024x68.sv b/pipelined/src/generic/mem/ram2p1r1wbe_1024x68.sv index 11eacd5ae..e6a6b6257 100755 --- a/pipelined/src/generic/mem/ram2p1r1wbe_1024x68.sv +++ b/pipelined/src/generic/mem/ram2p1r1wbe_1024x68.sv @@ -41,7 +41,7 @@ module ram2p1r1wbe_1024x68( output logic [67:0] QB ); - // replace "generic1024x69RAM" with "TSDN..1024X69.." module from your memory vendor + // replace "generic1024x68RAM" with "TSDN..1024X68.." module from your memory vendor generic1024x68RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); diff --git a/pipelined/src/generic/mem/rom1p1r.sv b/pipelined/src/generic/mem/rom1p1r.sv index 4669cadb8..64cb9224b 100644 --- a/pipelined/src/generic/mem/rom1p1r.sv +++ b/pipelined/src/generic/mem/rom1p1r.sv @@ -38,9 +38,12 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, // Core Memory logic [DATA_WIDTH-1:0] ROM [(2**ADDR_WIDTH)-1:0]; - if (`USE_SRAM == 1 && DATA_WIDTH == 64 && `XLEN == 64) begin + if (`USE_SRAM == 1 && DATA_WIDTH == 64) begin rom1p1r_128x64 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout)); + end if (`USE_SRAM == 1 && DATA_WIDTH == 32) begin + rom1p1r_128x32 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout)); + end else begin always @ (posedge clk) begin if(ce) dout <= ROM[addr]; From 924e55325c33a12cc7e17a528b5150403bb31e60 Mon Sep 17 00:00:00 2001 From: James Stine Date: Thu, 2 Feb 2023 13:54:25 -0600 Subject: [PATCH 2/3] Forgot 1p ram for rv32gc : cache data 64x128 and cache tags 64x22 --- pipelined/src/generic/mem/ram1p1rwbe.sv | 20 ++++++++++ pipelined/src/generic/mem/ram1p1rwbe_64x22.sv | 40 +++++++++++++++++++ 2 files changed, 60 insertions(+) create mode 100755 pipelined/src/generic/mem/ram1p1rwbe_64x22.sv diff --git a/pipelined/src/generic/mem/ram1p1rwbe.sv b/pipelined/src/generic/mem/ram1p1rwbe.sv index 028f928cd..e33e708a3 100644 --- a/pipelined/src/generic/mem/ram1p1rwbe.sv +++ b/pipelined/src/generic/mem/ram1p1rwbe.sv @@ -68,6 +68,26 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) ( ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we), .A(addr), .D(din), .BWEB(~BitWriteMask), .Q(dout)); + + end if (`USE_SRAM == 1 && WIDTH == 128 && DEPTH == 32) begin + genvar index; + // 64 x 128-bit SRAM + logic [WIDTH-1:0] BitWriteMask; + for (index=0; index < WIDTH; index++) + assign BitWriteMask[index] = bwe[index/8]; + TS1N28HPCPSVTB64X128M4SW sram1A (.CLK(clk), .CEB(~ce), .WEB(~we), + .A(addr), .D(din), + .BWEB(~BitWriteMask), .Q(dout)); + + end else if (`USE_SRAM == 1 && WIDTH == 22 && DEPTH == 32) begin + genvar index; + // 64 x 22-bit SRAM + logic [WIDTH-1:0] BitWriteMask; + for (index=0; index < WIDTH; index++) + assign BitWriteMask[index] = bwe[index/8]; + ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we), + .A(addr), .D(din), + .BWEB(~BitWriteMask), .Q(dout)); // *************************************************************************** // READ first SRAM model diff --git a/pipelined/src/generic/mem/ram1p1rwbe_64x22.sv b/pipelined/src/generic/mem/ram1p1rwbe_64x22.sv new file mode 100755 index 000000000..84c8d1b75 --- /dev/null +++ b/pipelined/src/generic/mem/ram1p1rwbe_64x22.sv @@ -0,0 +1,40 @@ +/////////////////////////////////////////// +// ram1p1rwbe_64x22.sv +// +// Written: james.stine@okstate.edu 2 Feburary 2023 +// Modified: +// +// Purpose: RAM wrapper for instantiating RAM IP +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module ram1p1rwbe_64x22( + input logic CLK, + input logic CEB, + input logic WEB, + input logic [5:0] A, + input logic [127:0] D, + input logic [127:0] BWEB, + output logic [127:0] Q +); + + // replace "generic64x22RAM" with "TS1N..64X22.." module from your memory vendor + generic64x22RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q); + +endmodule From 3531afa5cfa46a566db93dd0a41bd61bb993329a Mon Sep 17 00:00:00 2001 From: David Harris <74973295+davidharrishmc@users.noreply.github.com> Date: Thu, 2 Feb 2023 12:59:28 -0800 Subject: [PATCH 3/3] Update README.md --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 12d7fe1f6..1fec92868 100644 --- a/README.md +++ b/README.md @@ -5,7 +5,7 @@ Wally is a 5-stage pipelined processor configurable to support all the standard ![Wally block diagram](wallyriscvTopAll.png) -Wally is described in a textbook, RISC-V System-on-Chip Design, by Harris, Stine, Thompson, and Harris. Users should follow the setup instructions below. A system administrator must install CAD tools using the directions further down. +Wally is described in an upcoming textbook, *RISC-V System-on-Chip Design*, by Harris, Stine, Thompson, and Harris. Users should follow the setup instructions below. A system administrator must install CAD tools using the directions further down. # New User Setup