From e6661ea26adf34ace34bd2cddd5a957abdf0806c Mon Sep 17 00:00:00 2001
From: Teo Ene <teodor@rivendell.ecen.okstate.edu>
Date: Wed, 17 Mar 2021 15:07:02 -0500
Subject: [PATCH] fix to last commit

---
 wally-pipelined/regression/wally-coremark_bare.do | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/wally-pipelined/regression/wally-coremark_bare.do b/wally-pipelined/regression/wally-coremark_bare.do
index d6c242aa1..a933a8445 100644
--- a/wally-pipelined/regression/wally-coremark_bare.do
+++ b/wally-pipelined/regression/wally-coremark_bare.do
@@ -28,7 +28,7 @@ vlib work
 # because vsim will run vopt
 
 # default to config/coremark, but allow this to be overridden at the command line.  For example:
-vlog +incdir+../config/coremark_bare ../testbench/testbench-coremark_bare.sv ../src/*/*.sv -suppress 2583
+vlog +incdir+../config/coremark_bare ../testbench/testbench-coremark_bare.sv ../testbench/function_radix.sv ../src/*/*.sv -suppress 2583
 
 # start and run simulation
 # remove +acc flag for faster sim during regressions if there is no need to access internal signals