diff --git a/src/ieu/aes/aes32d.sv b/src/ieu/aes/aes32d.sv index e3eb61cec..f761b5060 100644 --- a/src/ieu/aes/aes32d.sv +++ b/src/ieu/aes/aes32d.sv @@ -34,8 +34,8 @@ module aes32d( logic [7:0] SboxOut; logic [31:0] so, mixed; - aesinvsbox8 inv_sbox(SboxIn, SboxOut); // Apply inverse sbox to si - assign so = {24'h0, SboxOut}; // Pad output of inverse substitution box - aesinvmixcolumns32 mix(so, mixed); // Run so through the mixword AES function + aesinvsbox8 inv_sbox(SboxIn, SboxOut); // Apply inverse sbox to si + aesinvmixcolumns8 mix(SboxOut, mixed); // Run so through the InvMixColumns AES function + assign so = {24'h0, SboxOut}; // Pad output of inverse substitution box mux2 #(32) rmux(mixed, so, finalround, result); // on final round, skip mixcolumns endmodule diff --git a/src/ieu/aes/aes32e.sv b/src/ieu/aes/aes32e.sv index ca00afdd3..ab28db196 100644 --- a/src/ieu/aes/aes32e.sv +++ b/src/ieu/aes/aes32e.sv @@ -34,8 +34,8 @@ module aes32e( logic [7:0] SboxOut; logic [31:0] so, mixed; - aessbox8 sbox(SboxIn, SboxOut); // Substitute - assign so = {24'h0, SboxOut}; // Pad sbox output - aesmixcolumns32 mwd(so, mixed); // Mix Word using aesmixword component - mux2 #(32) rmux(mixed, so, finalround, result); // on final round, skip mixcolumns + aessbox8 sbox(SboxIn, SboxOut); // Substitute + assign so = {24'h0, SboxOut}; // Pad sbox output + aesmixcolumns32 mb(so, mixed); // Mix using MixColumns component + mux2 #(32) rmux(mixed, so, finalround, result); // on final round, skip MixColumns endmodule diff --git a/src/ieu/aes/aes64d.sv b/src/ieu/aes/aes64d.sv index 96355a566..a9e6feb75 100644 --- a/src/ieu/aes/aes64d.sv +++ b/src/ieu/aes/aes64d.sv @@ -42,7 +42,7 @@ module aes64d( mux2 #(64) mixcolmux(SboxOut, rs1, aes64im, MixcolIn); - // Apply inverse mixword to sbox outputs + // Apply inverse MixColumns to sbox outputs aesinvmixcolumns32 invmw0(MixcolIn[31:0], MixcolOut[31:0]); aesinvmixcolumns32 invmw1(MixcolIn[63:32], MixcolOut[63:32]); diff --git a/src/ieu/aes/aes64e.sv b/src/ieu/aes/aes64e.sv index b37d8787c..7435f4327 100644 --- a/src/ieu/aes/aes64e.sv +++ b/src/ieu/aes/aes64e.sv @@ -46,7 +46,7 @@ module aes64e( aessbox32 sbox1(ShiftRowOut[63:32], SboxOut[63:32]); // instantiate second sbox - // Apply mix columns operations + // Apply MixColumns operations aesmixcolumns32 mw0(SboxOut[31:0], MixcolOut[31:0]); aesmixcolumns32 mw1(SboxOut[63:32], MixcolOut[63:32]); diff --git a/src/ieu/aes/aesinvmixcolumns8.sv b/src/ieu/aes/aesinvmixcolumns8.sv new file mode 100644 index 000000000..134ceeb11 --- /dev/null +++ b/src/ieu/aes/aesinvmixcolumns8.sv @@ -0,0 +1,47 @@ +/////////////////////////////////////////// +// aesinvmixcolumns8.sv +// +// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu +// Created: 05 March 2024 +// +// Purpose: AES Inverted Mix Column Function for use with AES +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module aesinvmixcolumns8( + input logic [7:0] a, + output logic [31:0] y +); + + logic [10:0] t, x0, x1, x2, x3; + + // aes32d operates on shifted versions of the input + assign t = {a, 3'b0} ^ {3'b0, a}; + assign x0 = {a, 3'b0} ^ {1'b0, a, 2'b0} ^ {2'b0, a, 1'b0}; + assign x1 = t; + assign x2 = t ^ {1'b0, a, 2'b0}; + assign x3 = t ^ {2'b0, a, 1'b0}; + + galoismultinverse8 gm0 (x0, y[7:0]); + galoismultinverse8 gm1 (x1, y[15:8]); + galoismultinverse8 gm2 (x2, y[23:16]); + galoismultinverse8 gm3 (x3, y[31:24]); + + endmodule diff --git a/src/ieu/aes/aesmixcolumns8.sv b/src/ieu/aes/aesmixcolumns8.sv new file mode 100644 index 000000000..66ab6534f --- /dev/null +++ b/src/ieu/aes/aesmixcolumns8.sv @@ -0,0 +1,39 @@ +/////////////////////////////////////////// +// aesmixcolumns8.sv +// +// Written: ryan.swann@okstate.edu, james.stine@okstate.edu, David_Harris@hmc.edu +// Created: 20 February 2024 +// +// Purpose: Galois field operation to byte in an individual 32-bit word +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// https://github.com/openhwgroup/cvw +// +// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + + +module aesmixcolumns8( + input logic [7:0] a, + output logic [31:0] y +); + + logic [7:0] xa, xapa; + + galoismultforward8 gm(a, xa); // xa + assign xapa = a ^ xa; // a ^ xa + assign y = {xapa, a, a, xa}; +endmodule