From e6077f1f162a5068047136ff8966489feffcdcdc Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 24 Aug 2022 17:03:22 -0700 Subject: [PATCH] Added ROM module and moved memories into generic/mem --- .../src/generic/{flop => mem}/bram1p1rw.sv | 0 .../generic/{flop => mem}/bram1p1rw_64x128.sv | 0 .../{flop => mem}/bram1p1rw_64x128wrap.sv | 0 .../src/generic/mem/bram1p1rw_64x44wrap.sv | 36 +++++++++ .../src/generic/{flop => mem}/bram2p1r1w.sv | 0 pipelined/src/generic/mem/brom1p1r.sv | 52 +++++++++++++ pipelined/src/uncore/ram_ahb.sv | 76 +++++++++++++++++++ pipelined/src/uncore/{ram.sv => rom_ahb.sv} | 6 +- pipelined/src/uncore/uncore.sv | 7 +- 9 files changed, 170 insertions(+), 7 deletions(-) rename pipelined/src/generic/{flop => mem}/bram1p1rw.sv (100%) rename pipelined/src/generic/{flop => mem}/bram1p1rw_64x128.sv (100%) rename pipelined/src/generic/{flop => mem}/bram1p1rw_64x128wrap.sv (100%) create mode 100644 pipelined/src/generic/mem/bram1p1rw_64x44wrap.sv rename pipelined/src/generic/{flop => mem}/bram2p1r1w.sv (100%) create mode 100644 pipelined/src/generic/mem/brom1p1r.sv create mode 100644 pipelined/src/uncore/ram_ahb.sv rename pipelined/src/uncore/{ram.sv => rom_ahb.sv} (96%) diff --git a/pipelined/src/generic/flop/bram1p1rw.sv b/pipelined/src/generic/mem/bram1p1rw.sv similarity index 100% rename from pipelined/src/generic/flop/bram1p1rw.sv rename to pipelined/src/generic/mem/bram1p1rw.sv diff --git a/pipelined/src/generic/flop/bram1p1rw_64x128.sv b/pipelined/src/generic/mem/bram1p1rw_64x128.sv similarity index 100% rename from pipelined/src/generic/flop/bram1p1rw_64x128.sv rename to pipelined/src/generic/mem/bram1p1rw_64x128.sv diff --git a/pipelined/src/generic/flop/bram1p1rw_64x128wrap.sv b/pipelined/src/generic/mem/bram1p1rw_64x128wrap.sv similarity index 100% rename from pipelined/src/generic/flop/bram1p1rw_64x128wrap.sv rename to pipelined/src/generic/mem/bram1p1rw_64x128wrap.sv diff --git a/pipelined/src/generic/mem/bram1p1rw_64x44wrap.sv b/pipelined/src/generic/mem/bram1p1rw_64x44wrap.sv new file mode 100644 index 000000000..89b77e8be --- /dev/null +++ b/pipelined/src/generic/mem/bram1p1rw_64x44wrap.sv @@ -0,0 +1,36 @@ +module bram1p1rw_64x44wrap + #( + //-------------------------------------------------------------------------- + parameter NUM_COL = 11, + parameter COL_WIDTH = 4, + parameter ADDR_WIDTH = 6, + // Addr Width in bits : 2 *ADDR_WIDTH = RAM Depth + parameter DATA_WIDTH = NUM_COL*COL_WIDTH // Data Width in bits + //---------------------------------------------------------------------- + ) ( + input logic clk, + input logic we, + input logic [NUM_COL-1:0] bwe, + input logic [ADDR_WIDTH-1:0] addr, + output logic [DATA_WIDTH-1:0] dout, + input logic [DATA_WIDTH-1:0] din + ); + + + logic we2; + logic [NUM_COL-1:0] bwe2; + logic [ADDR_WIDTH-1:0] addr2; + logic [DATA_WIDTH-1:0] dout2; + logic [DATA_WIDTH-1:0] din2; + + always_ff @(posedge clk) begin + we2 <= we; + bwe2 <= bwe; + addr2 <= addr; + din2 <= din; + dout2 <= dout; + end + + bram1p1rw_64x128 #(NUM_COL, COL_WIDTH, ADDR_WIDTH, DATA_WIDTH) dut(clk, we2, bwe2, addr2, dout, din2); + +endmodule diff --git a/pipelined/src/generic/flop/bram2p1r1w.sv b/pipelined/src/generic/mem/bram2p1r1w.sv similarity index 100% rename from pipelined/src/generic/flop/bram2p1r1w.sv rename to pipelined/src/generic/mem/bram2p1r1w.sv diff --git a/pipelined/src/generic/mem/brom1p1r.sv b/pipelined/src/generic/mem/brom1p1r.sv new file mode 100644 index 000000000..762e82f62 --- /dev/null +++ b/pipelined/src/generic/mem/brom1p1r.sv @@ -0,0 +1,52 @@ +/////////////////////////////////////////// +// brom1p1r +// +// Written: David_Harris@hmc.edu 8/24/22 +// +// Purpose: Single-ported ROM +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// This model actually works correctly with vivado. + +`include "wally-config.vh" + +module brom1p1r + #( + //-------------------------------------------------------------------------- + parameter ADDR_WIDTH = 8, + // Addr Width in bits : 2 **ADDR_WIDTH = RAM Depth + parameter DATA_WIDTH = 32 // Data Width in bits + //---------------------------------------------------------------------- + ) ( + input logic clk, + input logic [ADDR_WIDTH-1:0] addr, + output logic [DATA_WIDTH-1:0] dout + ); + // Core Memory + logic [DATA_WIDTH-1:0] ROM [(2**ADDR_WIDTH)-1:0]; + + always @ (posedge clk) begin + dout <= ROM[addr]; + end +endmodule // bytewrite_tdp_ram_rf diff --git a/pipelined/src/uncore/ram_ahb.sv b/pipelined/src/uncore/ram_ahb.sv new file mode 100644 index 000000000..1ede0696c --- /dev/null +++ b/pipelined/src/uncore/ram_ahb.sv @@ -0,0 +1,76 @@ +/////////////////////////////////////////// +// ram_ahb.sv +// +// Written: David_Harris@hmc.edu 9 January 2021 +// Modified: +// +// Purpose: On-chip RAM, external to core, with AHB interface +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module ram_ahb #(parameter BASE=0, RANGE = 65535) ( + input logic HCLK, HRESETn, + input logic HSELRam, + input logic [31:0] HADDR, + input logic HWRITE, + input logic HREADY, + input logic [1:0] HTRANS, + input logic [`XLEN-1:0] HWDATA, + input logic [`XLEN/8-1:0] HWSTRB, + output logic [`XLEN-1:0] HREADRam, + output logic HRESPRam, HREADYRam +); + + localparam ADDR_WIDTH = $clog2(RANGE/8); + localparam OFFSET = $clog2(`XLEN/8); + + logic [`XLEN/8-1:0] ByteMask; + logic [31:0] HADDRD, RamAddr; + logic initTrans; + logic memwrite, memwriteD, memread; + logic nextHREADYRam; + + // a new AHB transactions starts when HTRANS requests a transaction, + // the peripheral is selected, and the previous transaction is completing + assign initTrans = HREADY & HSELRam & HTRANS[1]; + assign memwrite = initTrans & HWRITE; + assign memread = initTrans & ~HWRITE; + + flopenr #(1) memwritereg(HCLK, ~HRESETn, HREADY, memwrite, memwriteD); + flopenr #(32) haddrreg(HCLK, ~HRESETn, HREADY, HADDR, HADDRD); + + // Stall on a read after a write because the RAM can't take both adddresses on the same cycle + assign nextHREADYRam = ~(memwriteD & memread); + flopr #(1) readyreg(HCLK, ~HRESETn, nextHREADYRam, HREADYRam); + assign HRESPRam = 0; // OK + + // On writes or during a wait state, use address delayed by one cycle to sync RamAddr with HWDATA or hold stalled address + mux2 #(32) adrmux(HADDR, HADDRD, memwriteD | ~HREADY, RamAddr); + + // single-ported RAM + bram1p1rw #(`XLEN/8, 8, ADDR_WIDTH) + memory(.clk(HCLK), .we(memwriteD), .bwe(HWSTRB), .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .dout(HREADRam), .din(HWDATA)); +endmodule + diff --git a/pipelined/src/uncore/ram.sv b/pipelined/src/uncore/rom_ahb.sv similarity index 96% rename from pipelined/src/uncore/ram.sv rename to pipelined/src/uncore/rom_ahb.sv index 5e7ab6b74..e6f3b336a 100644 --- a/pipelined/src/uncore/ram.sv +++ b/pipelined/src/uncore/rom_ahb.sv @@ -1,10 +1,10 @@ /////////////////////////////////////////// -// ram.sv +// rom_ahb.sv // // Written: David_Harris@hmc.edu 9 January 2021 // Modified: // -// Purpose: On-chip RAM, external to core +// Purpose: On-chip ROM, external to core // // A component of the Wally configurable RISC-V project. // @@ -30,7 +30,7 @@ `include "wally-config.vh" -module ram #(parameter BASE=0, RANGE = 65535) ( +module rom_ahb #(parameter BASE=0, RANGE = 65535) ( input logic HCLK, HRESETn, input logic HSELRam, input logic [31:0] HADDR, diff --git a/pipelined/src/uncore/uncore.sv b/pipelined/src/uncore/uncore.sv index 883ee8e69..8e1bdafdc 100644 --- a/pipelined/src/uncore/uncore.sv +++ b/pipelined/src/uncore/uncore.sv @@ -107,7 +107,7 @@ module uncore ( // on-chip RAM if (`UNCORE_RAM_SUPPORTED) begin : ram - ram #( + ram_ahb #( .BASE(`UNCORE_RAM_BASE), .RANGE(`UNCORE_RAM_RANGE)) ram ( .HCLK, .HRESETn, .HSELRam, .HADDR, @@ -116,9 +116,8 @@ module uncore ( .HRESPRam, .HREADYRam); end - // *** switch to new RAM - if (`BOOTROM_SUPPORTED) begin : bootrom - ram #(.BASE(`BOOTROM_BASE), .RANGE(`BOOTROM_RANGE)) + if (`BOOTROM_SUPPORTED) begin : bootrom + rom_ahb #(.BASE(`BOOTROM_BASE), .RANGE(`BOOTROM_RANGE)) bootrom( .HCLK, .HRESETn, .HSELRam(HSELBootRom), .HADDR,