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Converted wall.tcl to entirely project mode.

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This commit is contained in:
Rose Thompson 2024-08-27 14:15:58 -07:00
parent f20a1564fa
commit e5d3462a90
1 changed files with 7 additions and 8 deletions
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15
fpga/generator/wally.tcl
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@ -23,13 +23,13 @@ if {$boardName!="ArtyA7"} {
} }
# read package first # read package first
read_verilog -sv ../src/CopiedFiles_do_not_add_to_repo/cvw.sv add_files ../src/CopiedFiles_do_not_add_to_repo/cvw.sv
#read_verilog -sv ../src/wallypipelinedsocwrapper.sv #read_verilog -sv ../src/wallypipelinedsocwrapper.sv
# then read top level # then read top level
if {$board=="ArtyA7"} { if {$board=="ArtyA7"} {
read_verilog {../src/fpgaTopArtyA7.sv} add_files {../src/fpgaTopArtyA7.sv}
} else { } else {
read_verilog {../src/fpgaTop.sv} add_files {../src/fpgaTop.sv}
} }
# read in ip # read in ip
@ -45,9 +45,7 @@ if {$board=="ArtyA7"} {
} }
# read in all other rtl # read in all other rtl
read_verilog -sv [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv] add_files [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv]
# *** Once the sdc is updated to use ahb changes these to system verilog.
read_verilog [glob -type f ../../addins/ahbsdc/sdc/*.v]
set_property include_dirs {../src/CopiedFiles_do_not_add_to_repo/config ../../config/shared ../../addins/ahbsdc/sdc} [current_fileset] set_property include_dirs {../src/CopiedFiles_do_not_add_to_repo/config ../../config/shared ../../addins/ahbsdc/sdc} [current_fileset]
@ -64,7 +62,7 @@ exec rm -rf reports/*
report_compile_order -constraints > reports/compile_order.rpt report_compile_order -constraints > reports/compile_order.rpt
# this is elaboration not synthesis. # this is elaboration not synthesis.
synth_design -rtl -name rtl_1 -flatten_hierarchy none #synth_design -rtl -name rtl_1 -flatten_hierarchy none
# apply timing constraint after elaboration # apply timing constraint after elaboration
if {$board=="ArtyA7"} { if {$board=="ArtyA7"} {
@ -75,7 +73,6 @@ if {$board=="ArtyA7"} {
set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$boardSubName.xdc] set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$boardSubName.xdc]
} }
report_clocks -file reports/clocks.rpt
# Temp # Temp
set_param messaging.defaultLimit 100000 set_param messaging.defaultLimit 100000
@ -87,6 +84,8 @@ launch_runs synth_1 -jobs 16
wait_on_run synth_1 wait_on_run synth_1
open_run synth_1 open_run synth_1
report_clocks -file reports/clocks.rpt
check_timing -verbose -file reports/check_timing.rpt check_timing -verbose -file reports/check_timing.rpt
report_timing -max_paths 10 -nworst 10 -delay_type max -sort_by slack -file reports/timing_WORST_10.rpt report_timing -max_paths 10 -nworst 10 -delay_type max -sort_by slack -file reports/timing_WORST_10.rpt
report_timing -nworst 1 -delay_type max -sort_by group -file reports/timing.rpt report_timing -nworst 1 -delay_type max -sort_by group -file reports/timing.rpt