Moving interlockfsm changes to a temporary branch.

reduced complexity of cache mux controls.

pipelined/src/cache/cache.sv

@@ -52,7 +52,7 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
   input logic                   IgnoreRequestTLB,
   input logic                   TrapM, 
   input logic                   Cacheable,
-  input logic                   SelReplay,
+  input logic                   SelHPTW,
    // Bus fsm interface
   output logic [1:0]            CacheBusRW,
   input logic                   CacheBusAck,
@@ -123,7 +123,7 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
   // and FlushAdr when handling D$ flushes  
   mux3 #(SETLEN) AdrSelMux(
     .d0(NextAdr[SETTOP-1:OFFSETLEN]), .d1(PAdr[SETTOP-1:OFFSETLEN]), .d2(FlushAdr),
-    .s({SelFlush, (SelAdr | SelReplay)}), .y(RAdr));
+    .s({SelFlush, (SelAdr | SelHPTW)}), .y(RAdr));
 
   // Array of cache ways, along with victim, hit, dirty, and read merging logic
   cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN) 

pipelined/src/ifu/ifu.sv

@@ -226,7 +226,7 @@ module ifu (
              .CacheBusRW,
              .ReadDataWord(ICacheInstrF),
              .Cacheable(CacheableF),
-             .SelReplay('0),
+             .SelHPTW('0),
              .CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess),
              .ByteMask('0), .WordCount('0), .SelBusWord('0),
              .FinalWriteData('0),

pipelined/src/lsu/interlockfsm.sv

@@ -44,7 +44,6 @@ module interlockfsm(
   input logic       DCacheStallM,
 
   output logic      InterlockStall,
-  output logic      SelReplayMemE,
   output logic      SelHPTW,
   output logic      IgnoreRequestTLB);
 
@@ -53,7 +52,7 @@ module interlockfsm(
   logic             EitherTLBMiss;
   logic             EitherTLBWrite;
 
-  typedef enum      logic[2:0]  {STATE_T0_READY,
+  typedef enum      logic  {STATE_T0_READY,
 				                 STATE_T3_TLB_MISS} statetype;
 
   (* mark_debug = "true" *)	  statetype InterlockCurrState, InterlockNextState;
@@ -81,7 +80,6 @@ module interlockfsm(
 	  
    assign InterlockStall = (InterlockCurrState == STATE_T0_READY & EitherTLBMiss & ~TrapM) | 
                            (InterlockCurrState == STATE_T3_TLB_MISS);
-  assign SelReplayMemE = (InterlockCurrState == STATE_T3_TLB_MISS & EitherTLBWrite & ~PendingTLBMiss);
   assign SelHPTW = (InterlockCurrState == STATE_T3_TLB_MISS);
   assign IgnoreRequestTLB = (InterlockCurrState == STATE_T0_READY & EitherTLBMiss);
 endmodule

pipelined/src/lsu/lsu.sv

@@ -116,7 +116,6 @@ module lsu (
   logic [`LLEN-1:0]         IMAFWriteDataM;
   logic [`LLEN-1:0]         ReadDataM;
   logic [(`LLEN-1)/8:0]     ByteMaskM;
-  logic                     SelReplay;
   logic                     SelDTIM;
     
   flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
@@ -131,7 +130,7 @@ module lsu (
 
   if(`VIRTMEM_SUPPORTED) begin : VIRTMEM_SUPPORTED
     lsuvirtmem lsuvirtmem(.clk, .reset, .StallW, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF,
-      .DTLBMissM, .DTLBWriteM, .InstrDAPageFaultF, .DataDAPageFaultM, .SelReplay,
+      .DTLBMissM, .DTLBWriteM, .InstrDAPageFaultF, .DataDAPageFaultM,
       .TrapM, .DCacheStallM, .SATP_REGW, .PCF,
       .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW,
       .ReadDataM(ReadDataM[`XLEN-1:0]), .WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M,
@@ -247,7 +246,7 @@ module lsu (
         .clk, .reset, .CPUBusy, .SelBusWord, .RW(LSURWM), .Atomic(LSUAtomicM),
         .FlushCache(FlushDCacheM), .NextAdr(IEUAdrE[11:0]), .PAdr(PAdrM), 
         .ByteMask(ByteMaskM), .WordCount(WordCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]),
-        .FinalWriteData(LSUWriteDataM), .Cacheable(CacheableOrFlushCacheM), .SelReplay,
+        .FinalWriteData(LSUWriteDataM), .Cacheable(CacheableOrFlushCacheM), .SelHPTW,
         .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),
         .IgnoreRequestTLB, .TrapM, .CacheCommitted(DCacheCommittedM), 
         .CacheBusAdr(DCacheBusAdr), .ReadDataWord(DCacheReadDataWordM), 

pipelined/src/lsu/lsuvirtmen.sv

@@ -38,7 +38,6 @@ module lsuvirtmem(
   input logic                 DTLBMissM,
   output logic                DTLBWriteM,
   input logic                 InstrDAPageFaultF,
-  output logic                SelReplay,
   input logic                 DataDAPageFaultM,
   input logic                 TrapM,
   input logic                 DCacheStallM,
@@ -72,7 +71,6 @@ module lsuvirtmem(
   logic [`XLEN+1:0]           HPTWAdrExt;
   logic [1:0]                 HPTWRW;
   logic [2:0]                 HPTWSize;
-  logic                       SelReplayMemE;
   logic                       ITLBMissOrDAFaultF, ITLBMissOrDAFaultNoTrapF;
   logic                       DTLBMissOrDAFaultM, DTLBMissOrDAFaultNoTrapM;
   logic                       SelHPTWAdr;
@@ -84,7 +82,7 @@ module lsuvirtmem(
   interlockfsm interlockfsm (
     .clk, .reset, .MemRWM, .AtomicM, .ITLBMissOrDAFaultF, .ITLBWriteF,
     .DTLBMissOrDAFaultM, .DTLBWriteM, .TrapM, .DCacheStallM,
-    .InterlockStall, .SelReplayMemE, .SelHPTW, .IgnoreRequestTLB);
+    .InterlockStall, .SelHPTW, .IgnoreRequestTLB);
   hptw hptw( 
     .clk, .reset, .SATP_REGW, .PCF, .IEUAdrExtM, .MemRWM, .AtomicM,
     .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW,
@@ -97,8 +95,6 @@ module lsuvirtmem(
   // to the orignal data virtual address.
   assign SelHPTWAdr = SelHPTW & ~(DTLBWriteM | ITLBWriteF);
 
-  assign SelReplay = SelHPTWAdr | SelReplayMemE;
-
   // multiplex the outputs to LSU
   if(`XLEN+2-`PA_BITS > 0) begin
     logic [(`XLEN+2-`PA_BITS)-1:0] zeros;

pipelined/src/privileged/csrsr.sv

@@ -126,7 +126,6 @@ module csrsr (
       else if (PrivilegeModeW == `M_MODE & STATUS_MPRV)  EndiannessPrivMode = STATUS_MPP;
       else                                               EndiannessPrivMode = PrivilegeModeW;
 
-      // *** Ross possible BUG: HPTW needs to match the endianness of SBE not xBE.
       case (EndiannessPrivMode) 
         `M_MODE: BigEndianM = STATUS_MBE;
         `S_MODE: BigEndianM = STATUS_SBE;