Merge pull request #327 from harshinisrinath1001/main

Fixed the spacing in the fpu module

src/fpu/fcmp.sv

@@ -151,5 +151,4 @@ module fcmp import cvw::*;  #(parameter cvw_t P) (
   //    - inf = inf and -inf = -inf
   //    - return 0 if comparison with NaN (unordered)
   assign CmpIntRes = {(P.XLEN-1)'(0), (((EQ|BothZero)&OpCtrl[1])|(LT&OpCtrl[0]&~BothZero))&~EitherNaN};
-  
 endmodule

src/fpu/fcvt.sv

@@ -1,4 +1,3 @@
-
 ///////////////////////////////////////////
 // fcvt.sv
 //
@@ -222,5 +221,4 @@ module fcvt import cvw::*;  #(parameter cvw_t P) (
           if(Int64)   Cs = Int[P.XLEN-1]&Signed;
           else        Cs = Int[31]&Signed;
       else            Cs = Xs;
-
 endmodule

src/fpu/fhazard.sv

@@ -56,7 +56,6 @@ module fhazard(
       // if the needed value is in the writeback stage
     end else if ((Adr1E == RdW) & FRegWriteW) ForwardXE = 2'b01; // choose FResult64W
   
-
     // if the needed value is in the memory stage - input 2
     if ((Adr2E == RdM) & FRegWriteM) begin
       // if the result will be FResM (can be taken from the memory stage)
@@ -64,7 +63,6 @@ module fhazard(
       // if the needed value is in the writeback stage
     end else if ((Adr2E == RdW) & FRegWriteW) ForwardYE = 2'b01; // choose FResult64W
 
-
     // if the needed value is in the memory stage - input 3
     if ((Adr3E == RdM) & FRegWriteM) begin
       // if the result will be FResM (can be taken from the memory stage)
@@ -72,5 +70,4 @@ module fhazard(
       // if the needed value is in the writeback stage
     end else if ((Adr3E == RdW) & FRegWriteW) ForwardZE = 2'b01; // choose FResult64W
   end 
-
 endmodule

src/fpu/fpu.sv

@@ -262,7 +262,6 @@ module fpu import cvw::*;  #(parameter cvw_t P) (
     .ToInt(FWriteIntE), .XZero(XZeroE), .Fmt(FmtE), .Ce(CeE), .ShiftAmt(CvtShiftAmtE), 
     .ResSubnormUf(CvtResSubnormUfE), .Cs(CsE), .IntZero(IntZeroE), .LzcIn(CvtLzcInE));
 
-
   // NaN Box SrcA to convert integer to requested FP size
   if(P.FPSIZES == 1) assign AlignedSrcAE = {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE};
   else if(P.FPSIZES == 2) 

src/fpu/fregfile.sv

@@ -51,4 +51,3 @@ module fregfile #(parameter FLEN) (
    assign #2 rd3 = rf[a3];
    
 endmodule // regfile
-

src/fpu/fsgninj.sv

@@ -73,5 +73,4 @@ module fsgninj import cvw::*;  #(parameter cvw_t P) (
       endcase
     assign SgnRes = {SgnBits[3], X[P.Q_LEN-2:P.D_LEN], SgnBits[2], X[P.D_LEN-2:P.S_LEN], SgnBits[1], X[P.S_LEN-2:P.H_LEN], SgnBits[0], X[P.H_LEN-2:0]};
   end
-
 endmodule

src/fpu/unpackinput.sv

@@ -107,7 +107,6 @@ module unpackinput import cvw::*;  #(parameter cvw_t P) (
       // is the exponent all 1's
       assign ExpMax = Fmt ? &In[P.FLEN-2:P.NF] : &In[P.LEN1-2:P.NF1];
   
-
   end else if (P.FPSIZES == 3) begin       // three floating point precsions supported
 
       // largest format | larger format  | smallest format
@@ -247,7 +246,6 @@ module unpackinput import cvw::*;  #(parameter cvw_t P) (
               2'b10: Sgn = In[P.H_LEN-1];
           endcase
 
-
       // extract the fraction
       always_comb
           case (Fmt)
@@ -266,7 +264,6 @@ module unpackinput import cvw::*;  #(parameter cvw_t P) (
               2'b10: ExpNonZero = |In[P.H_LEN-2:P.H_NF]; 
           endcase
 
-
       // example double to single conversion:
       // 1023 = 0011 1111 1111
       // 127  = 0000 0111 1111 (subtract this)
@@ -285,7 +282,6 @@ module unpackinput import cvw::*;  #(parameter cvw_t P) (
               2'b10: Exp = {In[P.H_LEN-2], {P.Q_NE-P.H_NE{~In[P.H_LEN-2]}}, In[P.H_LEN-3:P.H_NF+1], In[P.H_NF]|~ExpNonZero}; 
           endcase
   
-
       // is the exponent all 1's
       always_comb 
           case (Fmt)

src/generic/adder.sv

@@ -33,5 +33,3 @@ module adder #(parameter WIDTH=8) (
 
   assign y = a + b;
 endmodule 
-
-

src/generic/counter.sv

@@ -36,5 +36,3 @@ module counter #(parameter WIDTH=8) (
   assign qnext = q + 1;
   flopenr #(WIDTH) cntrflop(clk, reset, en, qnext, q);
 endmodule 
-
-

src/generic/neg.sv

@@ -32,4 +32,3 @@ module neg #(parameter WIDTH = 8) (
 
   assign y = ~a + 1;
 endmodule
-

src/generic/or_rows.sv

@@ -48,5 +48,3 @@ module or_rows #(parameter ROWS = 8, COLS=2) (
     /* verilator lint_on UNOPTFLAT */
   end
 endmodule
-
-

src/generic/prioritythermometer.sv

@@ -48,6 +48,3 @@ module prioritythermometer #(parameter N = 8) (
   end
   /* verilator lint_on UNOPTFLAT */
 endmodule
-
-
-