Successfully added RVVIStall for back pressure to slow down the pipeline if the ethernet or host computer running imperasDV can't keep up.

src/hazard/hazard.sv

@@ -31,7 +31,7 @@ module hazard import cvw::*;  #(parameter cvw_t P) (
   input  logic  BPWrongE, CSRWriteFenceM, RetM, TrapM,   
   input  logic  StructuralStallD,
   input  logic  LSUStallM, IFUStallF,
-  input  logic  FPUStallD,
+  input  logic  FPUStallD, RVVIStall,
   input  logic  DivBusyE, FDivBusyE,
   input  logic  wfiM, IntPendingM,
   // Stall & flush outputs
@@ -89,7 +89,7 @@ module hazard import cvw::*;  #(parameter cvw_t P) (
   // Need to gate IFUStallF when the equivalent FlushFCause = FlushDCause = 1.
   // assign StallWCause = ((IFUStallF & ~FlushDCause) | LSUStallM) & ~FlushWCause;
   // Because FlushWCause is a strict subset of FlushDCause, FlushWCause is factored out.
-  assign StallWCause = (IFUStallF & ~FlushDCause) | (LSUStallM & ~FlushWCause);
+  assign StallWCause = (IFUStallF & ~FlushDCause) | (LSUStallM & ~FlushWCause) | RVVIStall;
 
   // Stall each stage for cause or if the next stage is stalled
   // coverage off: StallFCause is always 0

src/wally/packetizer.sv

@@ -143,7 +143,6 @@ module packetizer import cvw::*; #(parameter cvw_t P,
   assign m_axi_wlast = BurstDone;
   assign m_axi_wvalid = (CurrState == STATE_RDY & valid) | (CurrState == STATE_TRANS);
   
-
   assign m_axi_bready = 1'b1; // *** probably wrong.
 
   // we aren't using the read channels. This ethernet device isn't going to read anything for now

src/wally/wallypipelinedcore.sv

@@ -44,7 +44,8 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
    output logic [2:0]            HBURST,
    output logic [3:0]            HPROT,
    output logic [1:0]            HTRANS,
-   output logic                  HMASTLOCK
+   output logic                  HMASTLOCK,
+   input  logic                  RVVIStall
 );
 
   logic                          StallF, StallD, StallE, StallM, StallW;
@@ -274,7 +275,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
     .BPWrongE, .CSRWriteFenceM, .RetM, .TrapM,
     .StructuralStallD,
     .LSUStallM, .IFUStallF,
-    .FPUStallD,
+    .FPUStallD, .RVVIStall,
     .DivBusyE, .FDivBusyE,
     .wfiM, .IntPendingM,
     // Stall & flush outputs

src/wally/wallypipelinedsoc.sv

@@ -68,6 +68,11 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P)  (
   logic [63:0]                MTIME_CLINT;      // from CLINT to CSRs
   logic                       MExtInt,SExtInt;  // from PLIC
 
+  localparam MAX_CSRS = 3;
+  logic                       valid;
+  logic                       RVVIStall;
+  logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvvi;
+
   // synchronize reset to SOC clock domain
   synchronizer resetsync(.clk, .d(reset_ext), .q(reset)); 
    
@@ -75,7 +80,7 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P)  (
   wallypipelinedcore #(P) core(.clk, .reset,
     .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT,
     .HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB,
-    .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK
+    .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .RVVIStall
    );
 
   // instantiate uncore if a bus interface exists
@@ -91,9 +96,7 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P)  (
   end
 
 
-  localparam MAX_CSRS = 3;
+
-  logic valid;
-  logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvvi;
   rvvisynth #(P, MAX_CSRS) rvvisynth(.clk, .reset, .valid, .rvvi);
 
   logic [3:0]                                       m_axi_awid;
@@ -134,7 +137,6 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P)  (
 
 
 
-  logic                                             RVVIStall;
 
   packetizer #(P, MAX_CSRS) packetizer(.rvvi, .valid, .m_axi_aclk(clk), .m_axi_aresetn(~reset), .RVVIStall,
     .m_axi_awid, .m_axi_awaddr, .m_axi_awlen, .m_axi_awsize, .m_axi_awburst, .m_axi_awcache, .m_axi_awvalid,