Added ahblite bus interface unit

wally-pipelined/config/rv64ic/wally-config.vh

@@ -58,6 +58,11 @@
 // Address space
 `define RESET_VECTOR 64'h0000000080000000
 
+// Bus Interface
+`define AHBW 64
+
+// Peripheral Addresses
+
 // Test modes
 
 // Tie GPIO outputs back to inputs

wally-pipelined/lint-wally

@@ -1,7 +1,7 @@
 # check for warnings in Verilog code
 # The verilator lint tool is faster and better than Modelsim so it is best to run this first.
 
-verilator --lint-only --top-module wallypipelined -Iconfig/rv64ic src/*.sv
+verilator --lint-only --top-module wallypipelinedsoc -Iconfig/rv64ic src/*.sv
 
 # --lint-only just runs lint rather than trying to compile and simulate
 # -I points to the include directory where files such as `include wally-config.vh  are found

wally-pipelined/src/ahblite.sv

@@ -0,0 +1,99 @@
+///////////////////////////////////////////
+// ahblite.sv
+//
+// Written: David_Harris@hmc.edu 9 January 2021
+// Modified: 
+//
+// Purpose: AHB Lite External Bus Unit
+//          See ARM_HIH0033A_AMBA_AHB-Lite_SPEC 1.0
+//          Arbitrates requests from instruction and data streams
+//          Connects hart to peripherals and I/O pins on SOC
+//          Bus width presently matches XLEN
+//          Anticipate replacing this with an AXI bus interface to communicate with FPGA DRAM/Flash controllers
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module ahblite (
+  input  logic             clk, reset,
+  // Signals from Instruction Cache
+  input  logic [`XLEN-1:0] IPAdrD,
+  input  logic             IReadD,
+  output logic [`XLEN-1:0] IRData,
+  output logic             IReady,
+  // Signals from Data Cache
+  input  logic [`XLEN-1:0] DPAdrM,
+  input  logic             DReadM, DWriteM,
+  input  logic [`XLEN-1:0] DWDataM,
+  input  logic [1:0]       DSizeM,
+  output logic [`XLEN-1:0] DRData,
+  output logic             DReady,
+  // AHB-Lite external signals
+  input  logic [`AHBW-1:0] HRDATA,
+  input  logic             HREADY, HRESP,
+  output logic [31:0]      HADDR,
+  output logic [`AHBW-1:0] HWDATA,
+  output logic             HWRITE,
+  output logic [2:0]       HSIZE,
+  output logic [2:0]       HBURST,
+  output logic [3:0]       HPROT,
+  output logic [1:0]       HTRANS,
+  output logic             HMASTLOCK
+);
+
+  logic HCLK, HRESETn;
+  logic GrantData;
+  logic [2:0] ISize;
+
+  assign HCLK = clk;
+  assign HRESETn = ~reset;
+
+  // Arbitrate requests by giving data priority over instructions
+  assign GrantData = DReadM | DWriteM;
+
+  // *** initially support HABW = XLEN
+
+  // Choose ISize based on XLen
+  generate
+    if (`AHBW == 32) assign ISize = 3'b010; // 32-bit transfers
+    else             assign ISize = 3'b011; // 64-bit transfers
+  endgenerate
+
+  // drive bus outputs
+  assign HADDR = GrantData ? DPAdrM[31:0] : IPAdrD[31:0];
+  flop #(`XLEN) wdreg(HCLK, DWDataM, HWDATA); // delay HWDATA by 1 cycle per spec; *** assumes AHBW = XLEN
+  assign HWRITE = DWriteM; // *** check no level to pulse conversion needed
+  assign HSIZE = GrantData ? {1'b0, DSizeM} : ISize;
+  assign HBURST = 3'b000; // Single burst only supported; consider generalizing for cache fillsfHPROT
+  assign HPROT = 4'b0011; // not used; see Section 3.7
+  assign HTRANS = IReadD | DReadM | DWriteM ? 2'b10 : 2'b00; // NONSEQ if reading or writing, IDLE otherwise
+  assign HMASTLOCK = 0; // no locking supported
+                  
+  // Route signals to Instruction and Data Caches
+  // *** assumes AHBW = XLEN
+  assign IRData = HRDATA;
+  assign IReady = HREADY & IReadD & ~GrantData;
+  assign DRData = HRDATA;
+  assign DReady = HREADY & GrantData;
+
+  // *** consider adding memory access faults based on HRESP being high
+  //   InstrAccessFaultF, DataAccessFaultM,
+
+endmodule
+

wally-pipelined/src/uartPC16550D.sv

@@ -145,16 +145,6 @@ module uartPC16550D(
           3'b110: MSR <= Din[3:0];
           3'b111: SCR <= Din;
         endcase
-      end else if (~MEMRb) begin
-        /* verilator lint_off CASEINCOMPLETE */
-        case (A)
-          3'b101: begin // clear some LSR bits on read
-            LSR[4:1] <= 0;
-            LSR[7] <= 0;
-          end
-          3'b110: MSR[1:0] <= 4'b0; // clear status bits on read
-        endcase
-        /* verilator lint_on CASEINCOMPLETE */
       end
       // Line Status Register (8.6.3)
       LSR[0] <= rxdataready; // Data ready

wally-pipelined/src/wallypipelinedhart.sv

@@ -36,7 +36,19 @@ module wallypipelinedhart (
   input  logic [`XLEN-1:0] ReadDataM,
   input  logic            TimerIntM, ExtIntM, SwIntM,
   input  logic            InstrAccessFaultF,
-  input  logic            DataAccessFaultM);
+  input  logic            DataAccessFaultM,
+  // Bus Interface
+  input  logic [`AHBW-1:0] HRDATA,
+  input  logic             HREADY, HRESP,
+  output logic [31:0]      HADDR,
+  output logic [`AHBW-1:0] HWDATA,
+  output logic             HWRITE,
+  output logic [2:0]       HSIZE,
+  output logic [2:0]       HBURST,
+  output logic [3:0]       HPROT,
+  output logic [1:0]       HTRANS,
+  output logic             HMASTLOCK
+);
 
   logic [1:0]  ForwardAE, ForwardBE;
   logic        StallF, StallD, FlushD, FlushE, FlushM, FlushW;
@@ -57,6 +69,7 @@ module wallypipelinedhart (
   logic LoadMisalignedFaultM, LoadAccessFaultM;
   logic StoreMisalignedFaultM, StoreAccessFaultM;
   logic [`XLEN-1:0] InstrMisalignedAdrM;
+  logic [`XLEN-1:0] zero = 0;
 
   logic        PCSrcE;
   logic        RegWriteM;
@@ -75,10 +88,15 @@ module wallypipelinedhart (
   ieu ieu(.*); // inteber execution unit: integer register file, datapath and controller
   dcu dcu(.Funct3M(InstrM[14:12]), .*); // data cache unit
 
+  ahblite ebu(
+    .IPAdrD(zero), .IReadD(1'b0), .IRData(), .IReady(), 
+    .DPAdrM(DataAdrM), .DReadM(MemRWM[1]), .DWriteM(MemRWM[0]), .DWDataM(WriteDataM), .DSizeM(2'b11), .DRData(), .DReady(), 
+    .*);
+
 /*  
   mdu mdu(.*); // multiply and divide unit
   fpu fpu(.*); // floating point unit
-  ebu ebu(.*); // external bus to memory and peripherals */
+  */
   hazard     hzu(.*);	// global stall and flush control
 
   // Priveleged block operates in M and W stages, handling CSRs and exceptions

wally-pipelined/src/wallypipelinedsoc.sv

@@ -1,38 +1,17 @@
 ///////////////////////////////////////////
-// wally-pipelined.sv
+// wally-pipelinedsoc.sv
 //
 // Written: David_Harris@hmc.edu 6 November 2020
 // Modified: 
 //
-// Purpose: Top level module for pipelined processor and memories
+// Purpose: System on chip including pipelined processor and memories
 // Full RV32/64IC instruction set
 //
-// To Do:
-//  Sort out terminology of faults, traps, interrputs, exceptions
-//  Long names for instruction decoder
-//  *Consitency in capitalizaiton
-//  *Divide into many files
-//  *Keep lint clean
-//  *Put in git repo
-//  Sort out memory map
-//  *Automate testing based on MISA
-//  Drop Funct3 from Controller pipeline if not needed
-//  Finish exceptions & test
-//    *Flushes caused by exceptions
-//    Generate statements to reduce hardware for unneeded exception logic
-//    *RET
-//    *Status register
-//    Misaligned instruction faults on other aults
-//
-//
 // Note: the CSRs do not support the following features
 //- Disabling portions of the instruction set with bits of the MISA register
 //- Changing from RV64 to RV32 by writing the SXL/UXL bits of the STATUS register
 // As of January 2020, virtual memory is not yet supported
 //
-// Reference MISA Values: 
-//  104: C compressed
-//
 // A component of the Wally configurable RISC-V project.
 // 
 // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
@@ -52,16 +31,28 @@
 
 `include "wally-config.vh"
 
-module wallypipelined (
+module wallypipelinedsoc (
   input  logic            clk, reset, 
-  output logic [`XLEN-1:0] WriteDataM, DataAdrM, 
+  // AHB Lite Interface
-  output logic [1:0]      MemRWM,
+  input  logic [`AHBW-1:0] HRDATA,
+  input  logic             HREADY, HRESP,
+  output logic [31:0]      HADDR,
+  output logic [`AHBW-1:0] HWDATA,
+  output logic             HWRITE,
+  output logic [2:0]       HSIZE,
+  output logic [2:0]       HBURST,
+  output logic [3:0]       HPROT,
+  output logic [1:0]       HTRANS,
+  output logic             HMASTLOCK,
+  // I/O Interface
   input  logic [31:0]      GPIOPinsIn,
   output logic [31:0]      GPIOPinsOut, GPIOPinsEn,
   input  logic             UARTSin,
   output logic             UARTSout
 );
 
+  logic [1:0] MemRWM;
+  logic [`XLEN-1:0] DataAdrM, WriteDataM;
   logic [`XLEN-1:0] PCF, ReadDataM;
   logic [31:0] InstrF;
   logic [7:0]  ByteMaskM;

wally-pipelined/testbench/testbench-imperas.sv

@@ -30,9 +30,6 @@ module testbench();
   logic        clk;
   logic        reset;
 
-  logic [`XLEN-1:0] WriteData, DataAdr;
-  logic [1:0]      MemRW;
-
   int test, i, errors, totalerrors;
   logic [31:0] sig32[0:10000];
   logic [`XLEN-1:0] signature[0:10000];
@@ -223,6 +220,18 @@ string tests32i[] = {
 };
   string tests[];
 
+  logic [`AHBW-1:0] HRDATA;
+  logic             HREADY, HRESP;
+  logic [31:0]      HADDR;
+  logic [`AHBW-1:0] HWDATA;
+  logic             HWRITE;
+  logic [2:0]       HSIZE;
+  logic [2:0]       HBURST;
+  logic [3:0]       HPROT;
+  logic [1:0]       HTRANS;
+  logic             HMASTLOCK;
+
+  
   // pick tests based on modes supported
   initial 
     if (`XLEN == 64) begin // RV64
@@ -242,10 +251,11 @@ string tests32i[] = {
   // instantiate device to be tested
   assign GPIOPinsIn = 0;
   assign UARTSin = 1;
-  wallypipelined dut(
+  assign HREADY = 1;
-    clk, reset, WriteData, DataAdr, MemRW, 
+  assign HRESP = 0;
-    GPIOPinsIn, GPIOPinsOut, GPIOPinsEn, UARTSin, UARTSout
+  assign HRDATA = 0;
-  ); 
+
+  wallypipelinedsoc dut(.*); 
 
   // Track names of instructions
   instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,