From e4d6a9f8c6247ce18177746c8a329e16849caead Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 19 Jul 2023 10:28:54 -0500 Subject: [PATCH] Removed all old configuration files. --- config/buildroot/config.vh | 1 - config/buildroot/wally-config.vh | 153 -------------------------- config/fpga/wally-config.vh | 162 ---------------------------- config/rv32e/rv32e-config.vh | 178 ------------------------------- config/shared/wally-shared.vh | 142 ------------------------ fpga/src/fpgaTopArtyA7.v | 6 +- testbench/testbench-linux.sv | 2 +- 7 files changed, 3 insertions(+), 641 deletions(-) delete mode 100644 config/buildroot/wally-config.vh delete mode 100644 config/fpga/wally-config.vh delete mode 100644 config/rv32e/rv32e-config.vh delete mode 100644 config/shared/wally-shared.vh diff --git a/config/buildroot/config.vh b/config/buildroot/config.vh index e0441860d..f3e15d6f0 100644 --- a/config/buildroot/config.vh +++ b/config/buildroot/config.vh @@ -27,7 +27,6 @@ // include shared configuration `include "BranchPredictorType.vh" -`include "wally-shared.vh" localparam FPGA = 1; // RV32 or RV64: XLEN = 32 or 64 diff --git a/config/buildroot/wally-config.vh b/config/buildroot/wally-config.vh deleted file mode 100644 index 0957dd003..000000000 --- a/config/buildroot/wally-config.vh +++ /dev/null @@ -1,153 +0,0 @@ -////////////////////////////////////////// -// wally-config.vh -// -// Written: David_Harris@hmc.edu 4 January 2021 -// Modified: -// -// Purpose: Specify which features are configured -// Macros to determine which modes are supported based on MISA -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -// include shared configuration -`include "wally-shared.vh" - -`define FPGA 1 -`define QEMU 0 -// RV32 or RV64: XLEN = 32 or 64 -`define XLEN 64 - -// IEEE 754 compliance -`define IEEE754 0 - -`define MISA (32'h0014112D) -`define ZICSR_SUPPORTED 1 -`define ZIFENCEI_SUPPORTED 1 -`define ZICOUNTERS_SUPPORTED 1 -`define COUNTERS 32 -`define ZFH_SUPPORTED 0 -`define SSTC_SUPPORTED 0 - -// LSU microarchitectural Features -`define BUS_SUPPORTED 1 -`define DCACHE_SUPPORTED 1 -`define ICACHE_SUPPORTED 1 -`define VIRTMEM_SUPPORTED 1 -`define VECTORED_INTERRUPTS_SUPPORTED 1 -`define BIGENDIAN_SUPPORTED 1 - -// TLB configuration. Entries should be a power of 2 -`define ITLB_ENTRIES 32 -`define DTLB_ENTRIES 32 - -// Cache configuration. Sizes should be a power of two -// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines -`define DCACHE_NUMWAYS 4 -`define DCACHE_WAYSIZEINBYTES 4096 -`define DCACHE_LINELENINBITS 512 -`define ICACHE_NUMWAYS 4 -`define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_LINELENINBITS 512 - -// Integer Divider Configuration -// IDIV_BITSPERCYCLE must be 1, 2, or 4 -`define IDIV_BITSPERCYCLE 4 -`define IDIV_ON_FPU 1 - -// Legal number of PMP entries are 0, 16, or 64 -`define PMP_ENTRIES 16 - -// Address space -`define RESET_VECTOR 64'h0000000000001000 - -// WFI Timeout Wait -`define WFI_TIMEOUT_BIT 16 - -// Peripheral Addresses -// Peripheral memory space extends from BASE to BASE+RANGE -// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define DTIM_SUPPORTED 1'b0 -`define DTIM_BASE 56'h80000000 -`define DTIM_RANGE 56'h00001FFF -`define IROM_SUPPORTED 1'b0 -`define IROM_BASE 56'h80000000 -`define IROM_RANGE 56'h00001FFF -`define BOOTROM_SUPPORTED 1'b1 -`define BOOTROM_BASE 56'h00001000 -`define BOOTROM_RANGE 56'h00000FFF -`define UNCORE_RAM_SUPPORTED 1'b1 -`define UNCORE_RAM_BASE 56'h80000000 -`define UNCORE_RAM_RANGE 56'h07FFFFFF -`define EXT_MEM_SUPPORTED 1'b0 -`define EXT_MEM_BASE 56'h80000000 -`define EXT_MEM_RANGE 56'h07FFFFFF -`define CLINT_SUPPORTED 1'b1 -`define CLINT_BASE 56'h02000000 -`define CLINT_RANGE 56'h0000FFFF -`define GPIO_SUPPORTED 1'b1 -`define GPIO_BASE 56'h10060000 -`define GPIO_RANGE 56'h000000FF -`define UART_SUPPORTED 1'b1 -`define UART_BASE 56'h10000000 -`define UART_RANGE 56'h00000007 -`define PLIC_SUPPORTED 1'b1 -`define PLIC_BASE 56'h0C000000 -`define PLIC_RANGE 56'h03FFFFFF -`define SDC_SUPPORTED 1'b0 -`define SDC_BASE 56'h00012100 -`define SDC_RANGE 56'h0000001F - -// Bus Interface width -`define AHBW 64 - -// Test modes - -// Tie GPIO outputs back to inputs -`define GPIO_LOOPBACK_TEST 0 - -// Hardware configuration -`define UART_PRESCALE 0 - -// Interrupt configuration -`define PLIC_NUM_SRC 53 -`define PLIC_UART_ID 10 -`define PLIC_GPIO_ID 3 - -`define BPRED_SUPPORTED 1 -`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT -`define BPRED_SIZE 10 -`define BPRED_NUM_LHR 6 -`define BTB_SIZE 10 - - -`define SVADU_SUPPORTED 1 -`define ZMMUL_SUPPORTED 0 - -// FPU division architecture -`define RADIX 32'h4 -`define DIVCOPIES 32'h4 - -// bit manipulation -`define ZBA_SUPPORTED 0 -`define ZBB_SUPPORTED 0 -`define ZBC_SUPPORTED 0 -`define ZBS_SUPPORTED 0 - -// Memory synthesis configuration -`define USE_SRAM 0 diff --git a/config/fpga/wally-config.vh b/config/fpga/wally-config.vh deleted file mode 100644 index 9230c148e..000000000 --- a/config/fpga/wally-config.vh +++ /dev/null @@ -1,162 +0,0 @@ -////////////////////////////////////////// -// wally-config.vh -// -// Written: David_Harris@hmc.edu 4 January 2021 -// Modified: -// -// Purpose: Specify which features are configured -// Macros to determine which modes are supported based on MISA -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -// include shared configuration -`include "wally-shared.vh" - -`define FPGA 1 -`define QEMU 0 - -// RV32 or RV64: XLEN = 32 or 64 -`define XLEN 64 - -// IEEE 754 compliance -`define IEEE754 0 - -`define MISA (32'h0014112D) -`define ZICSR_SUPPORTED 1 -`define ZIFENCEI_SUPPORTED 1 -`define ZICOUNTERS_SUPPORTED 1 -`define ZFH_SUPPORTED 0 -`define COUNTERS 32 -`define SSTC_SUPPORTED 0 - -// LSU microarchitectural Features -`define BUS_SUPPORTED 1 -`define DCACHE_SUPPORTED 1 -`define ICACHE_SUPPORTED 1 -`define VIRTMEM_SUPPORTED 1 -`define VECTORED_INTERRUPTS_SUPPORTED 1 -`define BIGENDIAN_SUPPORTED 1 - -// TLB configuration. Entries should be a power of 2 -`define ITLB_ENTRIES 32 -`define DTLB_ENTRIES 32 - -// Cache configuration. Sizes should be a power of two -// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines -`define DCACHE_NUMWAYS 4 -`define DCACHE_WAYSIZEINBYTES 4096 -`define DCACHE_LINELENINBITS 512 -`define ICACHE_NUMWAYS 4 -`define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_LINELENINBITS 512 - -// Integer Divider Configuration -// IDIV_BITSPERCYCLE must be 1, 2, or 4 -`define IDIV_BITSPERCYCLE 4 -`define IDIV_ON_FPU 1 - -// Legal number of PMP entries are 0, 16, or 64 -`define PMP_ENTRIES 16 - -// Address space -`define RESET_VECTOR 64'h0000000000001000 - -// WFI Timeout Wait -`define WFI_TIMEOUT_BIT 16 - -// Peripheral Addresses -// Peripheral memory space extends from BASE to BASE+RANGE -// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define DTIM_SUPPORTED 1'b0 -`define DTIM_BASE 56'h80000000 -`define DTIM_RANGE 56'h00001FFF -`define IROM_SUPPORTED 1'b0 -`define IROM_BASE 56'h80000000 -`define IROM_RANGE 56'h00001FFF - -`define BOOTROM_SUPPORTED 1'b1 -`define BOOTROM_BASE 56'h00001000 -`define BOOTROM_RANGE 56'h00000FFF - -`define UNCORE_RAM_SUPPORTED 1'b0 -`define UNCORE_RAM_BASE 56'h100000000 -`define UNCORE_RAM_RANGE 56'h07FFFFFF - -`define EXT_MEM_SUPPORTED 1'b1 -`define EXT_MEM_BASE 56'h80000000 -`define EXT_MEM_RANGE 56'h07FFFFFF - -`define EXT_SUPPORTED 1'b0 -`define EXT_BASE 56'h80000000 -`define EXT_RANGE 56'h07FFFFFF - -`define CLINT_SUPPORTED 1'b1 -`define CLINT_BASE 56'h02000000 -`define CLINT_RANGE 56'h0000FFFF -`define GPIO_SUPPORTED 1'b1 -`define GPIO_BASE 56'h10060000 -`define GPIO_RANGE 56'h000000FF -`define UART_SUPPORTED 1'b1 -`define UART_BASE 56'h10000000 -`define UART_RANGE 56'h00000007 -`define PLIC_SUPPORTED 1'b1 -`define PLIC_BASE 56'h0C000000 -`define PLIC_RANGE 56'h03FFFFFF -`define SDC_SUPPORTED 1'b1 -`define SDC_BASE 56'h00012100 -`define SDC_RANGE 56'h0000001F - -// Bus Interface width -`define AHBW 64 - -// Test modes - -// Tie GPIO outputs back to inputs -`define GPIO_LOOPBACK_TEST 0 - -// Hardware configuration -`define UART_PRESCALE 0 - -// Interrupt configuration -`define PLIC_NUM_SRC 53 -`define PLIC_UART_ID 10 -`define PLIC_GPIO_ID 3 - -`define BPRED_SUPPORTED 1 -`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT -`define BPRED_SIZE 12 -`define BPRED_NUM_LHR 6 -`define BTB_SIZE 10 - - -`define SVADU_SUPPORTED 1 -`define ZMMUL_SUPPORTED 0 - -// FPU division architecture -`define RADIX 32'h4 -`define DIVCOPIES 32'h4 - -// bit manipulation -`define ZBA_SUPPORTED 0 -`define ZBB_SUPPORTED 0 -`define ZBC_SUPPORTED 0 -`define ZBS_SUPPORTED 0 - -// Memory synthesis configuration -`define USE_SRAM 0 diff --git a/config/rv32e/rv32e-config.vh b/config/rv32e/rv32e-config.vh deleted file mode 100644 index 4701b69f1..000000000 --- a/config/rv32e/rv32e-config.vh +++ /dev/null @@ -1,178 +0,0 @@ -////////////////////////////////////////// -// wally-config.vh -// -// Written: David_Harris@hmc.edu 4 January 2021 -// Modified: -// -// Purpose: Specify which features are configured -// Macros to determine which modes are supported based on MISA -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -localparam PA_BITS = 34; -//localparam AHBW = 32; -//localparam XLEN = 32; -//localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 ); -////localparam BUS_SUPPORTED = 1'b1; -//localparam ZICSR_SUPPORTED = 1'b0; -localparam M_SUPPORTED = 1'b0; -localparam F_SUPPORTED = 1'b0; -//localparam ZMMUL_SUPPORTED = 1'b0; -//localparam F_SUPPORTED = 1'b0; -//localparam PMP_ENTRIES = 0; -localparam LLEN = 32; -//localparam FPGA = 1'b0; -//localparam QEMU = 1'b0; - // //VPN_SEGMENT_BITS: (LLEN == 32 ? 10 : 9), - // `include "test-shared.vh" -localparam FLEN = 32; - -`include "test-shared.vh" - - - -// include shared configuration -//`include "wally-shared.vh" - -localparam FPGA = 0; -localparam QEMU = 0; - -// RV32 or RV64: XLEN = 32 or 64 -localparam XLEN = 32; - -// IEEE 754 compliance -localparam IEEE754 = 0; - -// E -localparam MISA = (32'h00000010); -localparam ZICSR_SUPPORTED = 0; -localparam ZIFENCEI_SUPPORTED = 0; -localparam COUNTERS = 0; -localparam ZICOUNTERS_SUPPORTED = 0; -localparam ZFH_SUPPORTED = 0; -localparam SSTC_SUPPORTED = 0; - -// LSU microarchitectural Features -localparam BUS_SUPPORTED = 1; -localparam DCACHE_SUPPORTED = 0; -localparam ICACHE_SUPPORTED = 0; -localparam VIRTMEM_SUPPORTED = 0; -localparam VECTORED_INTERRUPTS_SUPPORTED = 0; -localparam BIGENDIAN_SUPPORTED = 0; - -// TLB configuration. Entries should be a power of 2 -localparam ITLB_ENTRIES = 0; -localparam DTLB_ENTRIES = 0; - -// Cache configuration. Sizes should be a power of two -// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines -localparam DCACHE_NUMWAYS = 4; -localparam DCACHE_WAYSIZEINBYTES = 4096; -localparam DCACHE_LINELENINBITS = 512; -localparam ICACHE_NUMWAYS = 4; -localparam ICACHE_WAYSIZEINBYTES = 4096; -localparam ICACHE_LINELENINBITS = 512; - -// Integer Divider Configuration -// IDIV_BITSPERCYCLE must be 1, 2, or 4 -localparam IDIV_BITSPERCYCLE = 1; -localparam IDIV_ON_FPU = 0; - -// Legal number of PMP entries are 0, 16, or 64 -localparam PMP_ENTRIES = 0; - -// Address space -localparam RESET_VECTOR = 32'h80000000; - -// WFI Timeout Wait -localparam WFI_TIMEOUT_BIT = 16; - -// Peripheral Addresses -// Peripheral memory space extends from BASE to BASE+RANGE -// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -localparam DTIM_SUPPORTED = 1'b0; -localparam DTIM_BASE = 34'h80000000; -localparam DTIM_RANGE = 34'h007FFFFF; -localparam IROM_SUPPORTED = 1'b0; -localparam IROM_BASE = 34'h80000000; -localparam IROM_RANGE = 34'h007FFFFF; -localparam BOOTROM_SUPPORTED = 1'b1; -localparam BOOTROM_BASE = 34'h00001000; -localparam BOOTROM_RANGE = 34'h00000FFF; -localparam UNCORE_RAM_SUPPORTED = 1'b1; -localparam UNCORE_RAM_BASE = 34'h80000000; -localparam UNCORE_RAM_RANGE = 34'h07FFFFFF; -localparam EXT_MEM_SUPPORTED = 1'b0; -localparam EXT_MEM_BASE = 34'h80000000; -localparam EXT_MEM_RANGE = 34'h07FFFFFF; -localparam CLINT_SUPPORTED = 1'b0; -localparam CLINT_BASE = 34'h02000000; -localparam CLINT_RANGE = 34'h0000FFFF; -localparam GPIO_SUPPORTED = 1'b0; -localparam GPIO_BASE = 34'h10060000; -localparam GPIO_RANGE = 34'h000000FF; -localparam UART_SUPPORTED = 1'b0; -localparam UART_BASE = 34'h10000000; -localparam UART_RANGE = 34'h00000007; -localparam PLIC_SUPPORTED = 1'b0; -localparam PLIC_BASE = 34'h0C000000; -localparam PLIC_RANGE = 34'h03FFFFFF; -localparam SDC_SUPPORTED = 1'b0; -localparam SDC_BASE = 34'h00012100; -localparam SDC_RANGE = 34'h0000001F; - -// Bus Interface width -localparam AHBW = 32; - -// Test modes - -// Tie GPIO outputs back to inputs -localparam GPIO_LOOPBACK_TEST = 1; - -// Hardware configuration -localparam UART_PRESCALE = 1; - -// Interrupt configuration -localparam PLIC_NUM_SRC = 10; -// comment out the following if >=32 sources -localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32); -localparam PLIC_GPIO_ID = 3; -localparam PLIC_UART_ID = 10; - -localparam BPRED_SUPPORTED = 0; -localparam BPRED_TYPE = "BP_GSHARE"; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT -localparam BPRED_SIZE = 10; -localparam BTB_SIZE = 10; - -localparam SVADU_SUPPORTED = 0; -localparam ZMMUL_SUPPORTED = 0; - -// FPU division architecture -localparam RADIX = 4; -localparam DIVCOPIES = 4; - -// bit manipulation -localparam ZBA_SUPPORTED = 0; -localparam ZBB_SUPPORTED = 0; -localparam ZBC_SUPPORTED = 0; -localparam ZBS_SUPPORTED = 0; - -// Memory synthesis configuration -localparam USE_SRAM = 0; - \ No newline at end of file diff --git a/config/shared/wally-shared.vh b/config/shared/wally-shared.vh deleted file mode 100644 index c743753ab..000000000 --- a/config/shared/wally-shared.vh +++ /dev/null @@ -1,142 +0,0 @@ -////////////////////////////////////////// -// wally-shared.vh -// -// Written: david_harris@hmc.edu 7 June 2021 -// -// Purpose: Shared and default configuration values common to all designs -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -// constants defining different privilege modes -// defined in Table 1.1 of the privileged spec -`define M_MODE (2'b11) -`define S_MODE (2'b01) -`define U_MODE (2'b00) - -// Virtual Memory Constants -`define VPN_SEGMENT_BITS (`XLEN == 32 ? 10 : 9) -`define VPN_BITS (`XLEN==32 ? (2*`VPN_SEGMENT_BITS) : (4*`VPN_SEGMENT_BITS)) -`define PPN_BITS (`XLEN==32 ? 22 : 44) -`define PA_BITS (`XLEN==32 ? 34 : 56) -`define SVMODE_BITS (`XLEN==32 ? 1 : 4) -`define ASID_BASE (`XLEN==32 ? 22 : 44) -`define ASID_BITS (`XLEN==32 ? 9 : 16) - -// constants to check SATP_MODE against -// defined in Table 4.3 of the privileged spec -`define NO_TRANSLATE 0 -`define SV32 1 -`define SV39 8 -`define SV48 9 - -// macros to define supported modes -`define A_SUPPORTED ((`MISA >> 0) % 2 == 1) -`define B_SUPPORTED ((`ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED | `ZBS_SUPPORTED)) // not based on MISA -`define C_SUPPORTED ((`MISA >> 2) % 2 == 1) -`define D_SUPPORTED ((`MISA >> 3) % 2 == 1) -`define E_SUPPORTED ((`MISA >> 4) % 2 == 1) -`define F_SUPPORTED ((`MISA >> 5) % 2 == 1) -`define I_SUPPORTED ((`MISA >> 8) % 2 == 1) -`define M_SUPPORTED ((`MISA >> 12) % 2 == 1) -`define Q_SUPPORTED ((`MISA >> 16) % 2 == 1) -`define S_SUPPORTED ((`MISA >> 18) % 2 == 1) -`define U_SUPPORTED ((`MISA >> 20) % 2 == 1) -// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21 - -// logarithm of XLEN, used for number of index bits to select -`define LOG_XLEN (`XLEN == 32 ? 5 : 6) - -// Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries) -`define PMPCFG_ENTRIES (`PMP_ENTRIES/8) - -// Floating point constants for Quad, Double, Single, and Half precisions -`define Q_LEN 32'd128 -`define Q_NE 32'd15 -`define Q_NF 32'd112 -`define Q_BIAS 32'd16383 -`define Q_FMT 2'd3 -`define D_LEN 32'd64 -`define D_NE 32'd11 -`define D_NF 32'd52 -`define D_BIAS 32'd1023 -`define D_FMT 2'd1 -`define S_LEN 32'd32 -`define S_NE 32'd8 -`define S_NF 32'd23 -`define S_BIAS 32'd127 -`define S_FMT 2'd0 -`define H_LEN 32'd16 -`define H_NE 32'd5 -`define H_NF 32'd10 -`define H_BIAS 32'd15 -`define H_FMT 2'd2 - -// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits -`define FLEN (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `S_LEN) -`define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `S_NE) -`define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `S_NF) -`define FMT (`Q_SUPPORTED ? 2'd3 : `D_SUPPORTED ? 2'd1 : 2'd0) -`define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `S_BIAS) -/* Delete once tested dh 10/10/22 - -`define FLEN (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `F_SUPPORTED ? `S_LEN : `H_LEN) -`define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `F_SUPPORTED ? `S_NE : `H_NE) -`define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `F_SUPPORTED ? `S_NF : `H_NF) -`define FMT (`Q_SUPPORTED ? 2'd3 : `D_SUPPORTED ? 2'd1 : `F_SUPPORTED ? 2'd0 : 2'd2) -`define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `F_SUPPORTED ? `S_BIAS : `H_BIAS)*/ - -// Floating point constants needed for FPU paramerterization -`define FPSIZES ((32)'(`Q_SUPPORTED)+(32)'(`D_SUPPORTED)+(32)'(`F_SUPPORTED)+(32)'(`ZFH_SUPPORTED)) -`define FMTBITS ((32)'(`FPSIZES>=3)+1) -`define LEN1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_LEN : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_LEN : `H_LEN) -`define NE1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NE : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NE : `H_NE) -`define NF1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NF : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NF : `H_NF) -`define FMT1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? 2'd1 : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? 2'd0 : 2'd2) -`define BIAS1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_BIAS : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_BIAS : `H_BIAS) -`define LEN2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_LEN : `H_LEN) -`define NE2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NE : `H_NE) -`define NF2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NF : `H_NF) -`define FMT2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? 2'd0 : 2'd2) -`define BIAS2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_BIAS : `H_BIAS) - -// largest length in IEU/FPU -`define CVTLEN ((`NF<`XLEN) ? (`XLEN) : (`NF)) -`define LLEN (($unsigned(`FLEN)<$unsigned(`XLEN)) ? ($unsigned(`XLEN)) : ($unsigned(`FLEN))) -`define LOGCVTLEN $unsigned($clog2(`CVTLEN+1)) -`define NORMSHIFTSZ (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVb + 1 +`NF+1) > (3*`NF+6) ? (`DIVb + 1 +`NF+1) : (3*`NF+6))) -`define LOGNORMSHIFTSZ ($clog2(`NORMSHIFTSZ)) -`define CORRSHIFTSZ (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVN+1+`NF) > (3*`NF+4) ? (`DIVN+1+`NF) : (3*`NF+4))) - -// division constants - -`define DIVN ((((`NF+2)<`XLEN) & `IDIV_ON_FPU) ? `XLEN : `NF+2) // standard length of input -`define LOGR ($clog2(`RADIX)) // r = log(R) -`define RK (`LOGR*`DIVCOPIES) // r*k used for intdiv preproc -`define LOGRK ($clog2(`RK)) // log2(r*k) -`define FPDUR ((`DIVN+1+(`LOGR*`DIVCOPIES))/(`LOGR*`DIVCOPIES)+(`RADIX/4)) -`define DURLEN ($clog2(`FPDUR+1)) -`define DIVb (`FPDUR*`LOGR*`DIVCOPIES-1) // canonical fdiv size (b) -`define DIVBLEN ($clog2(`DIVb+1)-1) -`define DIVa (`DIVb+1-`XLEN) // used for idiv on fpu - -// Disable spurious Verilator warnings - -/* verilator lint_off STMTDLY */ -/* verilator lint_off ASSIGNDLY */ -/* verilator lint_off PINCONNECTEMPTY */ diff --git a/fpga/src/fpgaTopArtyA7.v b/fpga/src/fpgaTopArtyA7.v index 0b10fe4e9..4e73773ab 100644 --- a/fpga/src/fpgaTopArtyA7.v +++ b/fpga/src/fpgaTopArtyA7.v @@ -24,8 +24,6 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-config.vh" - module fpgaTop (input default_100mhz_clk, (* mark_debug = "true" *) input resetn, @@ -68,12 +66,12 @@ module fpgaTop wire HCLKOpen; wire HRESETnOpen; - wire [`AHBW-1:0] HRDATAEXT; + wire [31:0] HRDATAEXT; wire HREADYEXT; wire HRESPEXT; wire HSELEXT; wire [31:0] HADDR; - wire [`AHBW-1:0] HWDATA; + wire [31:0] HWDATA; wire HWRITE; wire [2:0] HSIZE; wire [2:0] HBURST; diff --git a/testbench/testbench-linux.sv b/testbench/testbench-linux.sv index 5c83aca29..4f9a3fd8f 100644 --- a/testbench/testbench-linux.sv +++ b/testbench/testbench-linux.sv @@ -829,7 +829,7 @@ module testbench; SvMode = SATP[63]; // Only perform translation if translation is on and the processor is not // in machine mode - if (SvMode & (dut.core.priv.priv.PrivilegeModeW != `M_MODE)) begin + if (SvMode & (dut.core.priv.priv.PrivilegeModeW != P.M_MODE)) begin BaseAdr = SATP[43:0] << 12; for (i = 2; i >= 0; i--) begin PAdr = BaseAdr + (VPN[i] << 3);