From a58fbd618eda7ef19c23f66b543723a35ca1946c Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 11 Dec 2022 15:48:00 -0600 Subject: [PATCH 1/6] Moved CPUBusy out of HPTW. --- pipelined/src/lsu/lsu.sv | 7 ++++--- pipelined/src/mmu/hptw.sv | 4 +--- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 7e36315ca..e9ef4558a 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -129,18 +129,18 @@ module lsu ( ///////////////////////////////////////////////////////////////////////////////////////////// if(`VIRTMEM_SUPPORTED) begin : VIRTMEM_SUPPORTED - hptw hptw(.clk, .reset, .StallW, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF, + hptw hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF, .DTLBMissM, .DTLBWriteM, .InstrDAPageFaultF, .DataDAPageFaultM, .FlushW, .DCacheStallM, .SATP_REGW, .PCF, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW, .ReadDataM(ReadDataM[`XLEN-1:0]), .WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M, .IEUAdrExtM, .PTE, .IHWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM, - .IHAdrM, .CPUBusy, .HPTWStall, .SelHPTW, + .IHAdrM, .HPTWStall, .SelHPTW, .IgnoreRequestTLB, .LSULoadAccessFaultM, .LSUStoreAmoAccessFaultM, .LoadAccessFaultM, .StoreAmoAccessFaultM, .HPTWInstrAccessFaultM); end else begin assign {HPTWStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, IgnoreRequestTLB} = '0; - assign CPUBusy = StallW; assign PreLSURWM = MemRWM; + assign PreLSURWM = MemRWM; assign IHAdrM = IEUAdrExtM; assign LSUFunct3M = Funct3M; assign LSUFunct7M = Funct7M; assign LSUAtomicM = AtomicM; assign IHWriteDataM = WriteDataM; @@ -155,6 +155,7 @@ module lsu ( // There is not a clean way to restore back to a partial executed instruction. CommiteedM will // delay the interrupt until the LSU is in a clean state. assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM; + assign CPUBusy = StallW & ~SelHPTW; // MMU and Misalignment fault logic required if privileged unit exists if(`ZICSR_SUPPORTED == 1) begin : dmmu diff --git a/pipelined/src/mmu/hptw.sv b/pipelined/src/mmu/hptw.sv index 1430cc869..688f88f95 100644 --- a/pipelined/src/mmu/hptw.sv +++ b/pipelined/src/mmu/hptw.sv @@ -31,7 +31,7 @@ `include "wally-config.vh" module hptw ( - input logic clk, reset, StallW, + input logic clk, reset, input logic [`XLEN-1:0] SATP_REGW, // includes SATP.MODE to determine number of levels in page table input logic [`XLEN-1:0] PCF, // addresses to translate input logic [`XLEN+1:0] IEUAdrExtM, // addresses to translate @@ -61,7 +61,6 @@ module hptw ( output logic [6:0] LSUFunct7M, output logic IgnoreRequestTLB, output logic SelHPTW, - output logic CPUBusy, output logic HPTWStall, input logic LSULoadAccessFaultM, LSUStoreAmoAccessFaultM, output logic LoadAccessFaultM, StoreAmoAccessFaultM, HPTWInstrAccessFaultM @@ -291,7 +290,6 @@ module hptw ( // to the orignal data virtual address. assign SelHPTWAdr = SelHPTW & ~(DTLBWriteM | ITLBWriteF); // always block interrupts when using the hardware page table walker. - assign CPUBusy = StallW & ~SelHPTW; // multiplex the outputs to LSU if(`XLEN == 64) assign HPTWAdrExt = {{(`XLEN+2-`PA_BITS){1'b0}}, HPTWAdr}; // extend to 66 bits From 232f866ad1aa95f12bbf51782441c8f857adfe74 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 11 Dec 2022 15:49:34 -0600 Subject: [PATCH 2/6] Renamed CPUBusy to Stall in cache. --- pipelined/src/cache/cachefsm.sv | 6 +++--- pipelined/src/ifu/ifu.sv | 2 +- pipelined/src/lsu/lsu.sv | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 12fd3ade5..860432c82 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -40,7 +40,7 @@ module cachefsm input logic FlushCache, input logic InvalidateCache, // hazard inputs - input logic CPUBusy, + input logic Stall, // Bus inputs input logic CacheBusAck, // dcache internals @@ -130,7 +130,7 @@ module cachefsm //STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_READY; STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_MISS_READ_DELAY; //else NextState = STATE_READY; - STATE_MISS_READ_DELAY: if(CPUBusy) NextState = STATE_MISS_READ_DELAY; + STATE_MISS_READ_DELAY: if(Stall) NextState = STATE_MISS_READ_DELAY; else NextState = STATE_READY; STATE_MISS_EVICT_DIRTY: if(CacheBusAck) NextState = STATE_MISS_FETCH_WDV; else NextState = STATE_MISS_EVICT_DIRTY; @@ -201,6 +201,6 @@ module cachefsm resetDelay; assign SelFetchBuffer = CurrState == STATE_MISS_WRITE_CACHE_LINE | CurrState == STATE_MISS_READ_DELAY; - assign ce = (CurrState == STATE_READY & ~CPUBusy | CacheStall) | (CurrState != STATE_READY) | reset; + assign ce = (CurrState == STATE_READY & ~Stall | CacheStall) | (CurrState != STATE_READY) | reset; endmodule // cachefsm diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 8da0dd51c..ba8ea1904 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -221,7 +221,7 @@ module ifu ( cache #(.LINELEN(`ICACHE_LINELENINBITS), .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS), .NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0)) - icache(.clk, .reset, .FlushStage(TrapM), .CPUBusy, + icache(.clk, .reset, .FlushStage(TrapM), .Stall(CPUBusy), .FetchBuffer, .CacheBusAck(ICacheBusAck), .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), .CacheBusRW, diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index e9ef4558a..920a9a22c 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -254,7 +254,7 @@ module lsu ( cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), .NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`LLEN), .DCACHE(1)) dcache( - .clk, .reset, .CPUBusy, .SelBusBeat, .FlushStage(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM), + .clk, .reset, .Stall(CPUBusy), .SelBusBeat, .FlushStage(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM), .FlushCache(CacheFlushM), .NextAdr(IEUAdrE[11:0]), .PAdr(PAdrM), .ByteMask(ByteMaskM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]), .CacheWriteData(LSUWriteDataM), .SelHPTW, From 6d573b32d2c787a5fc1cb37b6d4a7942ab363449 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 11 Dec 2022 15:51:35 -0600 Subject: [PATCH 3/6] Changed CPUBusy to Stall in ebu modules. --- pipelined/src/cache/cache.sv | 4 ++-- pipelined/src/ebu/ahbcacheinterface.sv | 4 ++-- pipelined/src/ebu/ahbinterface.sv | 4 ++-- pipelined/src/ebu/buscachefsm.sv | 4 ++-- pipelined/src/ebu/busfsm.sv | 4 ++-- pipelined/src/ifu/ifu.sv | 4 ++-- pipelined/src/lsu/lsu.sv | 4 ++-- 7 files changed, 14 insertions(+), 14 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index 321129357..6c7aa8994 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -35,7 +35,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE input logic reset, // cpu side input logic FlushStage, - input logic CPUBusy, + input logic Stall, input logic [1:0] CacheRW, input logic [1:0] CacheAtomic, input logic FlushCache, @@ -194,7 +194,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE // Cache FSM ///////////////////////////////////////////////////////////////////////////////////////////// cachefsm cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck, - .FlushStage, .CacheRW, .CacheAtomic, .CPUBusy, + .FlushStage, .CacheRW, .CacheAtomic, .Stall, .CacheHit, .LineDirty, .CacheStall, .CacheCommitted, .CacheMiss, .CacheAccess, .SelAdr, .ClearValid, .ClearDirty, .SetDirty, diff --git a/pipelined/src/ebu/ahbcacheinterface.sv b/pipelined/src/ebu/ahbcacheinterface.sv index 530cdb42c..9c01b0354 100644 --- a/pipelined/src/ebu/ahbcacheinterface.sv +++ b/pipelined/src/ebu/ahbcacheinterface.sv @@ -64,7 +64,7 @@ module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE input logic Flush, input logic [`PA_BITS-1:0] PAdr, input logic [1:0] BusRW, - input logic CPUBusy, + input logic Stall, input logic [2:0] Funct3, output logic SelBusBeat, output logic BusStall, @@ -114,7 +114,7 @@ module ahbcacheinterface #(parameter BEATSPERLINE, LINELEN, LOGWPL, CACHE_ENABLE buscachefsm #(BeatCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm( - .HCLK, .HRESETn, .Flush, .BusRW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat, + .HCLK, .HRESETn, .Flush, .BusRW, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat, .CacheBusRW, .CacheBusAck, .BeatCount, .BeatCountDelayed, .HREADY, .HTRANS, .HWRITE, .HBURST); endmodule diff --git a/pipelined/src/ebu/ahbinterface.sv b/pipelined/src/ebu/ahbinterface.sv index 9955cca5a..0505cfc55 100644 --- a/pipelined/src/ebu/ahbinterface.sv +++ b/pipelined/src/ebu/ahbinterface.sv @@ -51,7 +51,7 @@ module ahbinterface #(parameter LSU = 0) // **** modify to use LSU/ifu parameter input logic [1:0] BusRW, input logic [`XLEN/8-1:0] ByteMask, input logic [`XLEN-1:0] WriteData, - input logic CPUBusy, + input logic Stall, output logic BusStall, output logic BusCommitted, output logic [(LSU ? `XLEN : 32)-1:0] FetchBuffer); @@ -73,6 +73,6 @@ module ahbinterface #(parameter LSU = 0) // **** modify to use LSU/ifu parameter end busfsm busfsm(.HCLK, .HRESETn, .Flush, .BusRW, - .BusCommitted, .CPUBusy, .BusStall, .CaptureEn, .HREADY, + .BusCommitted, .Stall, .BusStall, .CaptureEn, .HREADY, .HTRANS, .HWRITE); endmodule diff --git a/pipelined/src/ebu/buscachefsm.sv b/pipelined/src/ebu/buscachefsm.sv index cddd74878..b89be6411 100644 --- a/pipelined/src/ebu/buscachefsm.sv +++ b/pipelined/src/ebu/buscachefsm.sv @@ -40,7 +40,7 @@ module buscachefsm #(parameter integer BeatCountThreshold, // IEU interface input logic Flush, input logic [1:0] BusRW, - input logic CPUBusy, + input logic Stall, output logic BusCommitted, output logic BusStall, output logic CaptureEn, @@ -89,7 +89,7 @@ module buscachefsm #(parameter integer BeatCountThreshold, else NextState = ADR_PHASE; DATA_PHASE: if(HREADY) NextState = MEM3; else NextState = DATA_PHASE; - MEM3: if(CPUBusy) NextState = MEM3; + MEM3: if(Stall) NextState = MEM3; else NextState = ADR_PHASE; CACHE_FETCH: if(HREADY & FinalBeatCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK; else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH; diff --git a/pipelined/src/ebu/busfsm.sv b/pipelined/src/ebu/busfsm.sv index 8203fa74e..d2f9447e3 100644 --- a/pipelined/src/ebu/busfsm.sv +++ b/pipelined/src/ebu/busfsm.sv @@ -38,7 +38,7 @@ module busfsm // IEU interface input logic Flush, input logic [1:0] BusRW, - input logic CPUBusy, + input logic Stall, output logic BusCommitted, output logic BusStall, output logic CaptureEn, @@ -65,7 +65,7 @@ module busfsm else NextState = ADR_PHASE; DATA_PHASE: if(HREADY) NextState = MEM3; else NextState = DATA_PHASE; - MEM3: if(CPUBusy) NextState = MEM3; + MEM3: if(Stall) NextState = MEM3; else NextState = ADR_PHASE; default: NextState = ADR_PHASE; endcase diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index ba8ea1904..f80d411e9 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -243,7 +243,7 @@ module ifu ( .BeatCount(), .Cacheable(CacheableF), .SelBusBeat(), .WriteDataM('0), .CacheBusAck(ICacheBusAck), .HWDATA(), .CacheableOrFlushCacheM(1'b0), .CacheReadDataWordM('0), .FetchBuffer, .PAdr(PCPF), - .BusRW, .CPUBusy, + .BusRW, .Stall(CPUBusy), .BusStall, .BusCommitted(BusCommittedF)); mux3 #(32) UnCachedDataMux(.d0(ICacheInstrF), .d1(FetchBuffer[32-1:0]), .d2(IROMInstrF), @@ -260,7 +260,7 @@ module ifu ( ahbinterface #(0) ahbinterface(.HCLK(clk), .Flush(TrapM), .HRESETn(~reset), .HREADY(IFUHREADY), .HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(), .HWSTRB(), .BusRW, .ByteMask(), .WriteData('0), - .CPUBusy, .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer)); + .Stall(CPUBusy), .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer)); assign CacheCommittedF = '0; if(`IROM_SUPPORTED) mux2 #(32) UnCachedDataMux2(FetchBuffer, IROMInstrF, SelIROM, InstrRawF); diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 920a9a22c..28860012a 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -270,7 +270,7 @@ module lsu ( .BeatCount, .SelBusBeat, .CacheReadDataWordM(DCacheReadDataWordM), .WriteDataM(LSUWriteDataM), .Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheBusRW, .CacheableOrFlushCacheM, .CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(PAdrM), - .Cacheable(CacheableOrFlushCacheM), .BusRW, .CPUBusy, + .Cacheable(CacheableOrFlushCacheM), .BusRW, .Stall(CPUBusy), .BusStall, .BusCommitted(BusCommittedM)); // FetchBuffer[`AHBW-1:0] needs to be duplicated LLENPOVERAHBW times. @@ -293,7 +293,7 @@ module lsu ( ahbinterface #(1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HREADY(LSUHREADY), .HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB), .BusRW, .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM), - .CPUBusy, .BusStall, .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer)); + .Stall(CPUBusy), .BusStall, .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer)); if(`DTIM_SUPPORTED) mux2 #(`XLEN) ReadDataMux2(FetchBuffer, DTIMReadDataWordM, SelDTIM, ReadDataWordMuxM); else assign ReadDataWordMuxM = FetchBuffer[`XLEN-1:0]; From 5b38b4e63980956db8eb5a9d269feb8eb86c7b17 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 11 Dec 2022 15:52:51 -0600 Subject: [PATCH 4/6] Renamed CPUBusy in LSU. --- pipelined/src/lsu/lsu.sv | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 28860012a..9b43102ba 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -103,7 +103,7 @@ module lsu ( logic [6:0] LSUFunct7M; logic [1:0] LSUAtomicM; (* mark_debug = "true" *) logic [`XLEN+1:0] IHAdrM; - logic CPUBusy; + logic GatedStallW; logic DCacheStallM; logic CacheableM; logic BusStall; @@ -155,7 +155,7 @@ module lsu ( // There is not a clean way to restore back to a partial executed instruction. CommiteedM will // delay the interrupt until the LSU is in a clean state. assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM; - assign CPUBusy = StallW & ~SelHPTW; + assign GatedStallW = StallW & ~SelHPTW; // MMU and Misalignment fault logic required if privileged unit exists if(`ZICSR_SUPPORTED == 1) begin : dmmu @@ -219,7 +219,7 @@ module lsu ( assign DTIMMemRWM = SelDTIM & ~IgnoreRequestTLB ? LSURWM : '0; // **** fix ReadDataWordM to be LLEN. ByteMask is wrong length. // **** create config to support DTIM with floating point. - dtim dtim(.clk, .reset, .ce(~CPUBusy), .MemRWM(DTIMMemRWM), + dtim dtim(.clk, .reset, .ce(~GatedStallW), .MemRWM(DTIMMemRWM), .Adr(DTIMAdr), .FlushW, .WriteDataM(LSUWriteDataM), .ReadDataWordM(DTIMReadDataWordM[`XLEN-1:0]), .ByteMaskM(ByteMaskM[`XLEN/8-1:0])); @@ -254,7 +254,7 @@ module lsu ( cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), .NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`LLEN), .DCACHE(1)) dcache( - .clk, .reset, .Stall(CPUBusy), .SelBusBeat, .FlushStage(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM), + .clk, .reset, .Stall(GatedStallW), .SelBusBeat, .FlushStage(FlushW), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM), .FlushCache(CacheFlushM), .NextAdr(IEUAdrE[11:0]), .PAdr(PAdrM), .ByteMask(ByteMaskM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]), .CacheWriteData(LSUWriteDataM), .SelHPTW, @@ -270,7 +270,7 @@ module lsu ( .BeatCount, .SelBusBeat, .CacheReadDataWordM(DCacheReadDataWordM), .WriteDataM(LSUWriteDataM), .Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheBusRW, .CacheableOrFlushCacheM, .CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdr(PAdrM), - .Cacheable(CacheableOrFlushCacheM), .BusRW, .Stall(CPUBusy), + .Cacheable(CacheableOrFlushCacheM), .BusRW, .Stall(GatedStallW), .BusStall, .BusCommitted(BusCommittedM)); // FetchBuffer[`AHBW-1:0] needs to be duplicated LLENPOVERAHBW times. @@ -293,7 +293,7 @@ module lsu ( ahbinterface #(1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HREADY(LSUHREADY), .HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB), .BusRW, .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM), - .Stall(CPUBusy), .BusStall, .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer)); + .Stall(GatedStallW), .BusStall, .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer)); if(`DTIM_SUPPORTED) mux2 #(`XLEN) ReadDataMux2(FetchBuffer, DTIMReadDataWordM, SelDTIM, ReadDataWordMuxM); else assign ReadDataWordMuxM = FetchBuffer[`XLEN-1:0]; From ad7dd56180d699e1b8a447357a82464b3a6d5feb Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 11 Dec 2022 15:54:19 -0600 Subject: [PATCH 5/6] Renamed CPUBusy to GatedStallF in IFU. --- pipelined/src/ifu/ifu.sv | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index f80d411e9..24f6f3636 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -113,7 +113,7 @@ module ifu ( logic ICacheFetchLine; logic BusStall; logic ICacheStallF, IFUCacheBusStallF; - logic CPUBusy; + logic GatedStallF; (* mark_debug = "true" *) logic [31:0] PostSpillInstrRawF; // branch predictor signal logic [`XLEN-1:0] PCNext1F, PCNext2F, PCNext0F; @@ -199,7 +199,7 @@ module ifu ( // The IROM uses untranslated addresses, so it is not compatible with virtual memory. if (`IROM_SUPPORTED) begin : irom assign IFURWF = 2'b10; - irom irom(.clk, .reset, .ce(~CPUBusy | reset), .Adr(PCNextFSpill[`XLEN-1:0]), .ReadData(IROMInstrF)); + irom irom(.clk, .reset, .ce(~GatedStallF | reset), .Adr(PCNextFSpill[`XLEN-1:0]), .ReadData(IROMInstrF)); end else begin assign IFURWF = 2'b10; @@ -221,7 +221,7 @@ module ifu ( cache #(.LINELEN(`ICACHE_LINELENINBITS), .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS), .NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0)) - icache(.clk, .reset, .FlushStage(TrapM), .Stall(CPUBusy), + icache(.clk, .reset, .FlushStage(TrapM), .Stall(GatedStallF), .FetchBuffer, .CacheBusAck(ICacheBusAck), .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), .CacheBusRW, @@ -243,7 +243,7 @@ module ifu ( .BeatCount(), .Cacheable(CacheableF), .SelBusBeat(), .WriteDataM('0), .CacheBusAck(ICacheBusAck), .HWDATA(), .CacheableOrFlushCacheM(1'b0), .CacheReadDataWordM('0), .FetchBuffer, .PAdr(PCPF), - .BusRW, .Stall(CPUBusy), + .BusRW, .Stall(GatedStallF), .BusStall, .BusCommitted(BusCommittedF)); mux3 #(32) UnCachedDataMux(.d0(ICacheInstrF), .d1(FetchBuffer[32-1:0]), .d2(IROMInstrF), @@ -260,7 +260,7 @@ module ifu ( ahbinterface #(0) ahbinterface(.HCLK(clk), .Flush(TrapM), .HRESETn(~reset), .HREADY(IFUHREADY), .HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(), .HWSTRB(), .BusRW, .ByteMask(), .WriteData('0), - .Stall(CPUBusy), .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer)); + .Stall(GatedStallF), .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer)); assign CacheCommittedF = '0; if(`IROM_SUPPORTED) mux2 #(32) UnCachedDataMux2(FetchBuffer, IROMInstrF, SelIROM, InstrRawF); @@ -277,7 +277,7 @@ module ifu ( assign IFUCacheBusStallF = ICacheStallF | BusStall; assign IFUStallF = IFUCacheBusStallF | SelNextSpillF; - assign CPUBusy = StallF & ~SelNextSpillF; + assign GatedStallF = StallF & ~SelNextSpillF; flopenl #(32) AlignedInstrRawDFlop(clk, reset, ~StallD, FlushD ? nop : PostSpillInstrRawF, nop, InstrRawD); From dbc3dac03dba5936b299ca0f8e749779eef72060 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sun, 11 Dec 2022 16:28:11 -0600 Subject: [PATCH 6/6] Removed unused flushf. --- pipelined/src/hazard/hazard.sv | 3 +-- pipelined/src/ifu/bpred.sv | 4 ++-- pipelined/src/ifu/ifu.sv | 4 ++-- pipelined/src/ifu/localHistoryPredictor.sv | 4 ++-- pipelined/src/wally/wallypipelinedcore.sv | 6 +++--- 5 files changed, 10 insertions(+), 11 deletions(-) diff --git a/pipelined/src/hazard/hazard.sv b/pipelined/src/hazard/hazard.sv index 0bd5cbe48..b22795608 100644 --- a/pipelined/src/hazard/hazard.sv +++ b/pipelined/src/hazard/hazard.sv @@ -41,7 +41,7 @@ module hazard( (* mark_debug = "true" *) input logic wfiM, IntPendingM, // Stall & flush outputs (* mark_debug = "true" *) output logic StallF, StallD, StallE, StallM, StallW, -(* mark_debug = "true" *) output logic FlushF, FlushD, FlushE, FlushM, FlushW +(* mark_debug = "true" *) output logic FlushD, FlushE, FlushM, FlushW ); logic StallFCause, StallDCause, StallECause, StallMCause, StallWCause; @@ -89,7 +89,6 @@ module hazard( assign FirstUnstalledW = ~StallW & StallM; // Each stage flushes if the previous stage is the last one stalled (for cause) or the system has reason to flush - assign #1 FlushF = BPPredWrongE; assign #1 FlushD = FirstUnstalledD | TrapM | RetM | BPPredWrongE; assign #1 FlushE = FirstUnstalledE | TrapM | RetM | BPPredWrongE; // *** why is BPPredWrongE here, but not needed in simple processor assign #1 FlushM = FirstUnstalledM | TrapM | RetM; diff --git a/pipelined/src/ifu/bpred.sv b/pipelined/src/ifu/bpred.sv index 2e306dc60..908d9a6bc 100644 --- a/pipelined/src/ifu/bpred.sv +++ b/pipelined/src/ifu/bpred.sv @@ -36,7 +36,7 @@ module bpred (input logic clk, reset, input logic StallF, StallD, StallE, StallM, - input logic FlushF, FlushD, FlushE, FlushM, + input logic FlushD, FlushE, FlushM, // Fetch stage // the prediction input logic [31:0] InstrD, @@ -103,7 +103,7 @@ module bpred else if (`BPTYPE == "BPLOCALPAg") begin:Predictor localHistoryPredictor DirPredictor(.clk, - .reset, .StallF, .StallE, .FlushF, + .reset, .StallF, .StallE, .LookUpPC(PCNextF), .Prediction(BPPredF), // update diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 24f6f3636..e7851d8b7 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -34,7 +34,7 @@ module ifu ( input logic clk, reset, input logic StallF, StallD, StallE, StallM, - input logic FlushF, FlushD, FlushE, FlushM, FlushW, + input logic FlushD, FlushE, FlushM, FlushW, // Bus interface (* mark_debug = "true" *) input logic [`XLEN-1:0] HRDATA, (* mark_debug = "true" *) output logic [`PA_BITS-1:0] IFUHADDR, @@ -309,7 +309,7 @@ module ifu ( logic [`XLEN-1:0] BPPredPCF; bpred bpred(.clk, .reset, .StallF, .StallD, .StallE, .StallM, - .FlushF, .FlushD, .FlushE, .FlushM, + .FlushD, .FlushE, .FlushM, .InstrD, .PCNextF, .BPPredPCF, .SelBPPredF, .PCE, .PCSrcE, .IEUAdrE, .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .BPPredWrongM, .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM); diff --git a/pipelined/src/ifu/localHistoryPredictor.sv b/pipelined/src/ifu/localHistoryPredictor.sv index 836bca9ad..757985868 100644 --- a/pipelined/src/ifu/localHistoryPredictor.sv +++ b/pipelined/src/ifu/localHistoryPredictor.sv @@ -38,7 +38,7 @@ module localHistoryPredictor ) (input logic clk, input logic reset, - input logic StallF, StallE, FlushF, + input logic StallF, StallE, input logic [`XLEN-1:0] LookUpPC, output logic [1:0] Prediction, // update @@ -116,7 +116,7 @@ module localHistoryPredictor flopenrc #(k) LHRFReg(.clk(clk), .reset(reset), .en(~StallF), - .clear(FlushF), + .clear(1'b0), .d(ForwardLHRNext), .q(LHRF)); /* diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index d189a0b1c..076088857 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -53,7 +53,7 @@ module wallypipelinedcore ( // logic [1:0] ForwardAE, ForwardBE; logic StallF, StallD, StallE, StallM, StallW; - logic FlushF, FlushD, FlushE, FlushM, FlushW; + logic FlushD, FlushE, FlushM, FlushW; logic RetM; (* mark_debug = "true" *) logic TrapM; @@ -170,7 +170,7 @@ module wallypipelinedcore ( ifu ifu( .clk, .reset, .StallF, .StallD, .StallE, .StallM, - .FlushF, .FlushD, .FlushE, .FlushM, .FlushW, + .FlushD, .FlushE, .FlushM, .FlushW, // Fetch .HRDATA, .PCF, .IFUHADDR, .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, @@ -325,7 +325,7 @@ module wallypipelinedcore ( .wfiM, .IntPendingM, // Stall & flush outputs .StallF, .StallD, .StallE, .StallM, .StallW, - .FlushF, .FlushD, .FlushE, .FlushM, .FlushW + .FlushD, .FlushE, .FlushM, .FlushW ); // global stall and flush control if (`ZICSR_SUPPORTED) begin:priv