mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
fix controller typo
This commit is contained in:
parent
45af9398cd
commit
e49ca99c9d
@ -93,7 +93,11 @@ module controller import cvw::*; #(parameter cvw_t P) (
|
|||||||
output logic CSRWriteFenceM, // CSR write or fence instruction; needs to flush the following instructions
|
output logic CSRWriteFenceM, // CSR write or fence instruction; needs to flush the following instructions
|
||||||
output logic [4:0] RdE, RdM, // Pipelined destination registers
|
output logic [4:0] RdE, RdM, // Pipelined destination registers
|
||||||
// Forwarding controls
|
// Forwarding controls
|
||||||
output logic [4:0] RdW // Register destinations in Execute, Memory, or Writeback stage
|
output logic [4:0] RdW, // Register destinations in Execute, Memory, or Writeback stage
|
||||||
|
// Debug scan chain
|
||||||
|
input logic DebugScanEn,
|
||||||
|
input logic DebugScanIn,
|
||||||
|
output logic DebugScanOut
|
||||||
);
|
);
|
||||||
|
|
||||||
logic [4:0] Rs1E; // pipelined register sources
|
logic [4:0] Rs1E; // pipelined register sources
|
||||||
|
Loading…
Reference in New Issue
Block a user