diff --git a/wally-pipelined/src/dmem/dmem.sv b/wally-pipelined/src/dmem/dmem.sv
index aa4327c21..679fc884b 100644
--- a/wally-pipelined/src/dmem/dmem.sv
+++ b/wally-pipelined/src/dmem/dmem.sv
@@ -51,25 +51,19 @@ module dmem (
   output logic             StoreMisalignedFaultM, StoreAccessFaultM,
   // TLB management
   //input logic  [`XLEN-1:0] PageTableEntryM,
+  input logic  [`XLEN-1:0] SATP_REGW,
   //input logic              DTLBWriteM, DTLBFlushM,
-  // *** satp value will come from CSRs
-  // input logic [`XLEN-1:0] SATP,
   output logic             DTLBMissM, DTLBHitM
 );
 
   logic             SquashSCM;
 
-  // Initially no MMU
-  // *** temporary hack until we can figure out how to get actual satp value
-  // from priv unit -- Thomas F
-  logic [`XLEN-1:0] SATP = '0;
   // *** temporary hack until walker is hooked up -- Thomas F
   logic  [`XLEN-1:0] PageTableEntryM = '0;
   logic DTLBFlushM = '0;
   logic DTLBWriteM = '0;
-  tlb #(3) dtlb(clk, reset, SATP, MemAdrM, PageTableEntryM, DTLBWriteM,
+  tlb #(3) dtlb(clk, reset, SATP_REGW, MemAdrM, PageTableEntryM, DTLBWriteM,
     DTLBFlushM, MemPAdrM, DTLBMissM, DTLBHitM);
-  //assign MemPAdrM = MemAdrM;
 
 	// Determine if an Unaligned access is taking place
 	always_comb
diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv
index d91acc5c0..bc4e6d1b7 100644
--- a/wally-pipelined/src/ebu/ahblite.sv
+++ b/wally-pipelined/src/ebu/ahblite.sv
@@ -44,6 +44,8 @@ module ahblite (
   input  logic             MemReadM, MemWriteM,
   input  logic [`XLEN-1:0] WriteDataM,
   input  logic [1:0]       MemSizeM,
+  // Signals from MMU ***
+  // MMUPAdr;
   // Return from bus
   output logic [`XLEN-1:0] ReadDataW,
   // AHB-Lite external signals
@@ -64,6 +66,7 @@ module ahblite (
   output logic             HWRITED,
   // Stalls
   output logic             InstrStall,/*InstrUpdate, */DataStall
+  // *** add a chip-level ready signal as part of handshake
 );
 
   logic GrantData;
@@ -75,7 +78,7 @@ module ahblite (
   assign HCLK = clk;
   assign HRESETn = ~reset;
 
-  // *** initially support HABW = XLEN
+  // *** initially support AHBW = XLEN
 
   // track bus state
   // Data accesses have priority over instructions.  However, if a data access comes
diff --git a/wally-pipelined/src/ebu/pagetablewalker.sv b/wally-pipelined/src/ebu/pagetablewalker.sv_dev
similarity index 84%
rename from wally-pipelined/src/ebu/pagetablewalker.sv
rename to wally-pipelined/src/ebu/pagetablewalker.sv_dev
index 4b42a4c96..eaed09482 100644
--- a/wally-pipelined/src/ebu/pagetablewalker.sv
+++ b/wally-pipelined/src/ebu/pagetablewalker.sv_dev
@@ -1,5 +1,5 @@
 ///////////////////////////////////////////
-// ahblite.sv
+// pagetablewalker.sv
 //
 // Written: tfleming@hmc.edu 2 March 2021
 // Modified: 
@@ -29,16 +29,17 @@
 module pagetablewalker (
   input  logic             clk, reset,
 
-  input  logic [`XLEN-1:0] satp,
+  input  logic [`XLEN-1:0] SATP_REGW,
 
-  input  logic             TLBMissF,
+  input  logic             ITLBMissF, DTLBMissM,
   input  logic [`XLEN-1:0] TranslationVAdr,
 
   input  logic             HCLK, HRESETn,
 
   input  logic             HREADY,
 
-  output logic [`XLEN-1:0] PageTableEntryF,
+  output logic [`XLEN-1:0] PageTableEntryF, PageTableEntryM,
+  output logic             ITLBWriteF, DTLBWriteM,
   output logic             TranslationComplete
 );
 
@@ -52,15 +53,15 @@ module pagetablewalker (
   endgenerate
   */
 
-  logic Sv_Mode = satp[31];
-  logic BasePageTablePPN [21:0] = satp[21:0];
+  logic Sv_Mode = SATP_REGW[31];
+  logic BasePageTablePPN [21:0] = SATP_REGW[21:0];
 
   logic VPN1 [9:0] = TranslationVAdr[31:22];
   logic VPN0 [9:0] = TranslationVAdr[21:12]; // *** could optimize by not passing offset?
 
   logic TranslationPAdr [33:0];
 
-  typedef enum {IDLE, LEVEL1, LEVEL0, LEAF, FAULT} statetype;
+  typedef enum {IDLE, DATA_LEVEL1, DATA_LEVEL0, DATA_LEAF, DATA FAULT} statetype;
   statetype WalkerState, NextWalkerState;
 
   always_ff @(posedge HCLK, negedge HRESETn)
@@ -92,11 +93,14 @@ module pagetablewalker (
       case (NextWalkerState)
         LEVEL1: TranslationPAdr <= {BasePageTablePPN, VPN1, 2'b00};
         LEVEL2: TranslationPAdr <= {CurrentPPN, VPN0, 2'b00};
-        LEAF:   PageTableEntryF <= CurrentPageTableEntry;
-                TranslationComplete <= '1;
+        LEAF: begin
+          PageTableEntryF <= CurrentPageTableEntry;
+          TranslationComplete <= '1;
+          end
+      endcase
     end
 
-  assign #1 Translate = (NextWalkerState = LEVEL1);
+  assign #1 Translate = (NextWalkerState == LEVEL1);
 
 
 endmodule
\ No newline at end of file
diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv
index 88e4f0bef..fe275bc01 100644
--- a/wally-pipelined/src/ifu/ifu.sv
+++ b/wally-pipelined/src/ifu/ifu.sv
@@ -54,9 +54,8 @@ module ifu (
   output logic [`XLEN-1:0] InstrMisalignedAdrM,
   // TLB management
   //input logic  [`XLEN-1:0] PageTableEntryF,
+  input logic  [`XLEN-1:0] SATP_REGW,
   //input logic              ITLBWriteF, ITLBFlushF,
-  // *** satp value will come from CSRs
-  // input logic [`XLEN-1:0] SATP,
   output logic             ITLBMissF, ITLBHitF,
   // bogus
   input  logic [15:0] rd2
@@ -71,14 +70,11 @@ module ifu (
   logic [31:0]     InstrF, InstrRawD, InstrE, InstrW;
   logic [31:0]     nop = 32'h00000013; // instruction for NOP
 
-  // *** temporary hack until we can figure out how to get actual satp value
-  // from priv unit -- Thomas F
-  logic [`XLEN-1:0] SATP = '0;
   // *** temporary hack until walker is hooked up -- Thomas F
   logic  [`XLEN-1:0] PageTableEntryF = '0;
   logic ITLBFlushF = '0;
   logic ITLBWriteF = '0;
-  tlb #(3) itlb(clk, reset, SATP, PCF, PageTableEntryF, ITLBWriteF, ITLBFlushF,
+  tlb #(3) itlb(clk, reset, SATP_REGW, PCF, PageTableEntryF, ITLBWriteF, ITLBFlushF,
     InstrPAdrF, ITLBMissF, ITLBHitF);
 
   // *** put memory interface on here, InstrF becomes output
diff --git a/wally-pipelined/src/privileged/csr.sv b/wally-pipelined/src/privileged/csr.sv
index f1f16ac97..5d3c24a49 100644
--- a/wally-pipelined/src/privileged/csr.sv
+++ b/wally-pipelined/src/privileged/csr.sv
@@ -40,6 +40,7 @@ module csr (
   output logic             STATUS_SPP, STATUS_TSR,
   output logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW,
   output logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW, 
+  output logic [`XLEN-1:0] SATP_REGW,
   output logic [11:0]      MIP_REGW, MIE_REGW,
   output logic             STATUS_MIE, STATUS_SIE,
   input  logic [4:0]       SetFflagsM,
@@ -126,6 +127,7 @@ module csr (
       assign MIDELEG_REGW = 0;
       assign SEDELEG_REGW = 0;
       assign SIDELEG_REGW = 0;
+      assign SATP_REGW = 0;
       assign MIP_REGW = 0;
       assign MIE_REGW = 0;
       assign STATUS_MIE = 0;
diff --git a/wally-pipelined/src/privileged/csrs.sv b/wally-pipelined/src/privileged/csrs.sv
index 8301eed51..8f688cc1b 100644
--- a/wally-pipelined/src/privileged/csrs.sv
+++ b/wally-pipelined/src/privileged/csrs.sv
@@ -48,6 +48,7 @@ module csrs #(parameter
     output logic [`XLEN-1:0] CSRSReadValM, SEPC_REGW, STVEC_REGW, 
     output logic [31:0]      SCOUNTEREN_REGW,     
     output logic [`XLEN-1:0] SEDELEG_REGW, SIDELEG_REGW, 
+    output logic [`XLEN-1:0] SATP_REGW,
     input  logic [11:0]      SIP_REGW, SIE_REGW,
     output logic             WriteSSTATUSM,
     output logic             IllegalCSRSAccessM
@@ -63,7 +64,7 @@ module csrs #(parameter
       logic WriteSTVECM;
       logic WriteSSCRATCHM, WriteSEPCM;
       logic WriteSCAUSEM, WriteSTVALM, WriteSATPM, WriteSCOUNTERENM;
-      logic [`XLEN-1:0] SSCRATCH_REGW, SCAUSE_REGW, STVAL_REGW, SATP_REGW;
+      logic [`XLEN-1:0] SSCRATCH_REGW, SCAUSE_REGW, STVAL_REGW;
       
       assign WriteSSTATUSM = CSRSWriteM && (CSRAdrM == SSTATUS);
       assign WriteSTVECM = CSRSWriteM && (CSRAdrM == STVEC);
@@ -123,6 +124,7 @@ module csrs #(parameter
       assign SEDELEG_REGW = 0;
       assign SIDELEG_REGW = 0;
       assign SCOUNTEREN_REGW = 0;
+      assign SATP_REGW = 0;
       assign IllegalCSRSAccessM = 1;
     end
   endgenerate
diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv
index 71b905865..a01fa557c 100644
--- a/wally-pipelined/src/privileged/privileged.sv
+++ b/wally-pipelined/src/privileged/privileged.sv
@@ -44,6 +44,7 @@ module privileged (
   input  logic             TimerIntM, ExtIntM, SwIntM,
   input  logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM,
   input  logic [4:0]       SetFflagsM,
+  output logic [`XLEN-1:0] SATP_REGW,
   output logic [2:0]       FRM_REGW,
   input  logic             FlushD, FlushE, FlushM, StallD, StallW
 );
diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv
index ded4df3d8..e2014653b 100644
--- a/wally-pipelined/src/wally/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wally/wallypipelinedhart.sv
@@ -88,8 +88,12 @@ module wallypipelinedhart (
   logic       SquashSCW;
 
   // memory management unit signals
+  logic             ITLBWriteF, DTLBWriteM;
   logic             ITLBMissF, ITLBHitF;
   logic             DTLBMissM, DTLBHitM;
+  logic [`XLEN-1:0] SATP_REGW;
+
+  logic [`XLEN-1:0] PageTableEntryF, PageTableEntryM;
 
   // bus interface to dmem
   logic             MemReadM, MemWriteM;
@@ -114,6 +118,8 @@ module wallypipelinedhart (
     .MemSizeM(Funct3M[1:0]), .UnsignedLoadM(Funct3M[2]),
     .*);
 
+  // walker walker(.*); *** // can send addresses to ahblite, send out pagetablestall
+  // *** can connect to hazard unit
 // changing from this to the line above breaks the program.  auipc at 104 fails; seems to be flushed.
 // Would need to insertinstruction as InstrD, not InstrF
     /*ahblite ebu(