diff --git a/README.md b/README.md index 88b388350..45e503d94 100644 --- a/README.md +++ b/README.md @@ -5,7 +5,7 @@ Wally is a 5-stage pipelined processor configurable to support all the standard ![Wally block diagram](wallyriscvTopAll.png) -Wally is described in a textbook, RISC-V System-on-Chip Design, by Harris, Stine, Thompson, and Harris. See Appendix D for directions installing the RISC-V tool chain needed to use Wally. +Wally is described in a textbook, RISC-V System-on-Chip Design, by Harris, Stine, Thompson, and Harris. Users should follow the setup instructions below. A system administrator must install CAD tools using the directions further down. New users may wish to do the following setup to access the server via a GUI and use a text editor. @@ -18,9 +18,17 @@ New users may wish to do the following setup to access the server via a GUI and Then follow Section 2.2 to clone the repo, source setup, make the tests and run regression + If you don't already have a Github account, create one + In a web browser, visit https://github.com/openhwgroup/cvw + In the upper right part of the screen, click on Fork + Create a fork, choosing the owner as your github account and the repository as cvw. + + On the Linux computer where you will be working, log in, clone your fork of the repo, + run the setup script, and build the tests: + $ cd - $ git clone --recurse-submodules https://github.com/davidharrishmc/riscv-wally - $ cd riscv-wally + $ git clone --recurse-submodules https://github.com//cvw + $ cd cvw $ source ./setup.sh $ make $ cd pipelined/regression @@ -28,8 +36,8 @@ Then follow Section 2.2 to clone the repo, source setup, make the tests and run Add the following lines to your .bashrc or .bash_profile - if [ -f ~/riscv-wally/setup.sh ]; then - source ~/riscv-wally/setup.sh + if [ -f ~/cvw/setup.sh ]; then + source ~/cvw/setup.sh fi # Tool-chain Installation (Sys Admin) diff --git a/setup.sh b/setup.sh index dc1f418d5..27ed893db 100755 --- a/setup.sh +++ b/setup.sh @@ -2,7 +2,7 @@ # setup.sh # David_Harris@hmc.edu and kekim@hmc.edu 1 December 2021 -# Set up tools for riscv-wally +# Set up tools for rvw echo "Executing Wally setup.sh" @@ -15,14 +15,15 @@ echo \$WALLY set to ${WALLY} # Must edit these based on your local environment. Ask your sysadmin. export MGLS_LICENSE_FILE=1717@solidworks.eng.hmc.edu # Change this to your Siemens license server export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server -export PATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin:$PATH # Change this for your path to Questa -export PATH=/cad/synopsys/SYN/bin:$PATH # Change this for your path to Design Compiler - +export QUESTAPATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin # Change this for your path to Questa +export SNPSPATH=/cad/synopsys/SYN/bin # Change this for your path to Design Compiler # Path to RISC-V Tools export RISCV=/opt/riscv # change this if you installed the tools in a different location # Tools +# Questa and Synopsys +export PATH=$QUESTAPATH:$SNPSPATH:$PATH # GCC export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RISCV/riscv-gnu-toolchain/lib:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib export PATH=$PATH:$RISCV/riscv-gnu-toolchain/bin:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/bin # GCC tools diff --git a/tests/riscof/spike/spike_rv32imc_isa.yaml b/tests/riscof/spike/spike_rv32imc_isa.yaml index 3438e17a0..478bbe56d 100644 --- a/tests/riscof/spike/spike_rv32imc_isa.yaml +++ b/tests/riscof/spike/spike_rv32imc_isa.yaml @@ -1,6 +1,7 @@ hart_ids: [0] hart0: - ISA: RV32IMAFDCZicsr_Zifencei_Zba_Zbb_Zbc_Zbs + ISA: RV32IMAFDCZicsr_Zifencei +# ISA: RV32IMAFDCZicsr_Zifencei_Zba_Zbb_Zbc_Zbs physical_addr_sz: 32 User_Spec_Version: '2.3' supported_xlen: [32] diff --git a/tests/riscof/spike/spike_rv64gc_isa.yaml b/tests/riscof/spike/spike_rv64gc_isa.yaml index a8837ac76..8037ad6f6 100644 --- a/tests/riscof/spike/spike_rv64gc_isa.yaml +++ b/tests/riscof/spike/spike_rv64gc_isa.yaml @@ -1,6 +1,7 @@ hart_ids: [0] hart0: - ISA: RV64IMAFDCSUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs + ISA: RV64IMAFDCSUZicsr_Zifencei +# ISA: RV64IMAFDCSUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs physical_addr_sz: 56 User_Spec_Version: '2.3' supported_xlen: [64]