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Added signed division to fdivsqrt

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cturek 2022-10-26 16:13:41 +00:00
parent a8a89f8dfc
commit e401d12889
1 changed files with 3 additions and 0 deletions
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pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
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@ -55,6 +55,7 @@ module fdivsqrtpreproc (
logic [`DIVb+3:0] DivX; logic [`DIVb+3:0] DivX;
logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt; logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt;
logic [`NE+1:0] Qe; logic [`NE+1:0] Qe;
logic Signed;
// ***can probably merge X LZC with conversion // ***can probably merge X LZC with conversion
// cout the number of leading zeros // cout the number of leading zeros
@ -64,6 +65,8 @@ module fdivsqrtpreproc (
lzc #(`NF+1) lzcX (Xm, XZeroCnt); lzc #(`NF+1) lzcX (Xm, XZeroCnt);
lzc #(`NF+1) lzcY (Ym, YZeroCnt); lzc #(`NF+1) lzcY (Ym, YZeroCnt);
assign Signed = Funct3E[0];
assign PreprocX = Xm[`NF-1:0]<<XZeroCnt; assign PreprocX = Xm[`NF-1:0]<<XZeroCnt;
assign PreprocY = Ym[`NF-1:0]<<YZeroCnt; assign PreprocY = Ym[`NF-1:0]<<YZeroCnt;