From e3bb0d28206f8583875c3af2a51da3da5cfcc978 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Fri, 18 Aug 2023 16:32:22 -0500
Subject: [PATCH] Now we have invalidate, clean, and flush working.

---
 src/cache/cachefsm.sv      |  4 +-
 tests/custom/simple/cbom.s | 76 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 78 insertions(+), 2 deletions(-)

diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv
index 6d36b78ba..8628937e7 100644
--- a/src/cache/cachefsm.sv
+++ b/src/cache/cachefsm.sv
@@ -157,7 +157,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
   assign SetValid = CurrState == STATE_WRITE_LINE | 
                     (CurrState == STATE_READY & CMOp[3]); // *** RT: NOT completely right has to be a hit
   assign ClearValid = P.ZICBOM_SUPPORTED & ((CurrState == STATE_READY & CMOp[0]) |
-                      (CurrState == STATE_CMO_DONE & CMOp[2]));
+                      (CurrState == STATE_CMO_WRITEBACK & CMOp[2] & CacheBusAck));
   // coverage off -item e 1 -fecexprrow 8
   assign LRUWriteEn = (CurrState == STATE_READY & AnyHit) |
                       (CurrState == STATE_WRITE_LINE) & ~FlushStage;
@@ -167,7 +167,7 @@ module cachefsm import cvw::*; #(parameter cvw_t P,
   assign ClearDirty = (CurrState == STATE_WRITE_LINE & ~(CacheRW[0])) |   // exclusion-tag: icache ClearDirty
                       (CurrState == STATE_FLUSH & LineDirty) | // This is wrong in a multicore snoop cache protocal.  Dirty must be cleared concurrently and atomically with writeback.  For single core cannot clear after writeback on bus ack and change flushadr.  Clears the wrong set.
   // Flush and eviction controls
-                      (P.ZICBOM_SUPPORTED & CurrState == STATE_CMO_DONE & (CMOp[1] | CMOp[2]));
+                      (P.ZICBOM_SUPPORTED & CurrState == STATE_CMO_WRITEBACK & (CMOp[1] | CMOp[2]) & CacheBusAck);
   assign ZeroCacheLine = CurrState == STATE_READY & CMOp[3];  // *** RT: NOT completely right
   assign SelWriteback = (CurrState == STATE_WRITEBACK & ~CacheBusAck) |
                     (CurrState == STATE_READY & AnyMiss & LineDirty);
diff --git a/tests/custom/simple/cbom.s b/tests/custom/simple/cbom.s
index 2cd90949a..e2c89284e 100644
--- a/tests/custom/simple/cbom.s
+++ b/tests/custom/simple/cbom.s
@@ -264,6 +264,77 @@ CBOMTest_clean_step9_check_all:
         sd a0, 0(s0)     # should be -1
         addi s0, s0, 8
 
+        ################################################################################
+        # Flush D$ line
+        ################################################################################
+
+        # theory of operation
+        # 1. Read several cachelines of data from memory into the d cache and copy to a second region of memory
+        # 2. Then verify the second region has the same data
+        # 3. For flush there is no way to create a negative control. We will flush 1 cache line
+        # 4. Verify whole region
+        # 5. Flush the remaining lines
+        # 6. Verify whole region
+
+        # step 1
+CBOMTest_flush_step1: 
+        la a0, SourceData
+        la a1, Destination3
+        li a2, 64
+        jal ra, memcpy8
+
+        # step 2 All should be valid
+CBOMTest_flush_step2_verify:
+        la a0, SourceData
+        la a1, Destination3
+        li a2, 64
+        jal ra, memcmp8
+        sd a0, 0(s0)     # should be -1
+        addi s0, s0, 8
+
+        # step 3 # flush 1 line
+CBOMTest_flush_step3:
+        la a1, Destination3
+        cbo.flush (a1)
+
+        # step 4 
+CBOMTest_flush_step4_verify:
+        la a0, SourceData
+        la a1, Destination3
+        li a2, 64
+        jal ra, memcmp8
+        sd a0, 0(s0)     # should be -1
+        addi s0, s0, 8
+
+        # step 5
+CBOMTest_flush_step5_flush_all:
+        la a1, Destination3
+        cbo.flush (a1)
+        la a1, Destination3+64
+        cbo.flush (a1)
+        la a1, Destination3+128
+        cbo.flush (a1)
+        la a1, Destination3+192
+        cbo.flush (a1)
+        la a1, Destination3+256
+        cbo.flush (a1)
+        la a1, Destination3+320
+        cbo.flush (a1)
+        la a1, Destination3+384
+        cbo.flush (a1)
+        la a1, Destination3+448
+        cbo.flush (a1)
+	
+        # step 6
+CBOMTest_flush_step6_verify:
+        la a0, SourceData
+        la a1, Destination3
+        li a2, 64
+        jal ra, memcmp8
+        sd a0, 0(s0)     # should be -1
+        addi s0, s0, 8
+        
+
         ld s0, 0(sp)
         ld ra, 8(sp)
         addi sp, sp, 16
@@ -349,3 +420,8 @@ Destination4:
 signature:
         .fill 16, 8, 0x0bad0bad0bad0bad
 
+
+ExceptedSignature:
+        .fill 13, 8, 0xFFFFFFFFFFFFFFFF
+        .fill 3,  8, 0x0bad0bad0bad0bad
+