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Fixed typos

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cturek 2022-06-01 00:07:36 +00:00
parent efe4b3e8fe
commit e3a0ee333f
2 changed files with 7 additions and 7 deletions
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2
addins/riscv-arch-test

@ -1 +1 @@
Subproject commit be67c99bd461742aa1c100bcc0732657faae2230 Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86

2
pipelined/srt/srt.sv
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@ -44,7 +44,7 @@ module srt #(parameter Nf=52) (
input logic [1:0] Fmt, // Floats: 00 = 16 bit, 01 = 32 bit, 10 = 64 bit, 11 = 128 bit input logic [1:0] Fmt, // Floats: 00 = 16 bit, 01 = 32 bit, 10 = 64 bit, 11 = 128 bit
input logic W64, // 32-bit ints on XLEN=64 input logic W64, // 32-bit ints on XLEN=64
input logic Signed, // Interpret integers as signed 2's complement input logic Signed, // Interpret integers as signed 2's complement
input logic Int, // Choose integer inputss input logic Int, // Choose integer inputs
input logic Sqrt, // perform square root, not divide input logic Sqrt, // perform square root, not divide
output logic rsign, output logic rsign,
output logic [Nf-1:0] Quot, Rem, QuotOTFC, // *** later handle integers output logic [Nf-1:0] Quot, Rem, QuotOTFC, // *** later handle integers