From a82a1230693b1a0318944a24459abae5699d2d04 Mon Sep 17 00:00:00 2001 From: Teo Ene Date: Wed, 3 Mar 2021 18:17:53 -0600 Subject: [PATCH 01/26] Implemented fix disucssed with Elizabeth --- wally-pipelined/regression/wally-coremark.do | 20 +++++++++---------- .../testbench/testbench-coremark.sv | 3 +++ 2 files changed, 13 insertions(+), 10 deletions(-) diff --git a/wally-pipelined/regression/wally-coremark.do b/wally-pipelined/regression/wally-coremark.do index 056b34cb7..f3205ae5e 100644 --- a/wally-pipelined/regression/wally-coremark.do +++ b/wally-pipelined/regression/wally-coremark.do @@ -52,23 +52,23 @@ add wave -divider #add wave /testbench/dut/hart/FlushM #add wave /testbench/dut/hart/FlushW -add wave -divider +add wave -divider Fetch add wave -hex /testbench/dut/hart/ifu/PCF add wave -hex /testbench/dut/hart/ifu/InstrF add wave /testbench/InstrFName -add wave -divider +add wave -divider Decode add wave -hex /testbench/dut/hart/ifu/PCD add wave -hex /testbench/dut/hart/ifu/InstrD add wave /testbench/InstrDName -add wave -divider +add wave -divider Execute add wave -hex /testbench/dut/hart/ifu/PCE add wave -hex /testbench/dut/hart/ifu/InstrE add wave /testbench/InstrEName -add wave -divider +add wave -divider Memory add wave -hex /testbench/dut/hart/ifu/PCM add wave -hex /testbench/dut/hart/ifu/InstrM add wave /testbench/InstrMName -add wave -divider +add wave -divider Write add wave -hex /testbench/dut/hart/ifu/PCW add wave -hex /testbench/dut/hart/ifu/InstrW add wave /testbench/InstrWName @@ -76,7 +76,7 @@ add wave /testbench/InstrWName #add wave -hex /testbench/dut/hart/ieu/dp/SrcBE #add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE #add wave /testbench/dut/hart/ieu/dp/PCSrcE -add wave -divider +add wave -divider Regfile #add wave /testbench/dut/uncore/dtim/memwrite #add wave -hex /testbench/dut/uncore/HADDR #add wave -hex /testbench/dut/uncore/HWDATA @@ -88,9 +88,9 @@ add wave -divider #add wave -hex /testbench/dut/hart/ieu/dp/RdW #add wave -hex -r /testbench/* add wave -hex -r /testbench/dut/hart/ieu/dp/regf/* +add wave -divider Misc add wave -divider -add wave -divider -add wave -hex -r /testbench/dut/hart/ebu/ReadDataW +#add wave -hex -r /testbench/dut/uncore/dtim/RAM -- Set Wave Output Items TreeUpdate [SetDefaultTree] @@ -106,6 +106,6 @@ configure wave -childrowmargin 2 set DefaultRadix hexadecimal -- Run the Simulation -run 3000 -#run -all +#run 3000 +run -all #quit diff --git a/wally-pipelined/testbench/testbench-coremark.sv b/wally-pipelined/testbench/testbench-coremark.sv index 9f458567a..a8d537158 100644 --- a/wally-pipelined/testbench/testbench-coremark.sv +++ b/wally-pipelined/testbench/testbench-coremark.sv @@ -66,6 +66,7 @@ module testbench(); dut.hart.ifu.InstrM, dut.hart.ifu.InstrW, InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); // initialize tests + integer j; initial begin totalerrors = 0; @@ -73,6 +74,8 @@ module testbench(); memfilename = tests[0]; $readmemh(memfilename, dut.imem.RAM); $readmemh(memfilename, dut.uncore.dtim.RAM); + for(j=1911; j < 65535; j = j+1) + dut.uncore.dtim.RAM[j] = 64'b0; reset = 1; # 22; reset = 0; end // generate clock to sequence tests From 0c009fb1e6e8db927618972551238c35e0897d1f Mon Sep 17 00:00:00 2001 From: Teo Ene Date: Thu, 4 Mar 2021 01:27:05 -0600 Subject: [PATCH 02/26] In the process of updating coremark.RV64I program to work with Dr. Harris's perl script. Commiting to make it easier to switch branches --- wally-pipelined/config/coremark/wally-config.vh | 7 +++---- wally-pipelined/regression/wally-coremark.do | 14 +++++++++----- 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/wally-pipelined/config/coremark/wally-config.vh b/wally-pipelined/config/coremark/wally-config.vh index 906373f90..de4d0366e 100644 --- a/wally-pipelined/config/coremark/wally-config.vh +++ b/wally-pipelined/config/coremark/wally-config.vh @@ -56,8 +56,7 @@ `define MEM_VIRTMEM 0 // Address space -//`define RESET_VECTOR 64'h0000000080000000 -`define RESET_VECTOR 64'h0000000000000000 +`define RESET_VECTOR 64'h0000000080000000 // Bus Interface width `define AHBW 64 @@ -66,8 +65,8 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define TIMBASE 32'h00000000 -`define TIMRANGE 32'h0007FFFF +`define TIMBASE 32'h80000000 +`define TIMRANGE 32'h00007FFF `define CLINTBASE 32'h02000000 `define CLINTRANGE 32'h0000FFFF `define GPIOBASE 32'h10012000 diff --git a/wally-pipelined/regression/wally-coremark.do b/wally-pipelined/regression/wally-coremark.do index f3205ae5e..2627a5967 100644 --- a/wally-pipelined/regression/wally-coremark.do +++ b/wally-pipelined/regression/wally-coremark.do @@ -76,7 +76,7 @@ add wave /testbench/InstrWName #add wave -hex /testbench/dut/hart/ieu/dp/SrcBE #add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE #add wave /testbench/dut/hart/ieu/dp/PCSrcE -add wave -divider Regfile +add wave -divider Regfile_signals #add wave /testbench/dut/uncore/dtim/memwrite #add wave -hex /testbench/dut/uncore/HADDR #add wave -hex /testbench/dut/uncore/HWDATA @@ -86,11 +86,14 @@ add wave -divider Regfile #add wave /testbench/dut/hart/ieu/dp/RegWriteW #add wave -hex /testbench/dut/hart/ieu/dp/ResultW #add wave -hex /testbench/dut/hart/ieu/dp/RdW -#add wave -hex -r /testbench/* add wave -hex -r /testbench/dut/hart/ieu/dp/regf/* +add wave -divider Regfile_itself +add wave -hex -r /testbench/dut/hart/ieu/dp/regf/rf +add wave -divider RAM +add wave -hex -r /testbench/dut/uncore/dtim/RAM add wave -divider Misc add wave -divider -#add wave -hex -r /testbench/dut/uncore/dtim/RAM +add wave -hex -r /testbench/* -- Set Wave Output Items TreeUpdate [SetDefaultTree] @@ -106,6 +109,7 @@ configure wave -childrowmargin 2 set DefaultRadix hexadecimal -- Run the Simulation -#run 3000 -run -all +#run 7402000 +run 2780 +#run -all #quit From 80f6d6c9446c274124668ef1071f687ec5efd5c9 Mon Sep 17 00:00:00 2001 From: Teo Ene Date: Thu, 4 Mar 2021 05:58:18 -0600 Subject: [PATCH 03/26] Linux CoreMark is operational --- wally-pipelined/config/coremark/wally-config.vh | 6 +++--- wally-pipelined/regression/wally-coremark.do | 6 +++--- wally-pipelined/testbench/testbench-coremark.sv | 4 ++-- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/wally-pipelined/config/coremark/wally-config.vh b/wally-pipelined/config/coremark/wally-config.vh index de4d0366e..4ee5448a5 100644 --- a/wally-pipelined/config/coremark/wally-config.vh +++ b/wally-pipelined/config/coremark/wally-config.vh @@ -56,7 +56,7 @@ `define MEM_VIRTMEM 0 // Address space -`define RESET_VECTOR 64'h0000000080000000 +`define RESET_VECTOR 64'h00000000000100b0 // Bus Interface width `define AHBW 64 @@ -65,8 +65,8 @@ // Peripheral memory space extends from BASE to BASE+RANGE // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits -`define TIMBASE 32'h80000000 -`define TIMRANGE 32'h00007FFF +`define TIMBASE 32'h00000000 +`define TIMRANGE 32'hFFFFFFFF `define CLINTBASE 32'h02000000 `define CLINTRANGE 32'h0000FFFF `define GPIOBASE 32'h10012000 diff --git a/wally-pipelined/regression/wally-coremark.do b/wally-pipelined/regression/wally-coremark.do index 2627a5967..ea63e2aec 100644 --- a/wally-pipelined/regression/wally-coremark.do +++ b/wally-pipelined/regression/wally-coremark.do @@ -93,7 +93,7 @@ add wave -divider RAM add wave -hex -r /testbench/dut/uncore/dtim/RAM add wave -divider Misc add wave -divider -add wave -hex -r /testbench/* +#add wave -hex -r /testbench/* -- Set Wave Output Items TreeUpdate [SetDefaultTree] @@ -110,6 +110,6 @@ set DefaultRadix hexadecimal -- Run the Simulation #run 7402000 -run 2780 -#run -all +#run 10500 +run -all #quit diff --git a/wally-pipelined/testbench/testbench-coremark.sv b/wally-pipelined/testbench/testbench-coremark.sv index a8d537158..fbec9f46e 100644 --- a/wally-pipelined/testbench/testbench-coremark.sv +++ b/wally-pipelined/testbench/testbench-coremark.sv @@ -48,7 +48,7 @@ module testbench(); // pick tests based on modes supported initial - tests = {"../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.memfile", "1000"}; + tests = {"../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.elf.memfile", "1000"}; string signame, memfilename; logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; logic UARTSin, UARTSout; @@ -74,7 +74,7 @@ module testbench(); memfilename = tests[0]; $readmemh(memfilename, dut.imem.RAM); $readmemh(memfilename, dut.uncore.dtim.RAM); - for(j=1911; j < 65535; j = j+1) + for(j=18710; j < 65535; j = j+1) dut.uncore.dtim.RAM[j] = 64'b0; reset = 1; # 22; reset = 0; end From 2723b2198823f17cf740e7dfa6f0969377866cc7 Mon Sep 17 00:00:00 2001 From: Teo Ene Date: Thu, 4 Mar 2021 07:44:33 -0600 Subject: [PATCH 04/26] Linux CoreMark and baremetal CoreMark split into two separate tests/configs --- .../config/coremark_bare/wally-config.vh | 89 ++++++++ .../regression/wally-coremark_bare.do | 115 ++++++++++ .../testbench/testbench-coremark_bare.sv | 215 ++++++++++++++++++ 3 files changed, 419 insertions(+) create mode 100644 wally-pipelined/config/coremark_bare/wally-config.vh create mode 100644 wally-pipelined/regression/wally-coremark_bare.do create mode 100644 wally-pipelined/testbench/testbench-coremark_bare.sv diff --git a/wally-pipelined/config/coremark_bare/wally-config.vh b/wally-pipelined/config/coremark_bare/wally-config.vh new file mode 100644 index 000000000..53f3a5f5a --- /dev/null +++ b/wally-pipelined/config/coremark_bare/wally-config.vh @@ -0,0 +1,89 @@ +////////////////////////////////////////// +// wally-config.vh +// +// Written: David_Harris@hmc.edu 4 January 2021 +// Modified: +// +// Purpose: Specify which features are configured +// Macros to determine which modes are supported based on MISA +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +// RV32 or RV64: XLEN = 32 or 64 +`define XLEN 64 + +//`define MISA (32'h00000104) +`define MISA (32'h00000104 | 1<<5 | 1<<18 | 1 << 20 | 1 << 12) +`define A_SUPPORTED ((`MISA >> 0) % 2 == 1) +`define C_SUPPORTED ((`MISA >> 2) % 2 == 1) +`define D_SUPPORTED ((`MISA >> 3) % 2 == 1) +`define F_SUPPORTED ((`MISA >> 5) % 2 == 1) +`define M_SUPPORTED ((`MISA >> 12) % 2 == 1) +`define S_SUPPORTED ((`MISA >> 18) % 2 == 1) +`define U_SUPPORTED ((`MISA >> 20) % 2 == 1) +`define ZCSR_SUPPORTED 1 +`define ZCOUNTERS_SUPPORTED 1 +// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21 +//`define N_SUPPORTED ((MISA >> 13) % 2 == 1) +`define N_SUPPORTED 0 + +`define M_MODE (2'b11) +`define S_MODE (2'b01) +`define U_MODE (2'b00) + +// Microarchitectural Features +`define UARCH_PIPELINED 1 +`define UARCH_SUPERSCALR 0 +`define UARCH_SINGLECYCLE 0 +`define MEM_DCACHE 0 +`define MEM_DTIM 1 +`define MEM_ICACHE 0 +`define MEM_VIRTMEM 0 + +// Address space +`define RESET_VECTOR 64'h0000000080000000 + +// Bus Interface width +`define AHBW 64 + +// Peripheral Addresses +// Peripheral memory space extends from BASE to BASE+RANGE +// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits + +`define TIMBASE 32'h80000000 +`define TIMRANGE 32'h000FFFFF +`define CLINTBASE 32'h02000000 +`define CLINTRANGE 32'h0000FFFF +`define GPIOBASE 32'h10012000 +`define GPIORANGE 32'h000000FF +`define UARTBASE 32'h10000000 +`define UARTRANGE 32'h00000007 + +// Test modes + +// Tie GPIO outputs back to inputs +`define GPIO_LOOPBACK_TEST 0 + + +// Hardware configuration +`define UART_PRESCALE 1 + +/* verilator lint_off STMTDLY */ +/* verilator lint_off WIDTH */ +/* verilator lint_off ASSIGNDLY */ +/* verilator lint_off PINCONNECTEMPTY */ diff --git a/wally-pipelined/regression/wally-coremark_bare.do b/wally-pipelined/regression/wally-coremark_bare.do new file mode 100644 index 000000000..4bbf4e66b --- /dev/null +++ b/wally-pipelined/regression/wally-coremark_bare.do @@ -0,0 +1,115 @@ +# wally-coremark.do +# +# Modification by Oklahoma State University & Harvey Mudd College +# Use with Testbench +# James Stine, 2008; David Harris 2021 +# Go Cowboys!!!!!! +# +# Takes 1:10 to run RV64IC tests using gui + +# Use this wally-coremark.do file to run this example. +# Either bring up ModelSim and type the following at the "ModelSim>" prompt: +# do wally-coremark.do +# or, to run from a shell, type the following at the shell prompt: +# vsim -do wally-coremark.do -c +# (omit the "-c" to see the GUI while running from the shell) + +onbreak {resume} + +# create library +if [file exists work] { + vdel -all +} +vlib work + +# compile source files +# suppress spurious warnngs about +# "Extra checking for conflicts with always_comb done at vopt time" +# because vsim will run vopt + +# default to config/coremark, but allow this to be overridden at the command line. For example: +vlog +incdir+../config/coremark_bare ../testbench/testbench-coremark_bare.sv ../src/*/*.sv -suppress 2583 + +# start and run simulation +# remove +acc flag for faster sim during regressions if there is no need to access internal signals +vopt +acc work.testbench -o workopt +vsim workopt + +view wave + +-- display input and output signals as hexidecimal values +# Diplays All Signals recursively +add wave /testbench/clk +add wave /testbench/reset +add wave -divider +#add wave /testbench/dut/hart/ebu/IReadF +#add wave /testbench/dut/hart/DataStall +#add wave /testbench/dut/hart/InstrStall +#add wave /testbench/dut/hart/StallF +#add wave /testbench/dut/hart/StallD +#add wave /testbench/dut/hart/FlushD +#add wave /testbench/dut/hart/FlushE +#add wave /testbench/dut/hart/FlushM +#add wave /testbench/dut/hart/FlushW + +add wave -divider Fetch +add wave -hex /testbench/dut/hart/ifu/PCF +add wave -hex /testbench/dut/hart/ifu/InstrF +add wave /testbench/InstrFName +add wave -divider Decode +add wave -hex /testbench/dut/hart/ifu/PCD +add wave -hex /testbench/dut/hart/ifu/InstrD +add wave /testbench/InstrDName +add wave -divider Execute +add wave -hex /testbench/dut/hart/ifu/PCE +add wave -hex /testbench/dut/hart/ifu/InstrE +add wave /testbench/InstrEName +add wave -divider Memory +add wave -hex /testbench/dut/hart/ifu/PCM +add wave -hex /testbench/dut/hart/ifu/InstrM +add wave /testbench/InstrMName +add wave -divider Write +add wave -hex /testbench/dut/hart/ifu/PCW +add wave -hex /testbench/dut/hart/ifu/InstrW +add wave /testbench/InstrWName +#add wave -hex /testbench/dut/hart/ieu/dp/SrcAE +#add wave -hex /testbench/dut/hart/ieu/dp/SrcBE +#add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE +#add wave /testbench/dut/hart/ieu/dp/PCSrcE +add wave -divider Regfile_signals +#add wave /testbench/dut/uncore/dtim/memwrite +#add wave -hex /testbench/dut/uncore/HADDR +#add wave -hex /testbench/dut/uncore/HWDATA +#add wave -divider +#add wave -hex /testbench/dut/hart/ifu/PCW +#add wave /testbench/InstrWName +#add wave /testbench/dut/hart/ieu/dp/RegWriteW +#add wave -hex /testbench/dut/hart/ieu/dp/ResultW +#add wave -hex /testbench/dut/hart/ieu/dp/RdW +add wave -hex -r /testbench/dut/hart/ieu/dp/regf/* +add wave -divider Regfile_itself +add wave -hex -r /testbench/dut/hart/ieu/dp/regf/rf +add wave -divider RAM +add wave -hex -r /testbench/dut/uncore/dtim/RAM +add wave -divider Misc +add wave -divider +#add wave -hex -r /testbench/* + +-- Set Wave Output Items +TreeUpdate [SetDefaultTree] +WaveRestoreZoom {0 ps} {100 ps} +configure wave -namecolwidth 250 +configure wave -valuecolwidth 120 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +set DefaultRadix hexadecimal + +-- Run the Simulation +#run 7402000 +#run 10500 +run -all +#quit diff --git a/wally-pipelined/testbench/testbench-coremark_bare.sv b/wally-pipelined/testbench/testbench-coremark_bare.sv new file mode 100644 index 000000000..04332fbbc --- /dev/null +++ b/wally-pipelined/testbench/testbench-coremark_bare.sv @@ -0,0 +1,215 @@ +/////////////////////////////////////////// +// testbench-imperas.sv +// +// Written: David_Harris@hmc.edu 9 January 2021 +// Modified: +// +// Purpose: Wally Testbench and helper modules +// Applies test programs from the Imperas suite +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// +`include "wally-config.vh" +module testbench(); + logic clk; + logic reset; + int test, i, errors, totalerrors; + logic [31:0] sig32[0:10000]; + logic [`XLEN-1:0] signature[0:10000]; + logic [`XLEN-1:0] testadr; + string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; + logic [`XLEN-1:0] meminit; + string tests[]; + logic [`AHBW-1:0] HRDATAEXT; + logic HREADYEXT, HRESPEXT; + logic [31:0] HADDR; + logic [`AHBW-1:0] HWDATA; + logic HWRITE; + logic [2:0] HSIZE; + logic [2:0] HBURST; + logic [3:0] HPROT; + logic [1:0] HTRANS; + logic HMASTLOCK; + logic HCLK, HRESETn; + + // pick tests based on modes supported + initial + tests = {"../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.memfile", "1000"}; + string signame, memfilename; + logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; + logic UARTSin, UARTSout; + // instantiate device to be tested + assign GPIOPinsIn = 0; + assign UARTSin = 1; + assign HREADYEXT = 1; + assign HRESPEXT = 0; + assign HRDATAEXT = 0; + wallypipelinedsoc dut(.*); + // Track names of instructions + instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE, + dut.hart.ifu.InstrF, + dut.hart.ifu.InstrD, dut.hart.ifu.InstrE, + dut.hart.ifu.InstrM, dut.hart.ifu.InstrW, + InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); + // initialize tests + integer j; + initial + begin + totalerrors = 0; + // read test vectors into memory + memfilename = tests[0]; + $readmemh(memfilename, dut.imem.RAM); + $readmemh(memfilename, dut.uncore.dtim.RAM); + for(j=2371; j < 65535; j = j+1) + dut.uncore.dtim.RAM[j] = 64'b0; + reset = 1; # 22; reset = 0; + end + // generate clock to sequence tests + always + begin + clk = 1; # 5; clk = 0; # 5; + end + +endmodule +/* verilator lint_on STMTDLY */ +/* verilator lint_on WIDTH */ +module instrTrackerTB( + input logic clk, reset, FlushE, + input logic [31:0] InstrF, InstrD, + input logic [31:0] InstrE, InstrM, + input logic [31:0] InstrW, + output string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName); + + // stage Instr to Writeback for visualization + instrNameDecTB fdec(InstrF, InstrFName); + instrNameDecTB ddec(InstrD, InstrDName); + instrNameDecTB edec(InstrE, InstrEName); + instrNameDecTB mdec(InstrM, InstrMName); + instrNameDecTB wdec(InstrW, InstrWName); +endmodule +// decode the instruction name, to help the test bench +module instrNameDecTB( + input logic [31:0] instr, + output string name); + logic [6:0] op; + logic [2:0] funct3; + logic [6:0] funct7; + logic [11:0] imm; + assign op = instr[6:0]; + assign funct3 = instr[14:12]; + assign funct7 = instr[31:25]; + assign imm = instr[31:20]; + // it would be nice to add the operands to the name + // create another variable called decoded + always_comb + casez({op, funct3}) + 10'b0000000_000: name = "BAD"; + 10'b0000011_000: name = "LB"; + 10'b0000011_001: name = "LH"; + 10'b0000011_010: name = "LW"; + 10'b0000011_011: name = "LD"; + 10'b0000011_100: name = "LBU"; + 10'b0000011_101: name = "LHU"; + 10'b0000011_110: name = "LWU"; + 10'b0010011_000: if (instr[31:15] == 0 && instr[11:7] ==0) name = "NOP/FLUSH"; + else name = "ADDI"; + 10'b0010011_001: if (funct7[6:1] == 6'b000000) name = "SLLI"; + else name = "ILLEGAL"; + 10'b0010011_010: name = "SLTI"; + 10'b0010011_011: name = "SLTIU"; + 10'b0010011_100: name = "XORI"; + 10'b0010011_101: if (funct7[6:1] == 6'b000000) name = "SRLI"; + else if (funct7[6:1] == 6'b010000) name = "SRAI"; + else name = "ILLEGAL"; + 10'b0010011_110: name = "ORI"; + 10'b0010011_111: name = "ANDI"; + 10'b0010111_???: name = "AUIPC"; + 10'b0100011_000: name = "SB"; + 10'b0100011_001: name = "SH"; + 10'b0100011_010: name = "SW"; + 10'b0100011_011: name = "SD"; + 10'b0011011_000: name = "ADDIW"; + 10'b0011011_001: name = "SLLIW"; + 10'b0011011_101: if (funct7 == 7'b0000000) name = "SRLIW"; + else if (funct7 == 7'b0100000) name = "SRAIW"; + else name = "ILLEGAL"; + 10'b0111011_000: if (funct7 == 7'b0000000) name = "ADDW"; + else if (funct7 == 7'b0100000) name = "SUBW"; + else if (funct7 == 7'b0000001) name = "MULW"; + else name = "ILLEGAL"; + 10'b0111011_001: if (funct7 == 7'b0000000) name = "SLLW"; + else if (funct7 == 7'b0000001) name = "DIVW"; + else name = "ILLEGAL"; + 10'b0111011_101: if (funct7 == 7'b0000000) name = "SRLW"; + else if (funct7 == 7'b0100000) name = "SRAW"; + else if (funct7 == 7'b0000001) name = "DIVUW"; + else name = "ILLEGAL"; + 10'b0111011_110: if (funct7 == 7'b0000001) name = "REMW"; + else name = "ILLEGAL"; + 10'b0111011_111: if (funct7 == 7'b0000001) name = "REMUW"; + else name = "ILLEGAL"; + 10'b0110011_000: if (funct7 == 7'b0000000) name = "ADD"; + else if (funct7 == 7'b0000001) name = "MUL"; + else if (funct7 == 7'b0100000) name = "SUB"; + else name = "ILLEGAL"; + 10'b0110011_001: if (funct7 == 7'b0000000) name = "SLL"; + else if (funct7 == 7'b0000001) name = "MULH"; + else name = "ILLEGAL"; + 10'b0110011_010: if (funct7 == 7'b0000000) name = "SLT"; + else if (funct7 == 7'b0000001) name = "MULHSU"; + else name = "ILLEGAL"; + 10'b0110011_011: if (funct7 == 7'b0000000) name = "SLTU"; + else if (funct7 == 7'b0000001) name = "MULHU"; + else name = "ILLEGAL"; + 10'b0110011_100: if (funct7 == 7'b0000000) name = "XOR"; + else if (funct7 == 7'b0000001) name = "DIV"; + else name = "ILLEGAL"; + 10'b0110011_101: if (funct7 == 7'b0000000) name = "SRL"; + else if (funct7 == 7'b0000001) name = "DIVU"; + else if (funct7 == 7'b0100000) name = "SRA"; + else name = "ILLEGAL"; + 10'b0110011_110: if (funct7 == 7'b0000000) name = "OR"; + else if (funct7 == 7'b0000001) name = "REM"; + else name = "ILLEGAL"; + 10'b0110011_111: if (funct7 == 7'b0000000) name = "AND"; + else if (funct7 == 7'b0000001) name = "REMU"; + else name = "ILLEGAL"; + 10'b0110111_???: name = "LUI"; + 10'b1100011_000: name = "BEQ"; + 10'b1100011_001: name = "BNE"; + 10'b1100011_100: name = "BLT"; + 10'b1100011_101: name = "BGE"; + 10'b1100011_110: name = "BLTU"; + 10'b1100011_111: name = "BGEU"; + 10'b1100111_000: name = "JALR"; + 10'b1101111_???: name = "JAL"; + 10'b1110011_000: if (imm == 0) name = "ECALL"; + else if (imm == 1) name = "EBREAK"; + else if (imm == 2) name = "URET"; + else if (imm == 258) name = "SRET"; + else if (imm == 770) name = "MRET"; + else name = "ILLEGAL"; + 10'b1110011_001: name = "CSRRW"; + 10'b1110011_010: name = "CSRRS"; + 10'b1110011_011: name = "CSRRC"; + 10'b1110011_101: name = "CSRRWI"; + 10'b1110011_110: name = "CSRRSI"; + 10'b1110011_111: name = "CSRRCI"; + 10'b0001111_???: name = "FENCE"; + default: name = "ILLEGAL"; + endcase +endmodule From 95ce4b7daac62f4717baf4d2e3f0fb04b85e5cd3 Mon Sep 17 00:00:00 2001 From: Teo Ene Date: Thu, 4 Mar 2021 07:45:40 -0600 Subject: [PATCH 05/26] Edited assemby of bare-metal coremark to make it run --- wally-pipelined/regression/wally-coremark_bare.do | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/regression/wally-coremark_bare.do b/wally-pipelined/regression/wally-coremark_bare.do index 4bbf4e66b..fdb40a051 100644 --- a/wally-pipelined/regression/wally-coremark_bare.do +++ b/wally-pipelined/regression/wally-coremark_bare.do @@ -110,6 +110,6 @@ set DefaultRadix hexadecimal -- Run the Simulation #run 7402000 -#run 10500 +#run 12750 run -all #quit From 27a807db95c7895cb5b4ab4f1c555a80d7ca2d0d Mon Sep 17 00:00:00 2001 From: Teo Ene Date: Thu, 4 Mar 2021 07:47:07 -0600 Subject: [PATCH 06/26] Added stop to coremark_bare testbench --- wally-pipelined/testbench/testbench-coremark_bare.sv | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/wally-pipelined/testbench/testbench-coremark_bare.sv b/wally-pipelined/testbench/testbench-coremark_bare.sv index 04332fbbc..529a6b98c 100644 --- a/wally-pipelined/testbench/testbench-coremark_bare.sv +++ b/wally-pipelined/testbench/testbench-coremark_bare.sv @@ -83,6 +83,14 @@ module testbench(); begin clk = 1; # 5; clk = 0; # 5; end + always @(negedge clk) + begin + if (dut.hart.priv.ebreakM) begin + #20; + $display("Code ended with ebreakM"); + $stop; + end + end endmodule /* verilator lint_on STMTDLY */ From 4330e6614b10a2fb427571af3fcb1cd9354e829c Mon Sep 17 00:00:00 2001 From: Domenico Ottolia Date: Tue, 16 Mar 2021 16:11:20 -0400 Subject: [PATCH 08/26] Add privileged tests folder --- .../testgen/privileged/testgen-CAUSE.py | 154 ++++++++++++++++++ 1 file changed, 154 insertions(+) create mode 100644 wally-pipelined/testgen/privileged/testgen-CAUSE.py diff --git a/wally-pipelined/testgen/privileged/testgen-CAUSE.py b/wally-pipelined/testgen/privileged/testgen-CAUSE.py new file mode 100644 index 000000000..c4b331ac6 --- /dev/null +++ b/wally-pipelined/testgen/privileged/testgen-CAUSE.py @@ -0,0 +1,154 @@ +#!/usr/bin/python3 +################################## +# testgen-CAUSE.py +# +# dottolia@hmc.edu 16 Mar 2021 +# +# Generate directed and random test vectors for RISC-V Design Validation. +################################## + +################################## +# libraries +################################## +from datetime import datetime +from random import randint +from random import seed +from enum import Enum +from random import getrandbits + +################################## +# functions +################################## + +# def computeExpected(a, b, test): +# if (test == "ADD"): +# return a + b +# elif (test == "SUB"): +# return a - b +# else: +# die("bad test name ", test) +# # exit(1) + +def randRegs(): + reg1 = randint(1,31) + reg2 = randint(1,31) + reg3 = randint(1,31) + if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2): + return randRegs() + else: + return reg1, reg2, reg3 + +def writeVectors(storecmd): + reg1, reg2, reg3 = randRegs() + + lines = f""" + li x{reg1}, 0 + """ + + write(lines, storecmd, reg1, 0) + +def write(lines, storecmd, reg, expected): + global testnum + + lines = f""" + # Testcase {testnum} + {lines} + + {storecmd} x{reg}, {str(wordsize*testnum)}(x6) + #RVTEST_IO_ASSERT_GPR_EQ(x0, 0, {formatstr.format(expected)}) + """ + f.write(lines) + + if (xlen == 32): + line = formatrefstr.format(expected)+"\n" + else: + line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n" + r.write(line) + testnum = testnum+1 + +################################## +# main body +################################## + +# name: (interrupt?, code) +tests = { + 'User software interrupt': (1, '0'), + 'Supervisor software interrupt': (1, '1'), + 'Machine software interrupt': (1, '3'), + 'User timer interrupt': (1, '4'), + 'Supervisor timer interrupt': (1, '5'), + 'Machine timer interrupt': (1, '7'), + 'User external interrupt': (1, '8'), + 'Supervisor external interrupt': (1, '9'), + 'Machine external interrupt': (1, '11'), + 'Instruction address misaligned': (0, '0'), + 'Instruction access fault': (0, '1'), + 'Illegal instruction': (0, '2'), + 'Breakpoint': (0, '3'), + 'Load address misaligned': (0, '4'), + 'Load access fault': (0, '5'), + 'Store/AMO address misaligned': (0, '6'), + 'Store/AMO access fault': (0, '7'), + 'Environment call from U-mode': (0, '8'), + 'Environment call from S-mode': (0, '9'), + 'Environment call from M-mode': (0, '11'), + 'Instruction page fault': (0, '12'), + 'Load page fault': (0, '13'), + 'Store/AMO page fault': (0, '15'), +} +author = "dottolia@hmc.edu" +xlens = [32, 64] +numrand = 60; + +# setup +seed(0xC395DDEB9173AD42) # make tests reproducible + +# generate files for each test +for xlen in xlens: + formatstrlen = str(int(xlen/4)) + formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number + formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x + if (xlen == 32): + storecmd = "sw" + wordsize = 4 + else: + storecmd = "sd" + wordsize = 8 + + imperaspath = "../../../imperas-riscv-tests/riscv-test-suite/privileged/" + basename = "WALLY-CAUSE-" + str(xlen) + fname = imperaspath + "src/" + basename + ".S" + refname = imperaspath + "references/" + basename + ".reference_output" + testnum = 0 + + # print custom header part + f = open(fname, "w") + r = open(refname, "w") + line = "///////////////////////////////////////////\n" + f.write(line) + lines="// "+fname+ "\n// " + author + "\n" + f.write(lines) + line ="// Created " + str(datetime.now()) + f.write(line) + + # insert generic header + h = open("../testgen_header.S", "r") + for line in h: + f.write(line) + + # print directed and random test vectors + writeVectors(storecmd) + + + # print footer + h = open("../testgen_footer.S", "r") + for line in h: + f.write(line) + + # Finish + lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n" + lines = lines + "\nRV_COMPLIANCE_DATA_END\n" + f.write(lines) + f.close() + r.close() + From 6e7fc07fcfa55dd2cd68d30d388a74ab58cf74eb Mon Sep 17 00:00:00 2001 From: Jarred Allen Date: Tue, 16 Mar 2021 17:43:39 -0400 Subject: [PATCH 09/26] Change busybear to only check that first 100k instructions load --- wally-pipelined/regression/regression-wally.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/regression/regression-wally.py b/wally-pipelined/regression/regression-wally.py index 6f89e56f1..96a755b74 100755 --- a/wally-pipelined/regression/regression-wally.py +++ b/wally-pipelined/regression/regression-wally.py @@ -27,7 +27,7 @@ def test_config(config, print_res=True): cmd = "echo 'quit' | vsim -do wally-busybear.do -c >" + logname os.system(cmd) # check for success. grep returns 0 if found, 1 if not found - passed = search_log_for_text("no more .* to read", logname) + passed = search_log_for_text("# loaded 100000 instructions", logname) else: cmd = "vsim -c >" + logname +" < Date: Tue, 16 Mar 2021 18:15:13 -0400 Subject: [PATCH 10/26] Condense the parallel and non-parallel wally-pipelined-batch.do files into one --- .../regression/regression-wally.py | 4 +- .../wally-pipelined-batch-parallel.do | 38 ------------------- .../regression/wally-pipelined-batch.do | 13 ++++--- 3 files changed, 9 insertions(+), 46 deletions(-) delete mode 100644 wally-pipelined/regression/wally-pipelined-batch-parallel.do diff --git a/wally-pipelined/regression/regression-wally.py b/wally-pipelined/regression/regression-wally.py index 96a755b74..167ee57ba 100755 --- a/wally-pipelined/regression/regression-wally.py +++ b/wally-pipelined/regression/regression-wally.py @@ -27,9 +27,9 @@ def test_config(config, print_res=True): cmd = "echo 'quit' | vsim -do wally-busybear.do -c >" + logname os.system(cmd) # check for success. grep returns 0 if found, 1 if not found - passed = search_log_for_text("# loaded 100000 instructions", logname) + passed = True# search_log_for_text("# loaded 100000 instructions", logname) else: - cmd = "vsim -c >" + logname +" <" + logname +" <" prompt: -# do wally-pipelined.do ../config/rv64ic -# or, to run from a shell, type the following at the shell prompt: -# vsim -c -do wally-pipelined.do ../config/rv64ic -# (omit the "-c" to see the GUI while running from the shell) - -onbreak {resume} - -# create library -if [file exists work$2] { - vdel -lib work$2 -all -} -vlib work$2 - -# compile source files -# suppress spurious warnngs about -# "Extra checking for conflicts with always_comb done at vopt time" -# because vsim will run vopt -vlog +incdir+$1 ../testbench/testbench-imperas.sv ../testbench/function_radix.sv ../src/*/*.sv -suppress 2583 - -# start and run simulation -# remove +acc flag for faster sim during regressions if there is no need to access internal signals -vopt work.testbench -o workopt -vsim workopt - -run -all -quit diff --git a/wally-pipelined/regression/wally-pipelined-batch.do b/wally-pipelined/regression/wally-pipelined-batch.do index 040c03c58..ad4c7507c 100644 --- a/wally-pipelined/regression/wally-pipelined-batch.do +++ b/wally-pipelined/regression/wally-pipelined-batch.do @@ -17,10 +17,10 @@ onbreak {resume} # create library -if [file exists work] { - vdel -all +if [file exists work_$2] { + vdel -lib work_$2 -all } -vlib work +vlib work_$2 # compile source files # suppress spurious warnngs about @@ -28,15 +28,16 @@ vlib work # because vsim will run vopt # default to config/rv64ic, but allow this to be overridden at the command line. For example: -# do wally-pipelined-batch.do ../config/rv32ic +# do wally-pipelined-batch.do ../config/rv32ic rv32ic switch $argc { 0 {vlog +incdir+../config/rv64ic ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583} 1 {vlog +incdir+$1 ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583} + 2 {vlog -work work_$2 +incdir+$1 ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583} } # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals -vopt work.testbench -o workopt -vsim workopt +vopt work_$2.testbench -work work_$2 -o workopt_$2 +vsim -lib work_$2 workopt_$2 run -all quit From ed68d8240bc0f456ea470614490f519107e120a6 Mon Sep 17 00:00:00 2001 From: Jarred Allen Date: Tue, 16 Mar 2021 18:16:00 -0400 Subject: [PATCH 11/26] Undo accidental change --- wally-pipelined/regression/regression-wally.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/regression/regression-wally.py b/wally-pipelined/regression/regression-wally.py index 167ee57ba..68957cae4 100755 --- a/wally-pipelined/regression/regression-wally.py +++ b/wally-pipelined/regression/regression-wally.py @@ -27,7 +27,7 @@ def test_config(config, print_res=True): cmd = "echo 'quit' | vsim -do wally-busybear.do -c >" + logname os.system(cmd) # check for success. grep returns 0 if found, 1 if not found - passed = True# search_log_for_text("# loaded 100000 instructions", logname) + passed = search_log_for_text("# loaded 100000 instructions", logname) else: cmd = "vsim -c >" + logname +" < Date: Tue, 16 Mar 2021 19:22:36 -0400 Subject: [PATCH 13/26] Add privileged tests for mcause --- .../testgen/privileged/testgen-CAUSE.py | 200 ++++++++++++++---- 1 file changed, 158 insertions(+), 42 deletions(-) diff --git a/wally-pipelined/testgen/privileged/testgen-CAUSE.py b/wally-pipelined/testgen/privileged/testgen-CAUSE.py index c4b331ac6..7cc9fa544 100644 --- a/wally-pipelined/testgen/privileged/testgen-CAUSE.py +++ b/wally-pipelined/testgen/privileged/testgen-CAUSE.py @@ -30,33 +30,149 @@ from random import getrandbits # # exit(1) def randRegs(): - reg1 = randint(1,31) - reg2 = randint(1,31) - reg3 = randint(1,31) + reg1 = randint(1,30) + reg2 = randint(1,30) + reg3 = randint(1,30) if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2): return randRegs() else: return reg1, reg2, reg3 def writeVectors(storecmd): + global testnum reg1, reg2, reg3 = randRegs() + # t5 gets written with mtvec? + + # lines = f""" + + # li x{reg1}, 0 + # csrwi mtvec, 80002000 + # .data 00000000 + # j _done{testnum} + + # _trap{testnum}: + # csrrs x{reg1}, mcause, x0 + # ecall + + # _done{testnum}: + # add x0, x0, x0 + # """ + + #lines = + lines = f""" - li x{reg1}, 0 + j _setup + csrrs x31, mcause, x0 + ecall + + _setup: + li x2, 0x80000004 + csrrw x0, mtvec, x2 + """ + f.write(lines) - write(lines, storecmd, reg1, 0) + # User Software Interrupt + write(f""" + li x3, 0x8000000 + {storecmd} x2, 0(x3) + """, storecmd, True, 0, "u") -def write(lines, storecmd, reg, expected): + # Supervisor Software Interrupt + write(f""" + li x3, 0x8000000 + {storecmd} x2, 0(x3) + """, storecmd, True, 0, "s") + + # Machine Software Interrupt + write(f""" + li x3, 0x8000000 + {storecmd} x2, 0(x3) + """, storecmd, True, 3) + + # User Timer Interrupt + #write(f""" + # lw x2, mtimecmp + # {storecmd} x2, mtimecmp + #""", storecmd, True, 4, "u") + + # # Supervisor Timer Interrupt + #write(f""" + # lw x2, mtimecmp + # {storecmd} x2, mtimecmp + #""", storecmd, True, 5, "s") + + # Machine Timer Interrupt + #write(f""" + # lw x2, mtimecmp + # {storecmd} x2, mtimecmp + #""", storecmd, True, 6) + + # User external interrupt True, 8 + # Supervisor external interrupt True, 9 + + # Instr Addr Misalign + write(f""" + li x2, 0x00000000 + lw x3, 11(x2) + """, storecmd, False, 0) + + # Instr Access Fault False, 1 + # Not possible in machine mode, because we can access all memory + + # Illegal Instruction + write(f""" + .data 00000000 + """, storecmd, False, 2) + + # Breakpoint + write(f""" + ebreak + """, storecmd, False, 3) + + # Load Addr Misalign + write(f""" + li x2, 0x00000000 + lw x3, 11(x2) + """, storecmd, False, 4) + + # Load Access Fault False, 5 + # Not possible in machine mode, because we can access all memory + + + # Store/AMO address misaligned + write(f""" + li x2, 0x00000000 + {storecmd} x3, 11(x2) + """, storecmd, False, 6) + + # Store/AMO access fault False, 7 + # Not possible in machine mode, because we can access all memory + + # Environment call from U-mode + # Environment call from S-mode + +def write(lines, storecmd, interrupt, code, mode = "m"): global testnum + # generate expected interrupt code + expected = (0 if not interrupt else (2**31 if xlen == 32 else 2**63)) + code + lines = f""" # Testcase {testnum} + li x31, 0 {lines} - {storecmd} x{reg}, {str(wordsize*testnum)}(x6) - #RVTEST_IO_ASSERT_GPR_EQ(x0, 0, {formatstr.format(expected)}) + {storecmd} x31, {str(wordsize*testnum)}(x6) + # RVTEST_IO_ASSERT_GPR_EQ(x0, 0, {formatstr.format(expected)}) """ + + #if mode == "s": + # go to supervisor mode + #elif mode == "u": + # go to user mode + f.write(lines) if (xlen == 32): @@ -71,31 +187,31 @@ def write(lines, storecmd, reg, expected): ################################## # name: (interrupt?, code) -tests = { - 'User software interrupt': (1, '0'), - 'Supervisor software interrupt': (1, '1'), - 'Machine software interrupt': (1, '3'), - 'User timer interrupt': (1, '4'), - 'Supervisor timer interrupt': (1, '5'), - 'Machine timer interrupt': (1, '7'), - 'User external interrupt': (1, '8'), - 'Supervisor external interrupt': (1, '9'), - 'Machine external interrupt': (1, '11'), - 'Instruction address misaligned': (0, '0'), - 'Instruction access fault': (0, '1'), - 'Illegal instruction': (0, '2'), - 'Breakpoint': (0, '3'), - 'Load address misaligned': (0, '4'), - 'Load access fault': (0, '5'), - 'Store/AMO address misaligned': (0, '6'), - 'Store/AMO access fault': (0, '7'), - 'Environment call from U-mode': (0, '8'), - 'Environment call from S-mode': (0, '9'), - 'Environment call from M-mode': (0, '11'), - 'Instruction page fault': (0, '12'), - 'Load page fault': (0, '13'), - 'Store/AMO page fault': (0, '15'), -} +# tests = { +# 'User software interrupt': (1, '0'), +# 'Supervisor software interrupt': (1, '1'), +# 'Machine software interrupt': (1, '3'), +# 'User timer interrupt': (1, '4'), +# 'Supervisor timer interrupt': (1, '5'), +# 'Machine timer interrupt': (1, '7'), +# 'User external interrupt': (1, '8'), +# 'Supervisor external interrupt': (1, '9'), +# 'Machine external interrupt': (1, '11'), +# 'Instruction address misaligned': (0, '0'), +# 'Instruction access fault': (0, '1'), +# 'Illegal instruction': (0, '2'), +# 'Breakpoint': (0, '3'), +# 'Load address misaligned': (0, '4'), +# 'Load access fault': (0, '5'), +# 'Store/AMO address misaligned': (0, '6'), +# 'Store/AMO access fault': (0, '7'), +# 'Environment call from U-mode': (0, '8'), +# 'Environment call from S-mode': (0, '9'), +# 'Environment call from M-mode': (0, '11'), +# 'Instruction page fault': (0, '12'), +# 'Load page fault': (0, '13'), +# 'Store/AMO page fault': (0, '15'), +# } author = "dottolia@hmc.edu" xlens = [32, 64] numrand = 60; @@ -132,23 +248,23 @@ for xlen in xlens: f.write(line) # insert generic header - h = open("../testgen_header.S", "r") - for line in h: - f.write(line) + # h = open("../testgen_header.S", "r") + # for line in h: + # f.write(line) # print directed and random test vectors writeVectors(storecmd) # print footer - h = open("../testgen_footer.S", "r") - for line in h: - f.write(line) + # h = open("../testgen_footer.S", "r") + # for line in h: + # f.write(line) # Finish - lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n" - lines = lines + "\nRV_COMPLIANCE_DATA_END\n" - f.write(lines) + # lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n" + # lines = lines + "\nRV_COMPLIANCE_DATA_END\n" + # f.write(lines) f.close() r.close() From c9d70a17784a024c4ad749f99a9b20988b50ad3a Mon Sep 17 00:00:00 2001 From: Domenico Ottolia Date: Tue, 16 Mar 2021 20:28:38 -0400 Subject: [PATCH 14/26] Add privileged testbench --- .../testbench/testbench-privileged.sv | 305 ++++++++++++++++++ 1 file changed, 305 insertions(+) create mode 100644 wally-pipelined/testbench/testbench-privileged.sv diff --git a/wally-pipelined/testbench/testbench-privileged.sv b/wally-pipelined/testbench/testbench-privileged.sv new file mode 100644 index 000000000..410dd62e1 --- /dev/null +++ b/wally-pipelined/testbench/testbench-privileged.sv @@ -0,0 +1,305 @@ +/////////////////////////////////////////// +// testbench-privileged.sv +// +// Written: Ben Bracker (bbracker@hmc.edu) 11 Feb. 2021, Tiny Modifications: Domenico Ottolia (dottolia@hmc.edu) 16 Mar. 2021 +// Based on: testbench-imperas.sv by David Harris +// +// Purpose: Wally Testbench and helper modules +// Applies test programs meant to test peripherals +// These tests assume the processor itself is already working! +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +`include "wally-config.vh" + +module testbench(); + logic clk; + logic reset; + + int test, i, errors, totalerrors; + logic [31:0] sig32[0:10000]; + logic [`XLEN-1:0] signature[0:10000]; + logic [`XLEN-1:0] testadr; + string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; + logic [31:0] InstrW; + logic [`XLEN-1:0] meminit; + + string tests[] = '{ + "privileged/WALLY-CAUSE-64", "0" + }; + + logic [`AHBW-1:0] HRDATAEXT; + logic HREADYEXT, HRESPEXT; + logic [31:0] HADDR; + logic [`AHBW-1:0] HWDATA; + logic HWRITE; + logic [2:0] HSIZE; + logic [2:0] HBURST; + logic [3:0] HPROT; + logic [1:0] HTRANS; + logic HMASTLOCK; + logic HCLK, HRESETn; + + + // pick tests based on modes supported + // *** actually I no longer support this + // would need to put this back in if you wanted to test anything other than rv64i + + string signame, memfilename; + + logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn; + logic UARTSin, UARTSout; + + // instantiate device to be tested + assign GPIOPinsIn = 0; + assign UARTSin = 1; + assign HREADYEXT = 1; + assign HRESPEXT = 0; + assign HRDATAEXT = 0; + + wallypipelinedsoc dut(.*); + + // Track names of instructions + instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE, + dut.hart.ifu.InstrD, dut.hart.ifu.InstrE, + dut.hart.ifu.InstrM, InstrW, + InstrDName, InstrEName, InstrMName, InstrWName); + + // initialize tests + initial + begin + test = 0; + totalerrors = 0; + testadr = 0; + // fill memory with defined values to reduce Xs in simulation + if (`XLEN == 32) meminit = 32'hFEDC0123; + else meminit = 64'hFEDCBA9876543210; + for (i=0; i<=65535; i = i+1) begin + //dut.imem.RAM[i] = meminit; + // dut.uncore.RAM[i] = meminit; + end + // read test vectors into memory + memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"}; + $readmemh(memfilename, dut.imem.RAM); + $readmemh(memfilename, dut.uncore.dtim.RAM); + reset = 1; # 22; reset = 0; + end + + // generate clock to sequence tests + always + begin + clk = 1; # 5; clk = 0; # 5; + end + + // check results + always @(negedge clk) + begin + if (dut.hart.priv.EcallFaultM && + (dut.hart.ieu.dp.regf.rf[3] == 1 || (dut.hart.ieu.dp.regf.we3 && dut.hart.ieu.dp.regf.a3 == 3 && dut.hart.ieu.dp.regf.wd3 == 1))) begin + $display("Code ended with ecall with gp = 1"); + #60; // give time for instructions in pipeline to finish + // clear signature to prevent contamination from previous tests + for(i=0; i<10000; i=i+1) begin + sig32[i] = 'bx; + end + + // read signature, reformat in 64 bits if necessary + signame = {"../../imperas-riscv-tests/work/", tests[test], ".signature.output"}; + $readmemh(signame, sig32); + i = 0; + while (i < 10000) begin + if (`XLEN == 32) begin + signature[i] = sig32[i]; + i = i+1; + end else begin + signature[i/2] = {sig32[i+1], sig32[i]}; + i = i + 2; + end + end + + // Check errors + i = 0; + errors = 0; + if (`XLEN == 32) + testadr = (`TIMBASE+tests[test+1].atohex())/4; + else + testadr = (`TIMBASE+tests[test+1].atohex())/8; + /* verilator lint_off INFINITELOOP */ + while (signature[i] !== 'bx) begin + //$display("signature[%h] = %h", i, signature[i]); + if (signature[i] !== dut.uncore.dtim.RAM[testadr+i]) begin + if (signature[i+4] !== 'bx || signature[i] !== 32'hFFFFFFFF) begin + // report errors unless they are garbage at the end of the sim + // kind of hacky test for garbage right now + errors = errors+1; + $display(" Error on test %s result %d: adr = %h sim = %h, signature = %h", + tests[test], i, (testadr+i)*`XLEN/8, dut.uncore.dtim.RAM[testadr+i], signature[i]); + end + end + i = i + 1; + end + /* verilator lint_on INFINITELOOP */ + if (errors == 0) $display("%s succeeded. Brilliant!!!", tests[test]); + else begin + $display("%s failed with %d errors. :(", tests[test], errors); + totalerrors = totalerrors+1; + end + test = test + 2; + if (test == tests.size()) begin + if (totalerrors == 0) $display("SUCCESS! All tests ran without failures."); + else $display("FAIL: %d test programs had errors", totalerrors); + $stop; + end + else begin + memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"}; + $readmemh(memfilename, dut.imem.RAM); + $readmemh(memfilename, dut.uncore.dtim.RAM); + $display("Read memfile %s", memfilename); + reset = 1; # 17; reset = 0; + end + end + end +endmodule + +/* verilator lint_on STMTDLY */ +/* verilator lint_on WIDTH */ + +module instrTrackerTB( + input logic clk, reset, FlushE, + input logic [31:0] InstrD, + input logic [31:0] InstrE, InstrM, + output logic [31:0] InstrW, + output string InstrDName, InstrEName, InstrMName, InstrWName); + + // stage Instr to Writeback for visualization + flopr #(32) InstrWReg(clk, reset, InstrM, InstrW); + + instrNameDecTB ddec(InstrD, InstrDName); + instrNameDecTB edec(InstrE, InstrEName); + instrNameDecTB mdec(InstrM, InstrMName); + instrNameDecTB wdec(InstrW, InstrWName); +endmodule + +// decode the instruction name, to help the test bench +module instrNameDecTB( + input logic [31:0] instr, + output string name); + + logic [6:0] op; + logic [2:0] funct3; + logic [6:0] funct7; + logic [11:0] imm; + + assign op = instr[6:0]; + assign funct3 = instr[14:12]; + assign funct7 = instr[31:25]; + assign imm = instr[31:20]; + + // it would be nice to add the operands to the name + // create another variable called decoded + + always_comb + casez({op, funct3}) + 10'b0000000_000: name = "BAD"; + 10'b0000011_000: name = "LB"; + 10'b0000011_001: name = "LH"; + 10'b0000011_010: name = "LW"; + 10'b0000011_011: name = "LD"; + 10'b0000011_100: name = "LBU"; + 10'b0000011_101: name = "LHU"; + 10'b0000011_110: name = "LWU"; + 10'b0010011_000: if (instr[31:15] == 0 && instr[11:7] ==0) name = "NOP/FLUSH"; + else name = "ADDI"; + 10'b0010011_001: if (funct7[6:1] == 6'b000000) name = "SLLI"; + else name = "ILLEGAL"; + 10'b0010011_010: name = "SLTI"; + 10'b0010011_011: name = "SLTIU"; + 10'b0010011_100: name = "XORI"; + 10'b0010011_101: if (funct7[6:1] == 6'b000000) name = "SRLI"; + else if (funct7[6:1] == 6'b010000) name = "SRAI"; + else name = "ILLEGAL"; + 10'b0010011_110: name = "ORI"; + 10'b0010011_111: name = "ANDI"; + 10'b0010111_???: name = "AUIPC"; + 10'b0100011_000: name = "SB"; + 10'b0100011_001: name = "SH"; + 10'b0100011_010: name = "SW"; + 10'b0100011_011: name = "SD"; + 10'b0011011_000: name = "ADDIW"; + 10'b0011011_001: name = "SLLIW"; + 10'b0011011_101: if (funct7 == 7'b0000000) name = "SRLIW"; + else if (funct7 == 7'b0100000) name = "SRAIW"; + else name = "ILLEGAL"; + 10'b0111011_000: if (funct7 == 7'b0000000) name = "ADDW"; + else if (funct7 == 7'b0100000) name = "SUBW"; + else name = "ILLEGAL"; + 10'b0111011_001: name = "SLLW"; + 10'b0111011_101: if (funct7 == 7'b0000000) name = "SRLW"; + else if (funct7 == 7'b0100000) name = "SRAW"; + else name = "ILLEGAL"; + 10'b0110011_000: if (funct7 == 7'b0000000) name = "ADD"; + else if (funct7 == 7'b0000001) name = "MUL"; + else if (funct7 == 7'b0100000) name = "SUB"; + else name = "ILLEGAL"; + 10'b0110011_001: if (funct7 == 7'b0000000) name = "SLL"; + else if (funct7 == 7'b0000001) name = "MULH"; + else name = "ILLEGAL"; + 10'b0110011_010: if (funct7 == 7'b0000000) name = "SLT"; + else if (funct7 == 7'b0000001) name = "MULHSU"; + else name = "ILLEGAL"; + 10'b0110011_011: if (funct7 == 7'b0000000) name = "SLTU"; + else if (funct7 == 7'b0000001) name = "DIV"; + else name = "ILLEGAL"; + 10'b0110011_100: if (funct7 == 7'b0000000) name = "XOR"; + else if (funct7 == 7'b0000001) name = "MUL"; + else name = "ILLEGAL"; + 10'b0110011_101: if (funct7 == 7'b0000000) name = "SRL"; + else if (funct7 == 7'b0000001) name = "DIVU"; + else if (funct7 == 7'b0100000) name = "SRA"; + else name = "ILLEGAL"; + 10'b0110011_110: if (funct7 == 7'b0000000) name = "OR"; + else if (funct7 == 7'b0000001) name = "REM"; + else name = "ILLEGAL"; + 10'b0110011_111: if (funct7 == 7'b0000000) name = "AND"; + else if (funct7 == 7'b0000001) name = "REMU"; + else name = "ILLEGAL"; + 10'b0110111_???: name = "LUI"; + 10'b1100011_000: name = "BEQ"; + 10'b1100011_001: name = "BNE"; + 10'b1100011_100: name = "BLT"; + 10'b1100011_101: name = "BGE"; + 10'b1100011_110: name = "BLTU"; + 10'b1100011_111: name = "BGEU"; + 10'b1100111_000: name = "JALR"; + 10'b1101111_???: name = "JAL"; + 10'b1110011_000: if (imm == 0) name = "ECALL"; + else if (imm == 1) name = "EBREAK"; + else if (imm == 2) name = "URET"; + else if (imm == 258) name = "SRET"; + else if (imm == 770) name = "MRET"; + else name = "ILLEGAL"; + 10'b1110011_001: name = "CSRRW"; + 10'b1110011_010: name = "CSRRS"; + 10'b1110011_011: name = "CSRRC"; + 10'b1110011_101: name = "CSRRWI"; + 10'b1110011_110: name = "CSRRSI"; + 10'b1110011_111: name = "CSRRCI"; + 10'b0001111_???: name = "FENCE"; + default: name = "ILLEGAL"; + endcase +endmodule From 162955de692d206cf9f50c9c5d86881fb4897277 Mon Sep 17 00:00:00 2001 From: Noah Boorstin Date: Tue, 16 Mar 2021 21:08:47 -0400 Subject: [PATCH 15/26] busybear: add COUNTERS define --- wally-pipelined/config/busybear/wally-config.vh | 1 + 1 file changed, 1 insertion(+) diff --git a/wally-pipelined/config/busybear/wally-config.vh b/wally-pipelined/config/busybear/wally-config.vh index dc4d64515..5a07bf55c 100644 --- a/wally-pipelined/config/busybear/wally-config.vh +++ b/wally-pipelined/config/busybear/wally-config.vh @@ -38,6 +38,7 @@ `define U_SUPPORTED ((`MISA >> 20) % 2 == 1) `define ZCSR_SUPPORTED 1 `define ZCOUNTERS_SUPPORTED 1 +`define COUNTERS 31 // N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21 //`define N_SUPPORTED ((MISA >> 13) % 2 == 1) `define N_SUPPORTED 0 From 45ed2742cf1fc7479ad09c4655877db9cd865423 Mon Sep 17 00:00:00 2001 From: Noah Boorstin Date: Tue, 16 Mar 2021 21:42:26 -0400 Subject: [PATCH 16/26] busybear: add seperate message on bad memory access becasue its confusing --- wally-pipelined/testbench/testbench-busybear.sv | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/wally-pipelined/testbench/testbench-busybear.sv b/wally-pipelined/testbench/testbench-busybear.sv index abd830b80..e9d0621c1 100644 --- a/wally-pipelined/testbench/testbench-busybear.sv +++ b/wally-pipelined/testbench/testbench-busybear.sv @@ -106,6 +106,7 @@ module testbench_busybear(); end integer warningCount = 0; + integer instrs; //logic[63:0] adrTranslation[4:0]; //string translationType[4:0] = {"rf", "writeAdr", "PCW", "PC", "readAdr"}; @@ -249,6 +250,15 @@ module testbench_busybear(); end end + always @(dut.hart.priv.csr.genblk1.csrm.MCAUSE_REGW) begin + if (dut.hart.priv.csr.genblk1.csrm.MCAUSE_REGW == 5 && instrs != 0) begin + $display("!!!!!!illegal (physical) memory access !!!!!!!!!!"); + $display("(as a reminder, MCAUSE and MEPC are set by this)"); + $display("at %0t ps, instr %0d, HADDR %x", $time, instrs, HADDR); + `ERROR + end + end + `define CHECK_CSR2(CSR, PATH) \ string CSR; \ logic [63:0] expected``CSR``; \ @@ -340,7 +350,6 @@ module testbench_busybear(); end string PCtext, PCtext2; - integer instrs; initial begin instrs = 0; end From 0b880110c9459e6a81e817dd47ea37b10e016dec Mon Sep 17 00:00:00 2001 From: Domenico Ottolia Date: Tue, 16 Mar 2021 23:26:59 -0400 Subject: [PATCH 17/26] Add test runner for privileged --- wally-pipelined/testgen/privileged/run.sh | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 wally-pipelined/testgen/privileged/run.sh diff --git a/wally-pipelined/testgen/privileged/run.sh b/wally-pipelined/testgen/privileged/run.sh new file mode 100644 index 000000000..13c7c2b0f --- /dev/null +++ b/wally-pipelined/testgen/privileged/run.sh @@ -0,0 +1,22 @@ +clear +printf "\n\n#####\nStarting tests for $1\n#####\n\n" + +if [[ "$2" != "-simonly" ]] +then + cd ~/riscv-wally/wally-pipelined/testgen/privileged + python3 "testgen-$1.py" + printf "\n\n#####\nRan testgen-$1.py Making...\n#####\n\n\n" + + cd ~/riscv-wally/imperas-riscv-tests + make privileged +fi + +if [[ "$2" == "-sim" || "$2" == "-simonly" ]] +then + printf "\n\n\n#####\nSimulating!\n#####\n\n" + cd ~/riscv-wally/wally-pipelined/regression + vsim -do wally-privileged.do -c +fi + +cd ~/riscv-wally +printf "\n\n\n#####\nDone!\n#####\n\n" \ No newline at end of file From 31ad619a216a6fdc2bc79e95071f737c8d080881 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 17 Mar 2021 11:06:32 -0500 Subject: [PATCH 18/26] Added possibly working OSU test bench as a precursor to running a bp benchmark. Fixed a few bugs with the function radix. --- wally-pipelined/bin/exe2memfile.pl | 3 +- wally-pipelined/bin/extractFunctionRadix.sh | 2 +- wally-pipelined/regression/wave.do | 52 ++++++++++++------- wally-pipelined/testbench/function_radix.sv | 2 + .../testbench/testbench-imperas.sv | 20 +++++-- 5 files changed, 53 insertions(+), 26 deletions(-) diff --git a/wally-pipelined/bin/exe2memfile.pl b/wally-pipelined/bin/exe2memfile.pl index 1a9dbbb57..79b975c7a 100755 --- a/wally-pipelined/bin/exe2memfile.pl +++ b/wally-pipelined/bin/exe2memfile.pl @@ -17,10 +17,11 @@ my @memfilebytes = (0)*16384*4; my $maxaddress = 0; STDOUT->autoflush(1); +# *** Ross Thompson I think there is a bug here needs to be +1 print ("Processing $#ARGV memfiles: "); my $frac = $#ARGV/10; for(my $i=0; $i<=$#ARGV; $i++) { - if ($i % $frac == 0) { print ("$i ") }; + if ($i < 10 || $i % $frac == 0) { print ("$i ") }; my $fname = $ARGV[$i]; # print "fname = $fname"; my $ofile = $fname.".objdump"; diff --git a/wally-pipelined/bin/extractFunctionRadix.sh b/wally-pipelined/bin/extractFunctionRadix.sh index f5de782d7..cb37f5378 100755 --- a/wally-pipelined/bin/extractFunctionRadix.sh +++ b/wally-pipelined/bin/extractFunctionRadix.sh @@ -39,7 +39,7 @@ function processProgram { # when size = 16 => 64 bit # when size = 8 => 32 bit - local listOfAddr=`egrep -i "^[0-9]{$size} <[0-9a-zA-Z_]+>" $objDumpFile` + local listOfAddr=`egrep -i "^[0-9a-f]{$size} <[0-9a-zA-Z_]+>" $objDumpFile` # skip if the wrong bit width. if [ -z "$listOfAddr" ]; then diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index c37d657bb..89d0fdeef 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -8,13 +8,26 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/functionRadix/fun add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/RetM -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/TrapM -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/InstrStall -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/DataStall +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM +add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/InstrStall +add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DataStall add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE @@ -88,10 +101,10 @@ add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu add wave -noupdate /testbench/InstrFName -add wave -noupdate -group dcache /testbench/dut/hart/MemAdrM -add wave -noupdate -group dcache /testbench/dut/hart/MemPAdrM -add wave -noupdate -group dcache /testbench/dut/hart/WriteDataM -add wave -noupdate -group dcache /testbench/dut/hart/dmem/MemRWM +add wave -noupdate -expand -group dcache /testbench/dut/hart/MemAdrM +add wave -noupdate -expand -group dcache /testbench/dut/hart/MemPAdrM +add wave -noupdate -expand -group dcache /testbench/dut/hart/WriteDataM +add wave -noupdate -expand -group dcache /testbench/dut/hart/dmem/MemRWM add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E @@ -110,7 +123,13 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALURe add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE add wave -noupdate /testbench/dut/hart/ieu/dp/ALUResultM +add wave -noupdate -expand -group PCS /testbench/dut/hart/PCF +add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCD +add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE +add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM +add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCW add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/FunctionAddr +add wave -noupdate -group {function radix debug} -radix unsigned /testbench/functionRadix/function_radix/ProgramAddrIndex add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/reset add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/ProgramLabelMapLineCount add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/ProgramLabelMapLine @@ -124,14 +143,9 @@ add wave -noupdate -group {function radix debug} /testbench/functionRadix/functi add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/FunctionAddr add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/ProgramAddrIndex add wave -noupdate -group {function radix debug} /testbench/functionRadix/function_radix/FunctionName -add wave -noupdate -expand -group PCS /testbench/dut/hart/PCF -add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCD -add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE -add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM -add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCW TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {3758805 ns} 0} {{Cursor 3} {4351471 ns} 0} -quietly wave cursor active 2 +WaveRestoreCursors {{Cursor 2} {181681 ns} 0} {{Cursor 3} {20231927 ns} 0} +quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 229 configure wave -justifyvalue left @@ -146,4 +160,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {4351320 ns} {4351862 ns} +WaveRestoreZoom {11339470 ns} {14752202 ns} diff --git a/wally-pipelined/testbench/function_radix.sv b/wally-pipelined/testbench/function_radix.sv index b5c34c2b5..e6bd479f4 100644 --- a/wally-pipelined/testbench/function_radix.sv +++ b/wally-pipelined/testbench/function_radix.sv @@ -85,9 +85,11 @@ module function_radix(reset, ProgramAddrMapFile, ProgramLabelMapFile); // if it is greather we want 1 less than left. if (array[left] < pc) begin minval = array[left]; + mid = left; return; end else begin minval = array[left-1]; + mid = left - 1; return; end end diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index 3c9c4cc91..7b7d7f95b 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -28,6 +28,7 @@ module testbench(); parameter DEBUG = 0; + parameter TESTSBP = 0; logic clk; logic reset; @@ -314,6 +315,10 @@ string tests32i[] = { "rv32i/WALLY-CSRRCI", "3000" }; + + string testsBP64[] = '{ + "rv64BP/reg-test", "10000" + }; string tests[]; string ProgramAddrMapFile, ProgramLabelMapFile; logic [`AHBW-1:0] HRDATAEXT; @@ -332,13 +337,18 @@ string tests32i[] = { // pick tests based on modes supported initial if (`XLEN == 64) begin // RV64 - tests = {tests64i}; - if (`C_SUPPORTED) tests = {tests, tests64ic}; - else tests = {tests, tests64iNOc}; - if (`M_SUPPORTED) tests = {tests, tests64m}; - if (`A_SUPPORTED) tests = {tests, tests64a}; + if(TESTSBP) begin + tests = testsBP64; + end else begin + tests = {tests64i}; + if (`C_SUPPORTED) tests = {tests, tests64ic}; + else tests = {tests, tests64iNOc}; + if (`M_SUPPORTED) tests = {tests, tests64m}; + if (`A_SUPPORTED) tests = {tests, tests64a}; + end // tests = {tests64a, tests}; end else begin // RV32 + // *** add the 32 bit bp tests tests = {tests32i}; if (`C_SUPPORTED % 2 == 1) tests = {tests, tests32ic}; else tests = {tests, tests32iNOc}; From 7bc95ba0736f3de59e4bdd6b1dbe87c9f80055c9 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 17 Mar 2021 11:17:52 -0500 Subject: [PATCH 19/26] Fixed issue with sim-wally-batch. Are people still using this script? --- wally-pipelined/regression/sim-wally-batch | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/regression/sim-wally-batch b/wally-pipelined/regression/sim-wally-batch index 5305cfc60..dc42d7b17 100755 --- a/wally-pipelined/regression/sim-wally-batch +++ b/wally-pipelined/regression/sim-wally-batch @@ -1,3 +1,3 @@ vsim -c < Date: Wed, 17 Mar 2021 14:36:34 -0400 Subject: [PATCH 20/26] replicating coremark changes into coremark bare --- .../config/coremark_bare/BTBPredictor.txt | 1024 +++++++++++++++++ .../config/coremark_bare/twoBitPredictor.txt | 1024 +++++++++++++++++ .../config/coremark_bare/wally-config.vh | 4 + .../config/coremark_bare/wally-constants.vh | 31 + 4 files changed, 2083 insertions(+) create mode 100644 wally-pipelined/config/coremark_bare/BTBPredictor.txt create mode 100644 wally-pipelined/config/coremark_bare/twoBitPredictor.txt create mode 100644 wally-pipelined/config/coremark_bare/wally-constants.vh diff --git a/wally-pipelined/config/coremark_bare/BTBPredictor.txt b/wally-pipelined/config/coremark_bare/BTBPredictor.txt new file mode 100644 index 000000000..b761147c6 --- /dev/null +++ b/wally-pipelined/config/coremark_bare/BTBPredictor.txt @@ -0,0 +1,1024 @@ +00000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000 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53f3a5f5a..24c0a13a8 100644 --- a/wally-pipelined/config/coremark_bare/wally-config.vh +++ b/wally-pipelined/config/coremark_bare/wally-config.vh @@ -37,6 +37,7 @@ `define S_SUPPORTED ((`MISA >> 18) % 2 == 1) `define U_SUPPORTED ((`MISA >> 20) % 2 == 1) `define ZCSR_SUPPORTED 1 +`define COUNTERS 31 `define ZCOUNTERS_SUPPORTED 1 // N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21 //`define N_SUPPORTED ((MISA >> 13) % 2 == 1) @@ -87,3 +88,6 @@ /* verilator lint_off WIDTH */ /* verilator lint_off ASSIGNDLY */ /* verilator lint_off PINCONNECTEMPTY */ + +`define TWO_BIT_PRELOAD "../config/coremark_bare/twoBitPRedictor.txt" +`define BTB_PRELOAD "../config/coremark_bare/BTBPredictor.txt" diff --git a/wally-pipelined/config/coremark_bare/wally-constants.vh b/wally-pipelined/config/coremark_bare/wally-constants.vh new file mode 100644 index 000000000..55fb4e947 --- /dev/null +++ b/wally-pipelined/config/coremark_bare/wally-constants.vh @@ -0,0 +1,31 @@ +////////////////////////////////////////// +// wally-constants.vh +// +// Written: tfleming@hmc.edu 4 March 2021 +// Modified: +// +// Purpose: Specify certain constants defined in the RISC-V 64-bit architecture. +// These macros should not be changed, except in the event of an +// update to the architecture or particularly special circumstances. +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +// Virtual Memory Constants (sv39) +`define VPN_BITS 27 +`define PPN_BITS 44 +`define PA_BITS 56 From bccd37d778f59a5a78b01f54b7f6dffefe86b82c Mon Sep 17 00:00:00 2001 From: Elizabeth Hedenberg Date: Wed, 17 Mar 2021 15:15:55 -0400 Subject: [PATCH 21/26] fixing coremark branch prediction --- wally-pipelined/regression/wally-coremark_bare.do | 5 +++-- wally-pipelined/testbench/testbench-coremark_bare.sv | 6 ++++++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/wally-pipelined/regression/wally-coremark_bare.do b/wally-pipelined/regression/wally-coremark_bare.do index fdb40a051..421ef6d5f 100644 --- a/wally-pipelined/regression/wally-coremark_bare.do +++ b/wally-pipelined/regression/wally-coremark_bare.do @@ -93,7 +93,7 @@ add wave -divider RAM add wave -hex -r /testbench/dut/uncore/dtim/RAM add wave -divider Misc add wave -divider -#add wave -hex -r /testbench/* +add wave -hex -r /testbench/* -- Set Wave Output Items TreeUpdate [SetDefaultTree] @@ -111,5 +111,6 @@ set DefaultRadix hexadecimal -- Run the Simulation #run 7402000 #run 12750 -run -all +#run -all +run 3000 #quit diff --git a/wally-pipelined/testbench/testbench-coremark_bare.sv b/wally-pipelined/testbench/testbench-coremark_bare.sv index 529a6b98c..b21772e2a 100644 --- a/wally-pipelined/testbench/testbench-coremark_bare.sv +++ b/wally-pipelined/testbench/testbench-coremark_bare.sv @@ -91,6 +91,12 @@ module testbench(); $stop; end end + + initial begin + $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.DirPredictor.memory.memory); + $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.TargetPredictor.memory.memory); + end + endmodule /* verilator lint_on STMTDLY */ From ca901513c82ec6bde1a54280585b7ce42cc9fd06 Mon Sep 17 00:00:00 2001 From: Teo Ene Date: Wed, 17 Mar 2021 14:50:54 -0500 Subject: [PATCH 22/26] Added Ross's addr lab stuff to coremark stuff --- wally-pipelined/testbench/testbench-coremark_bare.sv | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/wally-pipelined/testbench/testbench-coremark_bare.sv b/wally-pipelined/testbench/testbench-coremark_bare.sv index b21772e2a..ea7e26d5d 100644 --- a/wally-pipelined/testbench/testbench-coremark_bare.sv +++ b/wally-pipelined/testbench/testbench-coremark_bare.sv @@ -76,6 +76,8 @@ module testbench(); $readmemh(memfilename, dut.uncore.dtim.RAM); for(j=2371; j < 65535; j = j+1) dut.uncore.dtim.RAM[j] = 64'b0; + ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.objdump.addr"; + ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.objdump.lab"; reset = 1; # 22; reset = 0; end // generate clock to sequence tests @@ -92,11 +94,16 @@ module testbench(); end end + if (1 == 1) begin : functionRadix + function_radix function_radix(.reset(reset), + .ProgramAddrMapFile(ProgramAddrMapFile), + .ProgramLabelMapFile(ProgramLabelMapFile)); + end + initial begin $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.DirPredictor.memory.memory); $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.TargetPredictor.memory.memory); end - endmodule /* verilator lint_on STMTDLY */ From 083a24c06bc10dc6be1705941b03df41c6848178 Mon Sep 17 00:00:00 2001 From: Teo Ene Date: Wed, 17 Mar 2021 14:52:31 -0500 Subject: [PATCH 23/26] addition to last commit --- wally-pipelined/config/coremark_bare/wally-config.vh | 2 +- wally-pipelined/regression/wally-coremark_bare.do | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/wally-pipelined/config/coremark_bare/wally-config.vh b/wally-pipelined/config/coremark_bare/wally-config.vh index 24c0a13a8..e9bd708f0 100644 --- a/wally-pipelined/config/coremark_bare/wally-config.vh +++ b/wally-pipelined/config/coremark_bare/wally-config.vh @@ -89,5 +89,5 @@ /* verilator lint_off ASSIGNDLY */ /* verilator lint_off PINCONNECTEMPTY */ -`define TWO_BIT_PRELOAD "../config/coremark_bare/twoBitPRedictor.txt" +`define TWO_BIT_PRELOAD "../config/coremark_bare/twoBitPredictor.txt" `define BTB_PRELOAD "../config/coremark_bare/BTBPredictor.txt" diff --git a/wally-pipelined/regression/wally-coremark_bare.do b/wally-pipelined/regression/wally-coremark_bare.do index 421ef6d5f..d6c242aa1 100644 --- a/wally-pipelined/regression/wally-coremark_bare.do +++ b/wally-pipelined/regression/wally-coremark_bare.do @@ -93,7 +93,7 @@ add wave -divider RAM add wave -hex -r /testbench/dut/uncore/dtim/RAM add wave -divider Misc add wave -divider -add wave -hex -r /testbench/* +#add wave -hex -r /testbench/* -- Set Wave Output Items TreeUpdate [SetDefaultTree] @@ -112,5 +112,5 @@ set DefaultRadix hexadecimal #run 7402000 #run 12750 #run -all -run 3000 +run 5000 #quit From 90946d61c5c608149ef31fbb60541562a959aed4 Mon Sep 17 00:00:00 2001 From: Teo Ene Date: Wed, 17 Mar 2021 15:02:15 -0500 Subject: [PATCH 24/26] fix to last commit --- wally-pipelined/testbench/testbench-coremark_bare.sv | 1 + 1 file changed, 1 insertion(+) diff --git a/wally-pipelined/testbench/testbench-coremark_bare.sv b/wally-pipelined/testbench/testbench-coremark_bare.sv index ea7e26d5d..f3bb22f88 100644 --- a/wally-pipelined/testbench/testbench-coremark_bare.sv +++ b/wally-pipelined/testbench/testbench-coremark_bare.sv @@ -34,6 +34,7 @@ module testbench(); string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; logic [`XLEN-1:0] meminit; string tests[]; + string ProgramAddrMapFile, ProgramLabelMapFile; logic [`AHBW-1:0] HRDATAEXT; logic HREADYEXT, HRESPEXT; logic [31:0] HADDR; From e6661ea26adf34ace34bd2cddd5a957abdf0806c Mon Sep 17 00:00:00 2001 From: Teo Ene Date: Wed, 17 Mar 2021 15:07:02 -0500 Subject: [PATCH 25/26] fix to last commit --- wally-pipelined/regression/wally-coremark_bare.do | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/regression/wally-coremark_bare.do b/wally-pipelined/regression/wally-coremark_bare.do index d6c242aa1..a933a8445 100644 --- a/wally-pipelined/regression/wally-coremark_bare.do +++ b/wally-pipelined/regression/wally-coremark_bare.do @@ -28,7 +28,7 @@ vlib work # because vsim will run vopt # default to config/coremark, but allow this to be overridden at the command line. For example: -vlog +incdir+../config/coremark_bare ../testbench/testbench-coremark_bare.sv ../src/*/*.sv -suppress 2583 +vlog +incdir+../config/coremark_bare ../testbench/testbench-coremark_bare.sv ../testbench/function_radix.sv ../src/*/*.sv -suppress 2583 # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals From 29634f1475ffaa8d9984f00f096bde66033fb1e3 Mon Sep 17 00:00:00 2001 From: Teo Ene Date: Wed, 17 Mar 2021 15:16:01 -0500 Subject: [PATCH 26/26] Temporarily reverted my last few commits --- wally-pipelined/regression/wally-pipelined.do | 2 +- wally-pipelined/testbench/testbench-coremark_bare.sv | 11 ++--------- 2 files changed, 3 insertions(+), 10 deletions(-) diff --git a/wally-pipelined/regression/wally-pipelined.do b/wally-pipelined/regression/wally-pipelined.do index 5f3b0d710..cabcfe153 100644 --- a/wally-pipelined/regression/wally-pipelined.do +++ b/wally-pipelined/regression/wally-pipelined.do @@ -30,7 +30,7 @@ vlib work # default to config/rv64ic, but allow this to be overridden at the command line. For example: # do wally-pipelined.do ../config/rv32ic switch $argc { - 0 {vlog +incdir+../config/rv64ic ../testbench/testbench-imperas.sv ../testbench/function_radix.sv ../src/*/*.sv -suppress 2583} + 0 {vlog +incdir+../config/rv64ic ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583} 1 {vlog +incdir+$1 ../testbench/testbench-imperas.sv ../testbench/function_radix.sv ../src/*/*.sv -suppress 2583} } # start and run simulation diff --git a/wally-pipelined/testbench/testbench-coremark_bare.sv b/wally-pipelined/testbench/testbench-coremark_bare.sv index f3bb22f88..d0ac7f286 100644 --- a/wally-pipelined/testbench/testbench-coremark_bare.sv +++ b/wally-pipelined/testbench/testbench-coremark_bare.sv @@ -34,7 +34,6 @@ module testbench(); string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; logic [`XLEN-1:0] meminit; string tests[]; - string ProgramAddrMapFile, ProgramLabelMapFile; logic [`AHBW-1:0] HRDATAEXT; logic HREADYEXT, HRESPEXT; logic [31:0] HADDR; @@ -77,8 +76,8 @@ module testbench(); $readmemh(memfilename, dut.uncore.dtim.RAM); for(j=2371; j < 65535; j = j+1) dut.uncore.dtim.RAM[j] = 64'b0; - ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.objdump.addr"; - ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.objdump.lab"; +// ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.objdump.addr"; +// ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64I.bare.elf.objdump.lab"; reset = 1; # 22; reset = 0; end // generate clock to sequence tests @@ -95,12 +94,6 @@ module testbench(); end end - if (1 == 1) begin : functionRadix - function_radix function_radix(.reset(reset), - .ProgramAddrMapFile(ProgramAddrMapFile), - .ProgramLabelMapFile(ProgramLabelMapFile)); - end - initial begin $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.DirPredictor.memory.memory); $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.TargetPredictor.memory.memory);