Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Minor cleanup

Browse Source
This commit is contained in:
James E. Stine 2021-04-02 08:20:44 -05:00
parent 82cd900b65
commit e38e7aff8e
3 changed files with 0 additions and 2048 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1921
wally-pipelined/src/muldiv/div.sv~
View File

File diff suppressed because it is too large Load Diff

21
wally-pipelined/src/muldiv/div/div.c~
View File

@ -1,21 +0,0 @@
#include <stdio.h>
#include <math.h>
#include <inttypes.h>
int main() {
uint64_t N;
uint64_t D;
uint64_t Q;
N = 0xc9649f05a8e1a8bb;
D = 0x82f6747f707af2c0;
printf("N = %" PRIx64 "\n", N);
printf("D = %" PRIx64 "\n", D);
printf("Q = %" PRIx64 "\n", Q);
printf("R = %" PRIx64 "\n", N%D);
}

106
wally-pipelined/src/muldiv/div/shifters_div.sv~
View File

@ -1,106 +0,0 @@
module shifter_l64 (Z, A, Shift);
input logic [63:0] A;
input logic [5:0] Shift;
logic [63:0] stage1;
logic [63:0] stage2;
logic [63:0] stage3;
logic [63:0] stage4;
logic [63:0] stage5;
logic [31:0] thirtytwozeros = 32'h0;
logic [15:0] sixteenzeros = 16'h0;
logic [ 7:0] eightzeros = 8'h0;
logic [ 3:0] fourzeros = 4'h0;
logic [ 1:0] twozeros = 2'b00;
logic onezero = 1'b0;
output logic [63:0] Z;
mux21x64 mx01(stage1, A, {A[31:0], thirtytwozeros}, Shift[5]);
mux21x64 mx02(stage2, stage1, {stage1[47:0], sixteenzeros}, Shift[4]);
mux21x64 mx03(stage3, stage2, {stage2[55:0], eightzeros}, Shift[3]);
mux21x64 mx04(stage4, stage3, {stage3[59:0], fourzeros}, Shift[2]);
mux21x64 mx05(stage5, stage4, {stage4[61:0], twozeros}, Shift[1]);
mux21x64 mx06(Z, stage5, {stage5[62:0], onezero}, Shift[0]);
endmodule // shifter_l64
module shifter_r64 (Z, A, Shift);
input logic [63:0] A;
input logic [5:0] Shift;
logic [63:0] stage1;
logic [63:0] stage2;
logic [63:0] stage3;
logic [63:0] stage4;
logic [63:0] stage5;
logic [31:0] thirtytwozeros = 32'h0;
logic [15:0] sixteenzeros = 16'h0;
logic [ 7:0] eightzeros = 8'h0;
logic [ 3:0] fourzeros = 4'h0;
logic [ 1:0] twozeros = 2'b00;
logic onezero = 1'b0;
output logic [63:0] Z;
mux21x64 mx01(stage1, A, {thirtytwozeros, A[63:32]}, Shift[5]);
mux21x64 mx02(stage2, stage1, {sixteenzeros, stage1[63:16]}, Shift[4]);
mux21x64 mx03(stage3, stage2, {eightzeros, stage2[63:8]}, Shift[3]);
mux21x64 mx04(stage4, stage3, {fourzeros, stage3[63:4]}, Shift[2]);
mux21x64 mx05(stage5, stage4, {twozeros, stage4[63:2]}, Shift[1]);
mux21x64 mx06(Z, stage5, {onezero, stage5[63:1]}, Shift[0]);
endmodule // shifter_r64
module shifter_l32 (Z, A, Shift);
input logic [31:0] A;
input logic [4:0] Shift;
logic [31:0] stage1;
logic [31:0] stage2;
logic [31:0] stage3;
logic [31:0] stage4;
logic [15:0] sixteenzeros = 16'h0;
logic [ 7:0] eightzeros = 8'h0;
logic [ 3:0] fourzeros = 4'h0;
logic [ 1:0] twozeros = 2'b00;
logic onezero = 1'b0;
output logic [31:0] Z;
mux21x32 mx01(stage1, A, {A[15:0], sixteenzeros}, Shift[4]);
mux21x32 mx02(stage2, stage1, {stage1[23:0], eightzeros}, Shift[3]);
mux21x32 mx03(stage3, stage2, {stage2[27:0], fourzeros}, Shift[2]);
mux21x32 mx04(stage4, stage3, {stage3[29:0], twozeros}, Shift[1]);
mux21x32 mx05(Z , stage4, {stage4[30:0], onezero}, Shift[0]);
endmodule // shifter_l32
module shifter_r32 (Z, A, Shift);
input logic [31:0] A;
input logic [4:0] Shift;
logic [31:0] stage1;
logic [31:0] stage2;
logic [31:0] stage3;
logic [31:0] stage4;
logic [15:0] sixteenzeros = 16'h0;
logic [ 7:0] eightzeros = 8'h0;
logic [ 3:0] fourzeros = 4'h0;
logic [ 1:0] twozeros = 2'b00;
logic onezero = 1'b0;
output logic [31:0] Z;
mux21x32 mx01(stage1, A, {sixteenzeros, A[31:16]}, Shift[4]);
mux21x32 mx02(stage2, stage1, {eightzeros, stage1[31:8]}, Shift[3]);
mux21x32 mx03(stage3, stage2, {fourzeros, stage2[31:4]}, Shift[2]);
mux21x32 mx04(stage4, stage3, {twozeros, stage3[31:2]}, Shift[1]);
mux21x32 mx05(Z , stage4, {onezero, stage4[31:1]}, Shift[0]);
endmodule // shifter_r32