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Added rem/div operation to postprocessor

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This commit is contained in:
cturek 2022-11-02 17:49:40 +00:00
parent e8d7607e87
commit e37f564e84
2 changed files with 12 additions and 8 deletions
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5
pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
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@ -79,5 +79,8 @@ module fdivsqrt(
.X,.Dpreproc, .FirstWS(WS), .FirstWC(WC), .X,.Dpreproc, .FirstWS(WS), .FirstWC(WC),
.DivStartE, .Xe(XeE), .Ye(YeE), .XZeroE, .YZeroE, .DivStartE, .Xe(XeE), .Ye(YeE), .XZeroE, .YZeroE,
.DivBusy); .DivBusy);
fdivsqrtpostproc fdivsqrtpostproc(.WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, .SqrtM, .SpecialCaseM, .QmM, .WZero, .DivSM); fdivsqrtpostproc fdivsqrtpostproc(
.WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun,
.SqrtM, .SpecialCaseM, .remOp(Funct3E[1]),
.QmM, .WZero, .DivSM);
endmodule endmodule

15
pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
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@ -31,13 +31,14 @@
`include "wally-config.vh" `include "wally-config.vh"
module fdivsqrtpostproc( module fdivsqrtpostproc(
input logic [`DIVb+3:0] WS, WC, input logic [`DIVb+3:0] WS, WC,
input logic [`DIVN-2:0] D, // U0.N-1 input logic [`DIVN-2:0] D, // U0.N-1
input logic [`DIVb:0] FirstU, FirstUM, input logic [`DIVb:0] FirstU, FirstUM,
input logic [`DIVb+1:0] FirstC, input logic [`DIVb+1:0] FirstC,
input logic Firstun, input logic Firstun,
input logic SqrtM, input logic SqrtM,
input logic SpecialCaseM, input logic SpecialCaseM,
input logic remOp,
output logic [`DIVb:0] QmM, output logic [`DIVb:0] QmM,
output logic WZero, output logic WZero,
output logic DivSM output logic DivSM