Encapsulated dtim.

pipelined/src/lsu/busdp.sv

@@ -5,6 +5,10 @@
 // Modified: 
 //
 // Purpose: Bus data path.
+// Bus Side logic
+// register the fetch data from the next level of memory.
+// This register should be necessary for timing.  There is no register in the uncore or
+// ahblite controller between the memories and this cache.
 // 
 // A component of the Wally configurable RISC-V project.
 // 

pipelined/src/lsu/dtim.sv

@@ -0,0 +1,73 @@
+///////////////////////////////////////////
+// dtim.sv
+//
+// Written: Ross Thompson ross1728@gmail.com January 30, 2022
+// Modified: 
+//
+// Purpose: simple memory with bus or cache.
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// MIT LICENSE
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this 
+// software and associated documentation files (the "Software"), to deal in the Software 
+// without restriction, including without limitation the rights to use, copy, modify, merge, 
+// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons 
+// to whom the Software is furnished to do so, subject to the following conditions:
+//
+//   The above copyright notice and this permission notice shall be included in all copies or 
+//   substantial portions of the Software.
+//
+//   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, 
+//   INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 
+//   PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+//   BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
+//   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE 
+//   OR OTHER DEALINGS IN THE SOFTWARE.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module dtim #(parameter WORDSPERLINE)
+  (
+  input logic                 clk, reset,
+  input logic                 CPUBusy,
+  input logic [1:0]           LSURWM,
+  input logic [`XLEN-1:0]     IEUAdrM,
+  input logic [`XLEN-1:0]     IEUAdrE,
+  input logic                 TrapM, 
+  input logic [`XLEN-1:0]     FinalWriteDataM,
+  output logic [`XLEN-1:0]    ReadDataWordM,
+  output logic                BusStall,
+  output logic                LSUBusWrite,
+  output logic                LSUBusRead,
+  output logic                DCacheBusAck,
+  output logic                BusCommittedM,
+  output logic [`XLEN-1:0]    ReadDataWordMuxM,
+  output logic                DCacheStallM,
+  output logic                DCacheCommittedM,
+  output logic                DCacheWriteLine,
+  output logic                DCacheFetchLine,
+  output logic [`PA_BITS-1:0] DCacheBusAdr,
+  output logic [`XLEN-1:0]    ReadDataLineSetsM [WORDSPERLINE-1:0],
+  output logic                DCacheMiss,
+  output logic                DCacheAccess);
+
+    // *** adjust interface so write address doesn't need delaying; switch to standard RAM?
+    simpleram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
+        .clk, 
+        .a(CPUBusy | LSURWM[0] ? IEUAdrM[31:0] : IEUAdrE[31:0]),
+        .we(LSURWM[0] & ~TrapM),  // have to ignore write if Trap.
+        .wd(FinalWriteDataM), .rd(ReadDataWordM));
+
+    // since we have a local memory the bus connections are all disabled.
+    // There are no peripherals supported.
+    assign {BusStall, LSUBusWrite, LSUBusRead, DCacheBusAck, BusCommittedM} = '0;   
+    assign ReadDataWordMuxM = ReadDataWordM;
+    assign {DCacheStallM, DCacheCommittedM, DCacheWriteLine, DCacheFetchLine, DCacheBusAdr} = '0;
+    assign ReadDataLineSetsM[0] = '0;
+    assign {DCacheMiss, DCacheAccess} = '0;
+
+endmodule  
+  

pipelined/src/lsu/lsu.sv

@@ -216,35 +216,13 @@ module lsu (
   
 
   if (`MEM_DTIM) begin : dtim
-/*    Consider restructuring with higher level blocks.  Try drawing block diagrams with several pages of schematics,
+    dtim #(WORDSPERLINE) 
-  one for top level, one for each sublevel, alternate with either dtim or bus.  If this looks more satisfactory,
+    dtim(.clk, .reset, .CPUBusy, .LSURWM, .IEUAdrM, .IEUAdrE, .TrapM, .FinalWriteDataM, 
-  restructure code accordingly.
+         .ReadDataWordM, .BusStall, .LSUBusWrite,.LSUBusRead, .DCacheBusAck, .BusCommittedM,
+         .ReadDataWordMuxM, .DCacheStallM, .DCacheCommittedM, .DCacheWriteLine, 
+         .DCacheFetchLine, .DCacheBusAdr, .ReadDataLineSetsM, .DCacheMiss, .DCacheAccess);
 
-  dtim dtim (.clk, .CPUBusy, .LSURWM, .IEUAdrM, .IEUAdrE, .TrapM, .FinalWriteDataM, .ReadDataWordM,
-               .BusStallM, .LSUBusWrite, .LSUBusRead, .DCacheBusAck, .BusCommittedM,
-               .ReadDataWordMuxM, .DCacheStallM, .DCacheCommittedM, .DCacheWriteLine, .DCacheFetchLine, .DCacheBusAdr,
-               .ReadDataLineSetsM, .DCacheMiss, .DCacheAccess); */
-
-    // *** adjust interface so write address doesn't need delaying; switch to standard RAM?
-    simpleram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
-        .clk, 
-        .a(CPUBusy | LSURWM[0] ? IEUAdrM[31:0] : IEUAdrE[31:0]),
-        .we(LSURWM[0] & ~TrapM),  // have to ignore write if Trap.
-        .wd(FinalWriteDataM), .rd(ReadDataWordM));
-
-    // since we have a local memory the bus connections are all disabled.
-    // There are no peripherals supported.
-    assign {BusStall, LSUBusWrite, LSUBusRead, DCacheBusAck, BusCommittedM} = '0;   
-    assign ReadDataWordMuxM = ReadDataWordM;
-    assign {DCacheStallM, DCacheCommittedM, DCacheWriteLine, DCacheFetchLine, DCacheBusAdr} = '0;
-    assign ReadDataLineSetsM[0] = 0;
-    assign DCacheMiss = 1'b0; assign DCacheAccess = 1'b0;
   end else begin : bus  
-    // Bus Side logic
-    // register the fetch data from the next level of memory.
-    // This register should be necessary for timing.  There is no register in the uncore or
-    // ahblite controller between the memories and this cache.
-
     busdp #(WORDSPERLINE, LINELEN) 
     busdp(.clk, .reset,
           .LSUBusHRDATA, .LSUBusAck, .LSUBusWrite, .LSUBusRead, .LSUBusHWDATA, .LSUBusSize, 

pipelined/testbench/testbench-tim.sv

@@ -196,7 +196,7 @@ logic [3:0] dummy;
       else pathname = tvpaths[1]; */
       memfilename = {pathname, tests[test], ".elf.memfile"};
       //$readmemh(memfilename, dut.uncore.ram.ram.RAM);
-      $readmemh(memfilename, dut.core.lsu.dtim.ram.RAM);      
+      $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);      
 //      if(`MEM_DTIM == 1) $readmemh(memfilename, dut.core.lsu.dtim.ram.RAM);
 //`ifdef `MEM_IROM
 //          $display("here!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!");
@@ -258,7 +258,7 @@ logic [3:0] dummy;
         while (signature[i] !== 'bx) begin
           //$display("signature[%h] = %h", i, signature[i]);
 		  // *** have to figure out how to exclude shadowram when not using a dcache.
-          if (signature[i] !== dut.core.lsu.dtim.ram.RAM[testadr+i] &
+          if (signature[i] !== dut.core.lsu.dtim.dtim.ram.RAM[testadr+i] &
 	      (signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin
             if (signature[i+4] !== 'bx | signature[i] !== 32'hFFFFFFFF) begin
               // report errors unless they are garbage at the end of the sim
@@ -266,7 +266,7 @@ logic [3:0] dummy;
               errors = errors+1;
               $display("  Error on test %s result %d: adr = %h sim (D$) %h sim (TIM) = %h, signature = %h", 
                     //tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], dut.uncore.ram.ram.RAM[testadr+i], signature[i]);
-                       tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], dut.core.lsu.dtim.ram.RAM[testadr+i], signature[i]);
+                       tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], dut.core.lsu.dtim.dtim.ram.RAM[testadr+i], signature[i]);
               $stop;//***debug
             end
           end
@@ -290,7 +290,7 @@ logic [3:0] dummy;
             //pathname = tvpaths[tests[0]];
             memfilename = {pathname, tests[test], ".elf.memfile"};
             //$readmemh(memfilename, dut.uncore.ram.ram.RAM);
-            $readmemh(memfilename, dut.core.lsu.dtim.ram.RAM);
+            $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
             //if(`MEM_DTIM == 1) $readmemh(memfilename, dut.core.lsu.dtim.ram.RAM);
 /* -----\/----- EXCLUDED -----\/-----
 `ifdef `MEM_IROM