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simpleram address simplification
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@ -46,7 +46,7 @@ module simpleram #(parameter BASE=0, RANGE = 65535) (
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localparam MemEndAddr = (RANGE+BASE)>>1+(`XLEN/32);
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logic [`XLEN-1:0] RAM[BASE>>(1+`XLEN/32):(RANGE+BASE)>>1+(`XLEN/32)];
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logic [31:0] HWADDR, A;
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logic [31:0] AD;
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logic [`XLEN-1:0] HREADRam0;
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logic prevHREADYRam, risingHREADYRam;
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@ -56,28 +56,26 @@ module simpleram #(parameter BASE=0, RANGE = 65535) (
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assign initTrans = HREADY & HSELRam & (HTRANS != 2'b00);
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flopenr #(32) Adrreg(clk, 1'b0, 1'b1, Adr, A);
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flop #(32) Adrreg(clk, Adr, AD);
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/* verilator lint_off WIDTH */
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if (`XLEN == 64) begin:ramrw
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always_ff @(posedge clk) begin
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if (HWRITE & |HTRANS) RAM[A[31:3]] <= #1 HWDATA;
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if (HWRITE & |HTRANS) RAM[AD[31:3]] <= #1 HWDATA;
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end
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end else begin
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always_ff @(posedge clk) begin:ramrw
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if (HWRITE & |HTRANS) RAM[A[31:2]] <= #1 HWDATA;
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if (HWRITE & |HTRANS) RAM[AD[31:2]] <= #1 HWDATA;
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end
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end
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// read
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if(`XLEN == 64) begin: ramr
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assign HREADRam0 = RAM[A[31:3]];
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assign HREADRam = RAM[AD[31:3]];
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end else begin
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assign HREADRam0 = RAM[A[31:2]];
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assign HREADRam = RAM[AD[31:2]];
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end
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/* verilator lint_on WIDTH */
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assign HREADRam = HREADRam0;
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endmodule
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