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simpleram address simplification

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This commit is contained in:
David Harris 2022-01-25 18:17:33 +00:00
parent 7ad2eb009a
commit e3136c9a1e
1 changed files with 6 additions and 8 deletions
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14
pipelined/src/generic/flop/simpleram.sv
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@ -46,7 +46,7 @@ module simpleram #(parameter BASE=0, RANGE = 65535) (
localparam MemEndAddr = (RANGE+BASE)>>1+(`XLEN/32);
logic [`XLEN-1:0] RAM[BASE>>(1+`XLEN/32):(RANGE+BASE)>>1+(`XLEN/32)];
logic [31:0] HWADDR, A;
logic [31:0] AD;
logic [`XLEN-1:0] HREADRam0;
logic prevHREADYRam, risingHREADYRam;
@ -56,28 +56,26 @@ module simpleram #(parameter BASE=0, RANGE = 65535) (
assign initTrans = HREADY & HSELRam & (HTRANS != 2'b00);
flopenr #(32) Adrreg(clk, 1'b0, 1'b1, Adr, A);
flop #(32) Adrreg(clk, Adr, AD);
/* verilator lint_off WIDTH */
if (`XLEN == 64) begin:ramrw
always_ff @(posedge clk) begin
if (HWRITE & |HTRANS) RAM[A[31:3]] <= #1 HWDATA;
if (HWRITE & |HTRANS) RAM[AD[31:3]] <= #1 HWDATA;
end
end else begin
always_ff @(posedge clk) begin:ramrw
if (HWRITE & |HTRANS) RAM[A[31:2]] <= #1 HWDATA;
if (HWRITE & |HTRANS) RAM[AD[31:2]] <= #1 HWDATA;
end
end
// read
if(`XLEN == 64) begin: ramr
assign HREADRam0 = RAM[A[31:3]];
assign HREADRam = RAM[AD[31:3]];
end else begin
assign HREADRam0 = RAM[A[31:2]];
assign HREADRam = RAM[AD[31:2]];
end
/* verilator lint_on WIDTH */
assign HREADRam = HREADRam0;
endmodule