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Possible plic fix?
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@ -176,7 +176,8 @@ module plic (
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end
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end
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// pending interrupt requests
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// pending interrupt requests
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assign nextIntPending = (intPending | requests) & ~intInProgress;
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//assign nextIntPending = (intPending | requests) & ~intInProgress;
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assign nextIntPending = requests;
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flopr #(`N) intPendingFlop(HCLK,~HRESETn,nextIntPending,intPending);
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flopr #(`N) intPendingFlop(HCLK,~HRESETn,nextIntPending,intPending);
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// context-dependent signals
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// context-dependent signals
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