diff --git a/.gitignore b/.gitignore
index 0d8418068..a056d82f8 100644
--- a/.gitignore
+++ b/.gitignore
@@ -210,4 +210,4 @@ sim/vcs/sim_out*
 sim/vcs/simprofile_dir
 sim/vcs/ucli.key
 sim/vcs/verdi_config_file
-sim/verilator/testbench.vcd 
+sim/*/testbench.vcd 
diff --git a/benchmarks/coremark/Makefile b/benchmarks/coremark/Makefile
index 527868eac..63afc34bf 100644
--- a/benchmarks/coremark/Makefile
+++ b/benchmarks/coremark/Makefile
@@ -12,6 +12,7 @@ sources=$(cmbase)/core_main.c $(cmbase)/core_list_join.c $(cmbase)/coremark.h  \
 	$(PORT_DIR)/crt.S $(PORT_DIR)/encoding.h $(PORT_DIR)/util.h $(PORT_DIR)/syscalls.c
 ABI := $(if $(findstring "64","$(XLEN)"),lp64,ilp32)
 ARCH := rv$(XLEN)im_zicsr_zba_zbb_zbs
+CONFIG := rv$(XLEN)gc
 #ARCH := rv$(XLEN)gc
 #ARCH := rv$(XLEN)imc_zicsr
 #ARCH := rv$(XLEN)im_zicsr
@@ -26,9 +27,9 @@ PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \
 
 all: $(work_dir)/coremark.bare.riscv.elf.memfile
 
-run:
+run: $(work_dir)/coremark.bare.riscv.elf.memfile
 #	time wsim rv$(XLEN)gc coremark --sim verilator 2>&1 | tee $(work_dir)/coremark.sim.log
-	time wsim rv$(XLEN)gc coremark 2>&1 | tee $(work_dir)/coremark.sim.log
+	time wsim ${CONFIG} coremark 2>&1 | tee $(work_dir)/coremark.sim.log
 
 $(work_dir)/coremark.bare.riscv.elf.memfile: $(work_dir)/coremark.bare.riscv
 	riscv64-unknown-elf-objdump -D $< > $<.elf.objdump
diff --git a/config/derivlist.txt b/config/derivlist.txt
index 3f6a869d9..66c61f426 100644
--- a/config/derivlist.txt
+++ b/config/derivlist.txt
@@ -237,6 +237,9 @@ BURST_EN            1
 
 # Branch predictor simulations
 
+deriv nobpred_rv32gc rv32gc 
+BPRED_SUPPORTED     0
+
 deriv bpred_GSHARE_6_16_10_1_rv32gc rv32gc 
 BPRED_SIZE          32'd6