From e2191e3637cad09cc248e396acd907c8b95e54a2 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Tue, 8 Feb 2022 09:47:01 -0600
Subject: [PATCH] Preparing to make a major change to the cache's write
 enables.

---
 pipelined/src/cache/cache.sv    |  7 +++++--
 pipelined/src/cache/cacheway.sv | 12 ++++++------
 2 files changed, 11 insertions(+), 8 deletions(-)

diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv
index 5089672c3..f70467f4a 100644
--- a/pipelined/src/cache/cache.sv
+++ b/pipelined/src/cache/cache.sv
@@ -121,8 +121,8 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, DCACHE = 1) (
   // Array of cache ways, along with victim, hit, dirty, and read merging logic
   cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN) CacheWays[NUMWAYS-1:0](
     .clk, .reset, .RAdr, .PAdr,
-		.WriteEnable(SRAMWayWriteEnable),
-		.WriteWordEnable(SRAMWordEnable),
+		.SRAMWayWriteEnable,
+		.SRAMWordEnable,
 		.TagWriteEnable(SRAMLineWayWriteEnable), 
 		.WriteData(SRAMWriteData),
         .SetValid(SetValidWay), .ClearValid(ClearValidWay), .SetDirty(SetDirtyWay), .ClearDirty(ClearDirtyWay),
@@ -157,9 +157,12 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, DCACHE = 1) (
   /////////////////////////////////////////////////////////////////////////////////////////////
  
   // *** Ross considering restructuring
+  // move decoder and wordwritenable into cacheway.
   onehotdecoder #(LOGWPL) adrdec(
     .bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecoded));
   assign SRAMWordEnable = SRAMLineWriteEnable ? '1 : MemPAdrDecoded; // OR
+
+  
   assign SRAMLineWayWriteEnable = SRAMLineWriteEnable ? VictimWay : '0; // AND
   assign SRAMWordWayWriteEnable = SRAMWordWriteEnable ? WayHit : '0; // AND
   mux2 #(NUMWAYS) WriteEnableMux(.d0(SRAMWordWayWriteEnable), .d1(VictimWay), 
diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv
index 7cb2084ad..09fcbfa29 100644
--- a/pipelined/src/cache/cacheway.sv
+++ b/pipelined/src/cache/cacheway.sv
@@ -37,8 +37,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
 
   input logic [$clog2(NUMLINES)-1:0] RAdr,
   input logic [`PA_BITS-1:0]         PAdr,
-  input logic                        WriteEnable,
-  input logic [LINELEN/`XLEN-1:0]    WriteWordEnable,
+  input logic                        SRAMWayWriteEnable,
+  input logic [LINELEN/`XLEN-1:0]    SRAMWordEnable,
   input logic                        TagWriteEnable,
   input logic [LINELEN-1:0]          WriteData,
   input logic                        SetValid,
@@ -68,7 +68,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
   logic [$clog2(NUMLINES)-1:0] 		  RAdrD;
   logic 							  SetValidD, ClearValidD;
   logic 							  SetDirtyD, ClearDirtyD;
-  logic 							  WriteEnableD;
+  logic 							  SRAMWayWriteEnableD;
 
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Tag Array
@@ -93,7 +93,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
     sram1rw #(.DEPTH(NUMLINES), .WIDTH(`XLEN)) CacheDataMem(.clk(clk), .Adr(RAdr),
       .ReadData(ReadDataLine[(words+1)*`XLEN-1:words*`XLEN] ),
       .WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]),
-      .WriteEnable(WriteEnable & WriteWordEnable[words]));
+      .WriteEnable(SRAMWayWriteEnable & SRAMWordEnable[words]));
   end
 
   // AND portion of distributed read multiplexers
@@ -112,8 +112,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
 	end
   // *** consider revisiting whether these delays are the best option? 
   flop #($clog2(NUMLINES)) RAdrDelayReg(clk, RAdr, RAdrD);
-  flop #(3) ValidCtrlDelayReg(clk, {SetValid, ClearValid, WriteEnable},
-    {SetValidD, ClearValidD, WriteEnableD});
+  flop #(3) ValidCtrlDelayReg(clk, {SetValid, ClearValid, SRAMWayWriteEnable},
+    {SetValidD, ClearValidD, SRAMWayWriteEnableD});
   assign Valid = ValidBits[RAdrD];
 
   /////////////////////////////////////////////////////////////////////////////////////////////