From c9b56f9acca5bc07cf205cda4dd24662e49a5559 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Wed, 1 Feb 2023 05:06:56 -0800
Subject: [PATCH 1/9] Only add memory libraries when targeting 28nm

---
 synthDC/.synopsys_dc.setup | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup
index 8b0ba0309..492256568 100755
--- a/synthDC/.synopsys_dc.setup
+++ b/synthDC/.synopsys_dc.setup
@@ -48,10 +48,12 @@ set cache_read   $cache_write
 lappend search_path ./scripts
 lappend search_path ./hdl
 lappend search_path ./mapped
-set memory /home/jstine/WallyMem/rv64gc/
-lappend target_library $memory/ts3n28hpcpa128x64m8m_130a/NLDM/ts3n28hpcpa128x64m8m_tt0p9v25c.db
-lappend target_library $memory/ts1n28hpcpsvtb64x128m4sw_180a/NLDM/ts1n28hpcpsvtb64x128m4sw_tt0p9v25c.db
-lappend target_library $memory/ts1n28hpcpsvtb64x44m4sw_180a/NLDM/ts1n28hpcpsvtb64x44m4sw_tt0p9v25c.db
+if {$tech="tsmc28"} {}
+    set memory /home/jstine/WallyMem/rv64gc/
+    lappend target_library $memory/ts3n28hpcpa128x64m8m_130a/NLDM/ts3n28hpcpa128x64m8m_tt0p9v25c.db
+    lappend target_library $memory/ts1n28hpcpsvtb64x128m4sw_180a/NLDM/ts1n28hpcpsvtb64x128m4sw_tt0p9v25c.db
+    lappend target_library $memory/ts1n28hpcpsvtb64x44m4sw_180a/NLDM/ts1n28hpcpsvtb64x44m4sw_tt0p9v25c.db
+}
 
 # Set up User Information
 set company "Oklahoma State University"

From 129380db0bdc833046ebbef9c8072285c51ed771 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Wed, 1 Feb 2023 05:49:30 -0800
Subject: [PATCH 2/9] Fixed typo in DC setup for memories

---
 synthDC/.synopsys_dc.setup | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup
index 492256568..2fdc11c27 100755
--- a/synthDC/.synopsys_dc.setup
+++ b/synthDC/.synopsys_dc.setup
@@ -48,7 +48,7 @@ set cache_read   $cache_write
 lappend search_path ./scripts
 lappend search_path ./hdl
 lappend search_path ./mapped
-if {$tech="tsmc28"} {}
+if {$tech == "tsmc28"} {
     set memory /home/jstine/WallyMem/rv64gc/
     lappend target_library $memory/ts3n28hpcpa128x64m8m_130a/NLDM/ts3n28hpcpa128x64m8m_tt0p9v25c.db
     lappend target_library $memory/ts1n28hpcpsvtb64x128m4sw_180a/NLDM/ts1n28hpcpsvtb64x128m4sw_tt0p9v25c.db

From 93f57402df76f4acbb88446e14889f76bfdc4f59 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Wed, 1 Feb 2023 15:43:52 -0800
Subject: [PATCH 3/9] Removed O2 from fir Makefile to be consistent with lab.

---
 examples/C/fir/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/examples/C/fir/Makefile b/examples/C/fir/Makefile
index c27e423a5..4e3991e46 100644
--- a/examples/C/fir/Makefile
+++ b/examples/C/fir/Makefile
@@ -5,7 +5,7 @@ $(TARGET).objdump: $(TARGET)
 	spike $(TARGET)
     
 $(TARGET): $(TARGET).c Makefile
-	riscv64-unknown-elf-gcc -o $(TARGET) -g -O2\
+	riscv64-unknown-elf-gcc -o $(TARGET) -g\
 	  -march=rv64gc -mabi=lp64d -mcmodel=medany \
 	  -nostdlib -static -lm -fno-tree-loop-distribute-patterns \
 	  -T../common/test.ld -I../common \

From 99d179dd3e37072dfc17cb59d44655c873abe0b1 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 2 Feb 2023 14:14:11 -0800
Subject: [PATCH 4/9] Removed pipelined level of hierarchy

---
 .gitignore                                    | 23 ++++++++-----------
 Install                                       |  2 +-
 Makefile                                      |  4 ++--
 README.md                                     |  2 +-
 benchmarks/coremark/Makefile                  |  2 +-
 benchmarks/embench/Makefile                   |  2 +-
 .../buildroot/wally-config.vh                 |  0
 .../config => config}/fpga/wally-config.vh    |  0
 .../config => config}/rv32e/wally-config.vh   |  0
 .../config => config}/rv32gc/wally-config.vh  |  0
 .../config => config}/rv32i/wally-config.vh   |  0
 .../config => config}/rv32imc/wally-config.vh |  0
 .../rv64fpquad/wally-config.vh                |  0
 .../config => config}/rv64gc/wally-config.vh  |  0
 .../config => config}/rv64i/wally-config.vh   |  0
 {pipelined/config => config}/shared/README    |  0
 .../config => config}/shared/wally-shared.vh  |  0
 fpga/README.md                                |  2 +-
 fpga/generator/Makefile                       |  2 +-
 fpga/generator/wally.tcl                      |  2 +-
 {pipelined/regression => regression}/Makefile |  0
 .../buildrootBugFinder.py                     |  0
 .../regression => regression}/fpga-wave.do    |  0
 .../regression => regression}/imperas.ic      |  0
 .../regression => regression}/lint-wally      |  0
 .../regression => regression}/linux-wave.do   |  0
 .../regression => regression}/make-tests.sh   |  2 +-
 .../makefile-memfile                          |  0
 .../regression-wally                          |  0
 .../run-imperasdv-tests.bash                  |  0
 .../regression => regression}/sim-buildroot   |  0
 .../sim-buildroot-batch                       |  0
 .../regression => regression}/sim-imperas     |  0
 .../regression => regression}/sim-testfloat   |  0
 .../sim-testfloat-batch                       |  0
 .../regression => regression}/sim-wally       |  0
 .../regression => regression}/sim-wally-batch |  0
 .../slack-notifier/slack-notifier.py          |  0
 {pipelined/regression => regression}/test     |  0
 .../regression => regression}/testfloat.do    |  0
 .../wally-pipelined-batch.do                  |  0
 .../wally-pipelined-imperas-no-idv.do         |  0
 .../wally-pipelined-imperas.do                |  0
 .../wally-pipelined.do                        |  0
 .../regression => regression}/wave-all.do     |  0
 .../wave-dos/ahb-muldiv.do                    |  0
 .../wave-dos/ahb-waves.do                     |  0
 .../wave-dos/cache-waves.do                   |  0
 .../wave-dos/default-waves.do                 |  0
 .../wave-dos/generic.do                       |  0
 .../wave-dos/linux-waves.do                   |  0
 .../wave-dos/peripheral-waves.do              |  0
 .../regression => regression}/wave-fpu.do     |  0
 {pipelined/regression => regression}/wave.do  |  0
 setup.imperas.sh                              |  2 +-
 {pipelined/src => src}/cache/cache.sv         |  0
 {pipelined/src => src}/cache/cacheLRU.sv      |  0
 {pipelined/src => src}/cache/cachefsm.sv      |  0
 {pipelined/src => src}/cache/cacheway.sv      |  0
 .../src => src}/cache/subcachelineread.sv     |  0
 .../src => src}/ebu/ahbcacheinterface.sv      |  0
 {pipelined/src => src}/ebu/ahbinterface.sv    |  0
 {pipelined/src => src}/ebu/buscachefsm.sv     |  0
 {pipelined/src => src}/ebu/busfsm.sv          |  0
 .../src => src}/ebu/controllerinputstage.sv   |  0
 {pipelined/src => src}/ebu/ebu.sv             |  0
 {pipelined/src => src}/ebu/ebuarbfsm.sv       |  0
 {pipelined/src => src}/fpu/fclassify.sv       |  0
 {pipelined/src => src}/fpu/fcmp.sv            |  0
 {pipelined/src => src}/fpu/fctrl.sv           |  0
 {pipelined/src => src}/fpu/fcvt.sv            |  0
 .../src => src}/fpu/fdivsqrt/fdivsqrt.sv      |  0
 .../fpu/fdivsqrt/fdivsqrtexpcalc.sv           |  0
 .../src => src}/fpu/fdivsqrt/fdivsqrtfgen2.sv |  0
 .../src => src}/fpu/fdivsqrt/fdivsqrtfgen4.sv |  0
 .../src => src}/fpu/fdivsqrt/fdivsqrtfsm.sv   |  0
 .../src => src}/fpu/fdivsqrt/fdivsqrtiter.sv  |  0
 .../fpu/fdivsqrt/fdivsqrtpostproc.sv          |  0
 .../fpu/fdivsqrt/fdivsqrtpreproc.sv           |  0
 .../src => src}/fpu/fdivsqrt/fdivsqrtqsel2.sv |  0
 .../src => src}/fpu/fdivsqrt/fdivsqrtqsel4.sv |  0
 .../fpu/fdivsqrt/fdivsqrtqsel4cmp.sv          |  0
 .../fpu/fdivsqrt/fdivsqrtstage2.sv            |  0
 .../fpu/fdivsqrt/fdivsqrtstage4.sv            |  0
 .../fpu/fdivsqrt/fdivsqrtuotfc2.sv            |  0
 .../fpu/fdivsqrt/fdivsqrtuotfc4.sv            |  0
 {pipelined/src => src}/fpu/fhazard.sv         |  0
 {pipelined/src => src}/fpu/fma/fma.sv         |  0
 {pipelined/src => src}/fpu/fma/fmaadd.sv      |  0
 {pipelined/src => src}/fpu/fma/fmaalign.sv    |  0
 {pipelined/src => src}/fpu/fma/fmaexpadd.sv   |  0
 {pipelined/src => src}/fpu/fma/fmalza.sv      |  0
 {pipelined/src => src}/fpu/fma/fmamult.sv     |  0
 {pipelined/src => src}/fpu/fma/fmasign.sv     |  0
 {pipelined/src => src}/fpu/fpu.sv             |  0
 {pipelined/src => src}/fpu/fregfile.sv        |  0
 {pipelined/src => src}/fpu/fsgninj.sv         |  0
 .../src => src}/fpu/postproc/cvtshiftcalc.sv  |  0
 .../src => src}/fpu/postproc/divshiftcalc.sv  |  0
 {pipelined/src => src}/fpu/postproc/flags.sv  |  0
 .../src => src}/fpu/postproc/fmashiftcalc.sv  |  0
 .../src => src}/fpu/postproc/negateintres.sv  |  0
 .../src => src}/fpu/postproc/normshift.sv     |  0
 .../src => src}/fpu/postproc/postprocess.sv   |  0
 .../src => src}/fpu/postproc/resultsign.sv    |  0
 {pipelined/src => src}/fpu/postproc/round.sv  |  0
 .../src => src}/fpu/postproc/roundsign.sv     |  0
 .../fpu/postproc/shiftcorrection.sv           |  0
 .../src => src}/fpu/postproc/specialcase.sv   |  0
 {pipelined/src => src}/fpu/unpack.sv          |  0
 {pipelined/src => src}/fpu/unpackinput.sv     |  0
 {pipelined/src => src}/generic/adder.sv       |  0
 {pipelined/src => src}/generic/aplusbeq0.sv   |  0
 {pipelined/src => src}/generic/arrs.sv        |  0
 {pipelined/src => src}/generic/binencoder.sv  |  0
 {pipelined/src => src}/generic/clockgater.sv  |  0
 {pipelined/src => src}/generic/counter.sv     |  0
 {pipelined/src => src}/generic/csa.sv         |  0
 {pipelined/src => src}/generic/decoder.sv     |  0
 {pipelined/src => src}/generic/flop/flop.sv   |  0
 {pipelined/src => src}/generic/flop/flopen.sv |  0
 .../src => src}/generic/flop/flopenl.sv       |  0
 .../src => src}/generic/flop/flopenr.sv       |  0
 .../src => src}/generic/flop/flopenrc.sv      |  0
 .../src => src}/generic/flop/flopens.sv       |  0
 {pipelined/src => src}/generic/flop/flopr.sv  |  0
 {pipelined/src => src}/generic/flop/floprc.sv |  0
 .../src => src}/generic/flop/synchronizer.sv  |  0
 {pipelined/src => src}/generic/lzc.sv         |  0
 .../src => src}/generic/mem/ram1p1rwbe.sv     |  0
 .../generic/mem/ram1p1rwbe_64x128.sv          |  0
 .../generic/mem/ram1p1rwbe_64x44.sv           |  0
 .../src => src}/generic/mem/ram2p1r1wbe.sv    |  0
 .../generic/mem/ram2p1r1wbe_1024x68.sv        |  0
 .../generic/mem/ram2p1r1wbe_64x32.sv          |  0
 {pipelined/src => src}/generic/mem/rom1p1r.sv |  0
 .../src => src}/generic/mem/rom1p1r_128x32.sv |  0
 .../src => src}/generic/mem/rom1p1r_128x64.sv |  0
 {pipelined/src => src}/generic/mux.sv         |  0
 {pipelined/src => src}/generic/neg.sv         |  0
 .../src => src}/generic/onehotdecoder.sv      |  0
 {pipelined/src => src}/generic/or_rows.sv     |  0
 .../src => src}/generic/priorityonehot.sv     |  0
 .../generic/prioritythermometer.sv            |  0
 {pipelined/src => src}/hazard/hazard.sv       |  0
 {pipelined/src => src}/ieu/alu.sv             |  0
 {pipelined/src => src}/ieu/comparator.sv      |  0
 {pipelined/src => src}/ieu/controller.sv      |  0
 {pipelined/src => src}/ieu/datapath.sv        |  0
 {pipelined/src => src}/ieu/extend.sv          |  0
 {pipelined/src => src}/ieu/forward.sv         |  0
 {pipelined/src => src}/ieu/ieu.sv             |  0
 {pipelined/src => src}/ieu/regfile.sv         |  0
 {pipelined/src => src}/ieu/shifter.sv         |  0
 {pipelined/src => src}/ifu/CodeAligner.py     |  0
 .../src => src}/ifu/bpred/RASPredictor.sv     |  0
 {pipelined/src => src}/ifu/bpred/bpred.sv     |  0
 {pipelined/src => src}/ifu/bpred/btb.sv       |  0
 .../src => src}/ifu/bpred/foldedgshare.sv     |  0
 .../src => src}/ifu/bpred/globalhistory.sv    |  0
 {pipelined/src => src}/ifu/bpred/gshare.sv    |  0
 .../ifu/bpred/localHistoryPredictor.sv        |  0
 {pipelined/src => src}/ifu/bpred/optgshare.sv |  0
 .../src => src}/ifu/bpred/satCounter2.sv      |  0
 .../ifu/bpred/speculativeglobalhistory.sv     |  0
 .../ifu/bpred/speculativegshare.sv            |  0
 .../src => src}/ifu/bpred/twoBitPredictor.sv  |  0
 {pipelined/src => src}/ifu/decompress.sv      |  0
 {pipelined/src => src}/ifu/ifu.sv             |  0
 {pipelined/src => src}/ifu/irom.sv            |  0
 {pipelined/src => src}/ifu/spill.sv           |  0
 {pipelined/src => src}/lsu/amoalu.sv          |  0
 {pipelined/src => src}/lsu/atomic.sv          |  0
 {pipelined/src => src}/lsu/dtim.sv            |  0
 {pipelined/src => src}/lsu/endianswap.sv      |  0
 {pipelined/src => src}/lsu/lrsc.sv            |  0
 {pipelined/src => src}/lsu/lsu.sv             |  0
 {pipelined/src => src}/lsu/subwordread.sv     |  0
 {pipelined/src => src}/lsu/subwordwrite.sv    |  0
 {pipelined/src => src}/lsu/swbytemask.sv      |  0
 {pipelined/src => src}/mdu/intdivrestoring.sv |  0
 .../src => src}/mdu/intdivrestoringstep.sv    |  0
 {pipelined/src => src}/mdu/mdu.sv             |  0
 {pipelined/src => src}/mdu/mul.sv             |  0
 {pipelined/src => src}/mmu/adrdec.sv          |  0
 {pipelined/src => src}/mmu/adrdecs.sv         |  0
 {pipelined/src => src}/mmu/hptw.sv            |  0
 {pipelined/src => src}/mmu/mmu.sv             |  0
 {pipelined/src => src}/mmu/pmachecker.sv      |  0
 {pipelined/src => src}/mmu/pmpadrdec.sv       |  0
 {pipelined/src => src}/mmu/pmpchecker.sv      |  0
 {pipelined/src => src}/mmu/tlb.sv             |  0
 {pipelined/src => src}/mmu/tlbcam.sv          |  0
 {pipelined/src => src}/mmu/tlbcamline.sv      |  0
 {pipelined/src => src}/mmu/tlbcontrol.sv      |  0
 {pipelined/src => src}/mmu/tlblru.sv          |  0
 {pipelined/src => src}/mmu/tlbmixer.sv        |  0
 {pipelined/src => src}/mmu/tlbram.sv          |  0
 {pipelined/src => src}/mmu/tlbramline.sv      |  0
 {pipelined/src => src}/mmu/vm64check.sv       |  0
 {pipelined/src => src}/privileged/csr.sv      |  0
 {pipelined/src => src}/privileged/csrc.sv     |  0
 {pipelined/src => src}/privileged/csri.sv     |  0
 {pipelined/src => src}/privileged/csrm.sv     |  0
 {pipelined/src => src}/privileged/csrs.sv     |  0
 {pipelined/src => src}/privileged/csrsr.sv    |  0
 {pipelined/src => src}/privileged/csru.sv     |  0
 {pipelined/src => src}/privileged/privdec.sv  |  0
 .../src => src}/privileged/privileged.sv      |  0
 {pipelined/src => src}/privileged/privmode.sv |  0
 .../src => src}/privileged/privpiperegs.sv    |  0
 {pipelined/src => src}/privileged/trap.sv     |  0
 {pipelined/src => src}/uncore/ahbapbbridge.sv |  0
 {pipelined/src => src}/uncore/clint_apb.sv    |  0
 {pipelined/src => src}/uncore/gpio_apb.sv     |  0
 {pipelined/src => src}/uncore/plic_apb.sv     |  0
 {pipelined/src => src}/uncore/ram_ahb.sv      |  0
 {pipelined/src => src}/uncore/rom_ahb.sv      |  0
 {pipelined/src => src}/uncore/uartPC16550D.sv |  0
 {pipelined/src => src}/uncore/uart_apb.sv     |  0
 {pipelined/src => src}/uncore/uncore.sv       |  0
 {pipelined/src => src}/wally/cvw.sv           |  0
 .../src => src}/wally/wallypipelinedcore.sv   |  0
 .../src => src}/wally/wallypipelinedsoc.sv    |  0
 synthDC/Makefile                              |  6 ++---
 synthDC/scripts/synth.tcl                     |  2 +-
 .../common/functionName.sv                    |  0
 .../common/instrNameDecTB.sv                  |  0
 .../common/instrTrackerTB.sv                  |  0
 .../common/wallyTracer.sv                     |  0
 {pipelined/testbench => testbench}/fp/case.sh |  0
 .../testbench => testbench}/sdc/ram2sdLoad.py |  0
 .../testbench => testbench}/sdc/ramdisk2.hex  |  0
 .../testbench => testbench}/sdc/run_tb.do     |  0
 .../testbench => testbench}/sdc/sdModel.sv    |  0
 .../testbench => testbench}/sdc/sd_crc_16.sv  |  0
 .../testbench => testbench}/sdc/sd_crc_7.sv   |  0
 .../testbench => testbench}/sdc/sd_defines.h  |  0
 .../testbench => testbench}/sdc/sd_top_tb.sv  |  0
 .../testbench => testbench}/sdc/wave.do       |  0
 .../testbench => testbench}/testbench-fp.sv   |  2 +-
 .../testbench-linux.sv                        |  0
 .../testbench => testbench}/testbench.sv      |  2 +-
 .../testbench_imperas.sv                      |  0
 .../testbench => testbench}/tests-fp.vh       |  0
 {pipelined/testbench => testbench}/tests.vh   | 14 +++++------
 tests/testgen/privileged/run.sh               |  4 ++--
 247 files changed, 35 insertions(+), 40 deletions(-)
 rename {pipelined/config => config}/buildroot/wally-config.vh (100%)
 rename {pipelined/config => config}/fpga/wally-config.vh (100%)
 rename {pipelined/config => config}/rv32e/wally-config.vh (100%)
 rename {pipelined/config => config}/rv32gc/wally-config.vh (100%)
 rename {pipelined/config => config}/rv32i/wally-config.vh (100%)
 rename {pipelined/config => config}/rv32imc/wally-config.vh (100%)
 rename {pipelined/config => config}/rv64fpquad/wally-config.vh (100%)
 rename {pipelined/config => config}/rv64gc/wally-config.vh (100%)
 rename {pipelined/config => config}/rv64i/wally-config.vh (100%)
 rename {pipelined/config => config}/shared/README (100%)
 rename {pipelined/config => config}/shared/wally-shared.vh (100%)
 rename {pipelined/regression => regression}/Makefile (100%)
 rename {pipelined/regression => regression}/buildrootBugFinder.py (100%)
 rename {pipelined/regression => regression}/fpga-wave.do (100%)
 rename {pipelined/regression => regression}/imperas.ic (100%)
 rename {pipelined/regression => regression}/lint-wally (100%)
 rename {pipelined/regression => regression}/linux-wave.do (100%)
 rename {pipelined/regression => regression}/make-tests.sh (88%)
 rename {pipelined/regression => regression}/makefile-memfile (100%)
 rename {pipelined/regression => regression}/regression-wally (100%)
 rename {pipelined/regression => regression}/run-imperasdv-tests.bash (100%)
 rename {pipelined/regression => regression}/sim-buildroot (100%)
 rename {pipelined/regression => regression}/sim-buildroot-batch (100%)
 rename {pipelined/regression => regression}/sim-imperas (100%)
 rename {pipelined/regression => regression}/sim-testfloat (100%)
 rename {pipelined/regression => regression}/sim-testfloat-batch (100%)
 rename {pipelined/regression => regression}/sim-wally (100%)
 rename {pipelined/regression => regression}/sim-wally-batch (100%)
 rename {pipelined/regression => regression}/slack-notifier/slack-notifier.py (100%)
 rename {pipelined/regression => regression}/test (100%)
 rename {pipelined/regression => regression}/testfloat.do (100%)
 rename {pipelined/regression => regression}/wally-pipelined-batch.do (100%)
 rename {pipelined/regression => regression}/wally-pipelined-imperas-no-idv.do (100%)
 rename {pipelined/regression => regression}/wally-pipelined-imperas.do (100%)
 rename {pipelined/regression => regression}/wally-pipelined.do (100%)
 rename {pipelined/regression => regression}/wave-all.do (100%)
 rename {pipelined/regression => regression}/wave-dos/ahb-muldiv.do (100%)
 rename {pipelined/regression => regression}/wave-dos/ahb-waves.do (100%)
 rename {pipelined/regression => regression}/wave-dos/cache-waves.do (100%)
 rename {pipelined/regression => regression}/wave-dos/default-waves.do (100%)
 rename {pipelined/regression => regression}/wave-dos/generic.do (100%)
 rename {pipelined/regression => regression}/wave-dos/linux-waves.do (100%)
 rename {pipelined/regression => regression}/wave-dos/peripheral-waves.do (100%)
 rename {pipelined/regression => regression}/wave-fpu.do (100%)
 rename {pipelined/regression => regression}/wave.do (100%)
 rename {pipelined/src => src}/cache/cache.sv (100%)
 rename {pipelined/src => src}/cache/cacheLRU.sv (100%)
 rename {pipelined/src => src}/cache/cachefsm.sv (100%)
 rename {pipelined/src => src}/cache/cacheway.sv (100%)
 rename {pipelined/src => src}/cache/subcachelineread.sv (100%)
 rename {pipelined/src => src}/ebu/ahbcacheinterface.sv (100%)
 rename {pipelined/src => src}/ebu/ahbinterface.sv (100%)
 rename {pipelined/src => src}/ebu/buscachefsm.sv (100%)
 rename {pipelined/src => src}/ebu/busfsm.sv (100%)
 rename {pipelined/src => src}/ebu/controllerinputstage.sv (100%)
 rename {pipelined/src => src}/ebu/ebu.sv (100%)
 rename {pipelined/src => src}/ebu/ebuarbfsm.sv (100%)
 rename {pipelined/src => src}/fpu/fclassify.sv (100%)
 rename {pipelined/src => src}/fpu/fcmp.sv (100%)
 rename {pipelined/src => src}/fpu/fctrl.sv (100%)
 rename {pipelined/src => src}/fpu/fcvt.sv (100%)
 rename {pipelined/src => src}/fpu/fdivsqrt/fdivsqrt.sv (100%)
 rename {pipelined/src => src}/fpu/fdivsqrt/fdivsqrtexpcalc.sv (100%)
 rename {pipelined/src => src}/fpu/fdivsqrt/fdivsqrtfgen2.sv (100%)
 rename {pipelined/src => src}/fpu/fdivsqrt/fdivsqrtfgen4.sv (100%)
 rename {pipelined/src => src}/fpu/fdivsqrt/fdivsqrtfsm.sv (100%)
 rename {pipelined/src => src}/fpu/fdivsqrt/fdivsqrtiter.sv (100%)
 rename {pipelined/src => src}/fpu/fdivsqrt/fdivsqrtpostproc.sv (100%)
 rename {pipelined/src => src}/fpu/fdivsqrt/fdivsqrtpreproc.sv (100%)
 rename {pipelined/src => src}/fpu/fdivsqrt/fdivsqrtqsel2.sv (100%)
 rename {pipelined/src => src}/fpu/fdivsqrt/fdivsqrtqsel4.sv (100%)
 rename {pipelined/src => src}/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv (100%)
 rename {pipelined/src => src}/fpu/fdivsqrt/fdivsqrtstage2.sv (100%)
 rename {pipelined/src => src}/fpu/fdivsqrt/fdivsqrtstage4.sv (100%)
 rename {pipelined/src => src}/fpu/fdivsqrt/fdivsqrtuotfc2.sv (100%)
 rename {pipelined/src => src}/fpu/fdivsqrt/fdivsqrtuotfc4.sv (100%)
 rename {pipelined/src => src}/fpu/fhazard.sv (100%)
 rename {pipelined/src => src}/fpu/fma/fma.sv (100%)
 rename {pipelined/src => src}/fpu/fma/fmaadd.sv (100%)
 rename {pipelined/src => src}/fpu/fma/fmaalign.sv (100%)
 rename {pipelined/src => src}/fpu/fma/fmaexpadd.sv (100%)
 rename {pipelined/src => src}/fpu/fma/fmalza.sv (100%)
 rename {pipelined/src => src}/fpu/fma/fmamult.sv (100%)
 rename {pipelined/src => src}/fpu/fma/fmasign.sv (100%)
 rename {pipelined/src => src}/fpu/fpu.sv (100%)
 rename {pipelined/src => src}/fpu/fregfile.sv (100%)
 rename {pipelined/src => src}/fpu/fsgninj.sv (100%)
 rename {pipelined/src => src}/fpu/postproc/cvtshiftcalc.sv (100%)
 rename {pipelined/src => src}/fpu/postproc/divshiftcalc.sv (100%)
 rename {pipelined/src => src}/fpu/postproc/flags.sv (100%)
 rename {pipelined/src => src}/fpu/postproc/fmashiftcalc.sv (100%)
 rename {pipelined/src => src}/fpu/postproc/negateintres.sv (100%)
 rename {pipelined/src => src}/fpu/postproc/normshift.sv (100%)
 rename {pipelined/src => src}/fpu/postproc/postprocess.sv (100%)
 rename {pipelined/src => src}/fpu/postproc/resultsign.sv (100%)
 rename {pipelined/src => src}/fpu/postproc/round.sv (100%)
 rename {pipelined/src => src}/fpu/postproc/roundsign.sv (100%)
 rename {pipelined/src => src}/fpu/postproc/shiftcorrection.sv (100%)
 rename {pipelined/src => src}/fpu/postproc/specialcase.sv (100%)
 rename {pipelined/src => src}/fpu/unpack.sv (100%)
 rename {pipelined/src => src}/fpu/unpackinput.sv (100%)
 rename {pipelined/src => src}/generic/adder.sv (100%)
 rename {pipelined/src => src}/generic/aplusbeq0.sv (100%)
 rename {pipelined/src => src}/generic/arrs.sv (100%)
 rename {pipelined/src => src}/generic/binencoder.sv (100%)
 rename {pipelined/src => src}/generic/clockgater.sv (100%)
 rename {pipelined/src => src}/generic/counter.sv (100%)
 rename {pipelined/src => src}/generic/csa.sv (100%)
 rename {pipelined/src => src}/generic/decoder.sv (100%)
 rename {pipelined/src => src}/generic/flop/flop.sv (100%)
 rename {pipelined/src => src}/generic/flop/flopen.sv (100%)
 rename {pipelined/src => src}/generic/flop/flopenl.sv (100%)
 rename {pipelined/src => src}/generic/flop/flopenr.sv (100%)
 rename {pipelined/src => src}/generic/flop/flopenrc.sv (100%)
 rename {pipelined/src => src}/generic/flop/flopens.sv (100%)
 rename {pipelined/src => src}/generic/flop/flopr.sv (100%)
 rename {pipelined/src => src}/generic/flop/floprc.sv (100%)
 rename {pipelined/src => src}/generic/flop/synchronizer.sv (100%)
 rename {pipelined/src => src}/generic/lzc.sv (100%)
 rename {pipelined/src => src}/generic/mem/ram1p1rwbe.sv (100%)
 rename {pipelined/src => src}/generic/mem/ram1p1rwbe_64x128.sv (100%)
 rename {pipelined/src => src}/generic/mem/ram1p1rwbe_64x44.sv (100%)
 rename {pipelined/src => src}/generic/mem/ram2p1r1wbe.sv (100%)
 rename {pipelined/src => src}/generic/mem/ram2p1r1wbe_1024x68.sv (100%)
 rename {pipelined/src => src}/generic/mem/ram2p1r1wbe_64x32.sv (100%)
 rename {pipelined/src => src}/generic/mem/rom1p1r.sv (100%)
 rename {pipelined/src => src}/generic/mem/rom1p1r_128x32.sv (100%)
 rename {pipelined/src => src}/generic/mem/rom1p1r_128x64.sv (100%)
 rename {pipelined/src => src}/generic/mux.sv (100%)
 rename {pipelined/src => src}/generic/neg.sv (100%)
 rename {pipelined/src => src}/generic/onehotdecoder.sv (100%)
 rename {pipelined/src => src}/generic/or_rows.sv (100%)
 rename {pipelined/src => src}/generic/priorityonehot.sv (100%)
 rename {pipelined/src => src}/generic/prioritythermometer.sv (100%)
 rename {pipelined/src => src}/hazard/hazard.sv (100%)
 rename {pipelined/src => src}/ieu/alu.sv (100%)
 rename {pipelined/src => src}/ieu/comparator.sv (100%)
 rename {pipelined/src => src}/ieu/controller.sv (100%)
 rename {pipelined/src => src}/ieu/datapath.sv (100%)
 rename {pipelined/src => src}/ieu/extend.sv (100%)
 rename {pipelined/src => src}/ieu/forward.sv (100%)
 rename {pipelined/src => src}/ieu/ieu.sv (100%)
 rename {pipelined/src => src}/ieu/regfile.sv (100%)
 rename {pipelined/src => src}/ieu/shifter.sv (100%)
 rename {pipelined/src => src}/ifu/CodeAligner.py (100%)
 rename {pipelined/src => src}/ifu/bpred/RASPredictor.sv (100%)
 rename {pipelined/src => src}/ifu/bpred/bpred.sv (100%)
 rename {pipelined/src => src}/ifu/bpred/btb.sv (100%)
 rename {pipelined/src => src}/ifu/bpred/foldedgshare.sv (100%)
 rename {pipelined/src => src}/ifu/bpred/globalhistory.sv (100%)
 rename {pipelined/src => src}/ifu/bpred/gshare.sv (100%)
 rename {pipelined/src => src}/ifu/bpred/localHistoryPredictor.sv (100%)
 rename {pipelined/src => src}/ifu/bpred/optgshare.sv (100%)
 rename {pipelined/src => src}/ifu/bpred/satCounter2.sv (100%)
 rename {pipelined/src => src}/ifu/bpred/speculativeglobalhistory.sv (100%)
 rename {pipelined/src => src}/ifu/bpred/speculativegshare.sv (100%)
 rename {pipelined/src => src}/ifu/bpred/twoBitPredictor.sv (100%)
 rename {pipelined/src => src}/ifu/decompress.sv (100%)
 rename {pipelined/src => src}/ifu/ifu.sv (100%)
 rename {pipelined/src => src}/ifu/irom.sv (100%)
 rename {pipelined/src => src}/ifu/spill.sv (100%)
 rename {pipelined/src => src}/lsu/amoalu.sv (100%)
 rename {pipelined/src => src}/lsu/atomic.sv (100%)
 rename {pipelined/src => src}/lsu/dtim.sv (100%)
 rename {pipelined/src => src}/lsu/endianswap.sv (100%)
 rename {pipelined/src => src}/lsu/lrsc.sv (100%)
 rename {pipelined/src => src}/lsu/lsu.sv (100%)
 rename {pipelined/src => src}/lsu/subwordread.sv (100%)
 rename {pipelined/src => src}/lsu/subwordwrite.sv (100%)
 rename {pipelined/src => src}/lsu/swbytemask.sv (100%)
 rename {pipelined/src => src}/mdu/intdivrestoring.sv (100%)
 rename {pipelined/src => src}/mdu/intdivrestoringstep.sv (100%)
 rename {pipelined/src => src}/mdu/mdu.sv (100%)
 rename {pipelined/src => src}/mdu/mul.sv (100%)
 rename {pipelined/src => src}/mmu/adrdec.sv (100%)
 rename {pipelined/src => src}/mmu/adrdecs.sv (100%)
 rename {pipelined/src => src}/mmu/hptw.sv (100%)
 rename {pipelined/src => src}/mmu/mmu.sv (100%)
 rename {pipelined/src => src}/mmu/pmachecker.sv (100%)
 rename {pipelined/src => src}/mmu/pmpadrdec.sv (100%)
 rename {pipelined/src => src}/mmu/pmpchecker.sv (100%)
 rename {pipelined/src => src}/mmu/tlb.sv (100%)
 rename {pipelined/src => src}/mmu/tlbcam.sv (100%)
 rename {pipelined/src => src}/mmu/tlbcamline.sv (100%)
 rename {pipelined/src => src}/mmu/tlbcontrol.sv (100%)
 rename {pipelined/src => src}/mmu/tlblru.sv (100%)
 rename {pipelined/src => src}/mmu/tlbmixer.sv (100%)
 rename {pipelined/src => src}/mmu/tlbram.sv (100%)
 rename {pipelined/src => src}/mmu/tlbramline.sv (100%)
 rename {pipelined/src => src}/mmu/vm64check.sv (100%)
 rename {pipelined/src => src}/privileged/csr.sv (100%)
 rename {pipelined/src => src}/privileged/csrc.sv (100%)
 rename {pipelined/src => src}/privileged/csri.sv (100%)
 rename {pipelined/src => src}/privileged/csrm.sv (100%)
 rename {pipelined/src => src}/privileged/csrs.sv (100%)
 rename {pipelined/src => src}/privileged/csrsr.sv (100%)
 rename {pipelined/src => src}/privileged/csru.sv (100%)
 rename {pipelined/src => src}/privileged/privdec.sv (100%)
 rename {pipelined/src => src}/privileged/privileged.sv (100%)
 rename {pipelined/src => src}/privileged/privmode.sv (100%)
 rename {pipelined/src => src}/privileged/privpiperegs.sv (100%)
 rename {pipelined/src => src}/privileged/trap.sv (100%)
 rename {pipelined/src => src}/uncore/ahbapbbridge.sv (100%)
 rename {pipelined/src => src}/uncore/clint_apb.sv (100%)
 rename {pipelined/src => src}/uncore/gpio_apb.sv (100%)
 rename {pipelined/src => src}/uncore/plic_apb.sv (100%)
 rename {pipelined/src => src}/uncore/ram_ahb.sv (100%)
 rename {pipelined/src => src}/uncore/rom_ahb.sv (100%)
 rename {pipelined/src => src}/uncore/uartPC16550D.sv (100%)
 rename {pipelined/src => src}/uncore/uart_apb.sv (100%)
 rename {pipelined/src => src}/uncore/uncore.sv (100%)
 rename {pipelined/src => src}/wally/cvw.sv (100%)
 rename {pipelined/src => src}/wally/wallypipelinedcore.sv (100%)
 rename {pipelined/src => src}/wally/wallypipelinedsoc.sv (100%)
 rename {pipelined/testbench => testbench}/common/functionName.sv (100%)
 rename {pipelined/testbench => testbench}/common/instrNameDecTB.sv (100%)
 rename {pipelined/testbench => testbench}/common/instrTrackerTB.sv (100%)
 rename {pipelined/testbench => testbench}/common/wallyTracer.sv (100%)
 rename {pipelined/testbench => testbench}/fp/case.sh (100%)
 rename {pipelined/testbench => testbench}/sdc/ram2sdLoad.py (100%)
 rename {pipelined/testbench => testbench}/sdc/ramdisk2.hex (100%)
 rename {pipelined/testbench => testbench}/sdc/run_tb.do (100%)
 rename {pipelined/testbench => testbench}/sdc/sdModel.sv (100%)
 rename {pipelined/testbench => testbench}/sdc/sd_crc_16.sv (100%)
 rename {pipelined/testbench => testbench}/sdc/sd_crc_7.sv (100%)
 rename {pipelined/testbench => testbench}/sdc/sd_defines.h (100%)
 rename {pipelined/testbench => testbench}/sdc/sd_top_tb.sv (100%)
 rename {pipelined/testbench => testbench}/sdc/wave.do (100%)
 rename {pipelined/testbench => testbench}/testbench-fp.sv (99%)
 rename {pipelined/testbench => testbench}/testbench-linux.sv (100%)
 rename {pipelined/testbench => testbench}/testbench.sv (99%)
 rename {pipelined/testbench => testbench}/testbench_imperas.sv (100%)
 rename {pipelined/testbench => testbench}/tests-fp.vh (100%)
 rename {pipelined/testbench => testbench}/tests.vh (99%)

diff --git a/.gitignore b/.gitignore
index 1e651e68e..b389dd1dd 100644
--- a/.gitignore
+++ b/.gitignore
@@ -15,7 +15,7 @@ benchmarks/embench/wally*.json
 #vsim work files to ignore
 transcript
 vsim.wlf
-pipelined/wlft*
+wlft*
 wlft*
 /imperas-riscv-tests/FunctionRadix_32.addr
 /imperas-riscv-tests/FunctionRadix_64.addr
@@ -42,8 +42,8 @@ tests/linux-testgen/buildroot-image-output
 tests/linux-testgen/buildroot-config-src/main.config.old
 tests/linux-testgen/buildroot-config-src/linux.config.old
 tests/linux-testgen/buildroot-config-src/busybox.config.old
-pipelined/regression/slack-notifier/slack-webhook-url.txt
-pipelined/regression/logs
+regression/slack-notifier/slack-webhook-url.txt
+regression/logs
 fpga/generator/IP
 fpga/generator/vivado.*
 fpga/generator/.Xil/*
@@ -59,7 +59,7 @@ examples/C/sum/sum
 examples/C/fir/fir
 examples/fp/softfloat_demo/softfloat_demo
 examples/fp/fpcalc/fpcalc
-pipelined/src/fma/fma16_testgen
+src/fma/fma16_testgen
 linux/devicetree/debug/*
 !linux/devicetree/debug/dump-dts.sh
 linux/testvector-generation/genCheckpoint.gdb
@@ -79,29 +79,24 @@ synthDC/ppa/plots
 synthDC/wallyplots/
 synthDC/runArchive
 synthDC/hdl
-/pipelined/regression/power.saif
+regression/power.saif
 tests/fp/vectors/*.tv
 synthDC/Summary.csv
-pipelined/srt/exptestgen
-pipelined/srt/testgen
-pipelined/srt/qslc_r4a2
-pipelined/srt/qslc_r4a2.sv
-pipelined/srt/testvectors
-pipelined/regression/wkdir
+regression/wkdir
 tests/custom/work
 tests/custom/*/*/*.list
 tests/custom/*/*/*.elf
 tests/custom/*/*/*.map
 tests/custom/*/*/*.memfile
 tests/custom/crt0/*.a
-/pipelined/regression/sd_model.log
+regression/sd_model.log
 fpga/src/sdc/*
 fpga/src/sdc.tar.gz
 fpga/src/CopiedFiles_do_not_add_to_repo/*
-/pipelined/regression/branch.log
+regression/branch.log
 /fpga/generator/sim/imp-funcsim.v
 /fpga/generator/sim/imp-timesim.sdf
 /fpga/generator/sim/imp-timesim.v
 /fpga/generator/sim/syn-funcsim.v
 external
-pipelined/regression/results
+regression/results
diff --git a/Install b/Install
index 7e509197d..46f4d78ec 100644
--- a/Install
+++ b/Install
@@ -328,6 +328,6 @@ source ./setup.sh        # may require some modification for your system. Always
 
   cd <to location of repo clone>
   make
-  cd pipelined/regression
+  cd regression
   ./regression-wally       #(depends on having Questa installed)
 
diff --git a/Makefile b/Makefile
index b3a054e49..24ba57e57 100644
--- a/Makefile
+++ b/Makefile
@@ -15,8 +15,8 @@ install:
 	##ln -s ${RISCV}/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
 
 regression:
-	make -C pipelined/regression
+	make -C regression
 
 clean:
-	make clean -C pipelined/regression
+	make clean -C regression
 
diff --git a/README.md b/README.md
index 12d7fe1f6..824c7c176 100644
--- a/README.md
+++ b/README.md
@@ -53,7 +53,7 @@ Edit setup.sh and change the following lines to point to the path and license se
 
 Run a regression simulation with Questa to prove everything is installed.
 
-	$ cd pipelined/regression
+	$ cd regression
 	$ ./regression-wally       (depends on having Questa installed)
 
 # Toolchain Installation (Sys Admin)
diff --git a/benchmarks/coremark/Makefile b/benchmarks/coremark/Makefile
index 8c467d581..b8235ea94 100644
--- a/benchmarks/coremark/Makefile
+++ b/benchmarks/coremark/Makefile
@@ -21,7 +21,7 @@ PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \
 all: $(work_dir)/coremark.bare.riscv.elf.memfile
 
 run:
-	(cd ../../pipelined/regression && (time vsim -c -do "do wally-pipelined-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log))
+	(cd ../../regression && (time vsim -c -do "do wally-pipelined-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log))
 	cd ../../benchmarks/coremark/
 #	KMG: added post processing script to give out branch miss proportion along with other stats to the coremark test
 	python3 coremark-postprocess.py
diff --git a/benchmarks/embench/Makefile b/benchmarks/embench/Makefile
index 21c30cf6e..b5030d119 100644
--- a/benchmarks/embench/Makefile
+++ b/benchmarks/embench/Makefile
@@ -34,7 +34,7 @@ sim: modelsim_build_memfile modelsim_run speed
 
 # launches modelsim to simulate tests on wally
 modelsim_run:
-	(cd ../../pipelined/regression/ && vsim -c -do "do wally-pipelined-batch.do rv32gc embench")
+	(cd ../../regression/ && vsim -c -do "do wally-pipelined-batch.do rv32gc embench")
 	cd ../../benchmarks/embench/
 
 # builds the objdump based on the compiled c elf files
diff --git a/pipelined/config/buildroot/wally-config.vh b/config/buildroot/wally-config.vh
similarity index 100%
rename from pipelined/config/buildroot/wally-config.vh
rename to config/buildroot/wally-config.vh
diff --git a/pipelined/config/fpga/wally-config.vh b/config/fpga/wally-config.vh
similarity index 100%
rename from pipelined/config/fpga/wally-config.vh
rename to config/fpga/wally-config.vh
diff --git a/pipelined/config/rv32e/wally-config.vh b/config/rv32e/wally-config.vh
similarity index 100%
rename from pipelined/config/rv32e/wally-config.vh
rename to config/rv32e/wally-config.vh
diff --git a/pipelined/config/rv32gc/wally-config.vh b/config/rv32gc/wally-config.vh
similarity index 100%
rename from pipelined/config/rv32gc/wally-config.vh
rename to config/rv32gc/wally-config.vh
diff --git a/pipelined/config/rv32i/wally-config.vh b/config/rv32i/wally-config.vh
similarity index 100%
rename from pipelined/config/rv32i/wally-config.vh
rename to config/rv32i/wally-config.vh
diff --git a/pipelined/config/rv32imc/wally-config.vh b/config/rv32imc/wally-config.vh
similarity index 100%
rename from pipelined/config/rv32imc/wally-config.vh
rename to config/rv32imc/wally-config.vh
diff --git a/pipelined/config/rv64fpquad/wally-config.vh b/config/rv64fpquad/wally-config.vh
similarity index 100%
rename from pipelined/config/rv64fpquad/wally-config.vh
rename to config/rv64fpquad/wally-config.vh
diff --git a/pipelined/config/rv64gc/wally-config.vh b/config/rv64gc/wally-config.vh
similarity index 100%
rename from pipelined/config/rv64gc/wally-config.vh
rename to config/rv64gc/wally-config.vh
diff --git a/pipelined/config/rv64i/wally-config.vh b/config/rv64i/wally-config.vh
similarity index 100%
rename from pipelined/config/rv64i/wally-config.vh
rename to config/rv64i/wally-config.vh
diff --git a/pipelined/config/shared/README b/config/shared/README
similarity index 100%
rename from pipelined/config/shared/README
rename to config/shared/README
diff --git a/pipelined/config/shared/wally-shared.vh b/config/shared/wally-shared.vh
similarity index 100%
rename from pipelined/config/shared/wally-shared.vh
rename to config/shared/wally-shared.vh
diff --git a/fpga/README.md b/fpga/README.md
index 3f9853c72..dfa27479e 100644
--- a/fpga/README.md
+++ b/fpga/README.md
@@ -16,7 +16,7 @@ a large number of debuging signals.
 
 * Programming the flash card
 You'll need to write the linux image to the flash card.  Use the convert2bin.py 
-script in pipelined/linux-testgen/linux-testvectors/ to convert the ram.txt
+script in linux-testgen/linux-testvectors/ [*** moved?] to convert the ram.txt 
 file from QEMU's preload to generate the binary.  Then to copy
  sudo dd if=ram.bin of=<path to flash card>.
 
diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile
index 3ab35b34b..1d07305fb 100644
--- a/fpga/generator/Makefile
+++ b/fpga/generator/Makefile
@@ -27,7 +27,7 @@ SDC:
 
 PreProcessFiles:
 	rm -rf ../src/CopiedFiles_do_not_add_to_repo/
-	cp -r ../../pipelined/src/ ../src/CopiedFiles_do_not_add_to_repo/
+	cp -r ../../src/ ../src/CopiedFiles_do_not_add_to_repo/
 	./insert_debug_comment.sh
 
 $(dst)/%.log: %.tcl
diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl
index 45444d577..c93abed78 100644
--- a/fpga/generator/wally.tcl
+++ b/fpga/generator/wally.tcl
@@ -19,7 +19,7 @@ read_verilog -sv [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../s
 read_verilog  {../src/fpgaTop.v}
 read_verilog -sv  [glob -type f ../src/sdc/*.sv]
 
-set_property include_dirs {../../pipelined/config/fpga ../../pipelined/config/shared} [current_fileset]
+set_property include_dirs {../../config/fpga ../../config/shared} [current_fileset]
 
 
 add_files -fileset constrs_1 -norecurse ../constraints/constraints-$boardSubName.xdc
diff --git a/pipelined/regression/Makefile b/regression/Makefile
similarity index 100%
rename from pipelined/regression/Makefile
rename to regression/Makefile
diff --git a/pipelined/regression/buildrootBugFinder.py b/regression/buildrootBugFinder.py
similarity index 100%
rename from pipelined/regression/buildrootBugFinder.py
rename to regression/buildrootBugFinder.py
diff --git a/pipelined/regression/fpga-wave.do b/regression/fpga-wave.do
similarity index 100%
rename from pipelined/regression/fpga-wave.do
rename to regression/fpga-wave.do
diff --git a/pipelined/regression/imperas.ic b/regression/imperas.ic
similarity index 100%
rename from pipelined/regression/imperas.ic
rename to regression/imperas.ic
diff --git a/pipelined/regression/lint-wally b/regression/lint-wally
similarity index 100%
rename from pipelined/regression/lint-wally
rename to regression/lint-wally
diff --git a/pipelined/regression/linux-wave.do b/regression/linux-wave.do
similarity index 100%
rename from pipelined/regression/linux-wave.do
rename to regression/linux-wave.do
diff --git a/pipelined/regression/make-tests.sh b/regression/make-tests.sh
similarity index 88%
rename from pipelined/regression/make-tests.sh
rename to regression/make-tests.sh
index fe4555ff2..de7765086 100755
--- a/pipelined/regression/make-tests.sh
+++ b/regression/make-tests.sh
@@ -13,4 +13,4 @@ make
 # exe2memfile.pl work/*/*/*.elf
 # cd ../linux-testgen/linux-testvectors
 # ./tvLinker.sh
-# cd ../../../pipelined/regression
+# cd ../../../regression
diff --git a/pipelined/regression/makefile-memfile b/regression/makefile-memfile
similarity index 100%
rename from pipelined/regression/makefile-memfile
rename to regression/makefile-memfile
diff --git a/pipelined/regression/regression-wally b/regression/regression-wally
similarity index 100%
rename from pipelined/regression/regression-wally
rename to regression/regression-wally
diff --git a/pipelined/regression/run-imperasdv-tests.bash b/regression/run-imperasdv-tests.bash
similarity index 100%
rename from pipelined/regression/run-imperasdv-tests.bash
rename to regression/run-imperasdv-tests.bash
diff --git a/pipelined/regression/sim-buildroot b/regression/sim-buildroot
similarity index 100%
rename from pipelined/regression/sim-buildroot
rename to regression/sim-buildroot
diff --git a/pipelined/regression/sim-buildroot-batch b/regression/sim-buildroot-batch
similarity index 100%
rename from pipelined/regression/sim-buildroot-batch
rename to regression/sim-buildroot-batch
diff --git a/pipelined/regression/sim-imperas b/regression/sim-imperas
similarity index 100%
rename from pipelined/regression/sim-imperas
rename to regression/sim-imperas
diff --git a/pipelined/regression/sim-testfloat b/regression/sim-testfloat
similarity index 100%
rename from pipelined/regression/sim-testfloat
rename to regression/sim-testfloat
diff --git a/pipelined/regression/sim-testfloat-batch b/regression/sim-testfloat-batch
similarity index 100%
rename from pipelined/regression/sim-testfloat-batch
rename to regression/sim-testfloat-batch
diff --git a/pipelined/regression/sim-wally b/regression/sim-wally
similarity index 100%
rename from pipelined/regression/sim-wally
rename to regression/sim-wally
diff --git a/pipelined/regression/sim-wally-batch b/regression/sim-wally-batch
similarity index 100%
rename from pipelined/regression/sim-wally-batch
rename to regression/sim-wally-batch
diff --git a/pipelined/regression/slack-notifier/slack-notifier.py b/regression/slack-notifier/slack-notifier.py
similarity index 100%
rename from pipelined/regression/slack-notifier/slack-notifier.py
rename to regression/slack-notifier/slack-notifier.py
diff --git a/pipelined/regression/test b/regression/test
similarity index 100%
rename from pipelined/regression/test
rename to regression/test
diff --git a/pipelined/regression/testfloat.do b/regression/testfloat.do
similarity index 100%
rename from pipelined/regression/testfloat.do
rename to regression/testfloat.do
diff --git a/pipelined/regression/wally-pipelined-batch.do b/regression/wally-pipelined-batch.do
similarity index 100%
rename from pipelined/regression/wally-pipelined-batch.do
rename to regression/wally-pipelined-batch.do
diff --git a/pipelined/regression/wally-pipelined-imperas-no-idv.do b/regression/wally-pipelined-imperas-no-idv.do
similarity index 100%
rename from pipelined/regression/wally-pipelined-imperas-no-idv.do
rename to regression/wally-pipelined-imperas-no-idv.do
diff --git a/pipelined/regression/wally-pipelined-imperas.do b/regression/wally-pipelined-imperas.do
similarity index 100%
rename from pipelined/regression/wally-pipelined-imperas.do
rename to regression/wally-pipelined-imperas.do
diff --git a/pipelined/regression/wally-pipelined.do b/regression/wally-pipelined.do
similarity index 100%
rename from pipelined/regression/wally-pipelined.do
rename to regression/wally-pipelined.do
diff --git a/pipelined/regression/wave-all.do b/regression/wave-all.do
similarity index 100%
rename from pipelined/regression/wave-all.do
rename to regression/wave-all.do
diff --git a/pipelined/regression/wave-dos/ahb-muldiv.do b/regression/wave-dos/ahb-muldiv.do
similarity index 100%
rename from pipelined/regression/wave-dos/ahb-muldiv.do
rename to regression/wave-dos/ahb-muldiv.do
diff --git a/pipelined/regression/wave-dos/ahb-waves.do b/regression/wave-dos/ahb-waves.do
similarity index 100%
rename from pipelined/regression/wave-dos/ahb-waves.do
rename to regression/wave-dos/ahb-waves.do
diff --git a/pipelined/regression/wave-dos/cache-waves.do b/regression/wave-dos/cache-waves.do
similarity index 100%
rename from pipelined/regression/wave-dos/cache-waves.do
rename to regression/wave-dos/cache-waves.do
diff --git a/pipelined/regression/wave-dos/default-waves.do b/regression/wave-dos/default-waves.do
similarity index 100%
rename from pipelined/regression/wave-dos/default-waves.do
rename to regression/wave-dos/default-waves.do
diff --git a/pipelined/regression/wave-dos/generic.do b/regression/wave-dos/generic.do
similarity index 100%
rename from pipelined/regression/wave-dos/generic.do
rename to regression/wave-dos/generic.do
diff --git a/pipelined/regression/wave-dos/linux-waves.do b/regression/wave-dos/linux-waves.do
similarity index 100%
rename from pipelined/regression/wave-dos/linux-waves.do
rename to regression/wave-dos/linux-waves.do
diff --git a/pipelined/regression/wave-dos/peripheral-waves.do b/regression/wave-dos/peripheral-waves.do
similarity index 100%
rename from pipelined/regression/wave-dos/peripheral-waves.do
rename to regression/wave-dos/peripheral-waves.do
diff --git a/pipelined/regression/wave-fpu.do b/regression/wave-fpu.do
similarity index 100%
rename from pipelined/regression/wave-fpu.do
rename to regression/wave-fpu.do
diff --git a/pipelined/regression/wave.do b/regression/wave.do
similarity index 100%
rename from pipelined/regression/wave.do
rename to regression/wave.do
diff --git a/setup.imperas.sh b/setup.imperas.sh
index e3ac447bf..4e30fb07f 100644
--- a/setup.imperas.sh
+++ b/setup.imperas.sh
@@ -31,7 +31,7 @@ export IMPERAS_PERSONALITY=CPUMAN_DV_ASYNC
 # setup QUESTA (Imperas only command, YMMV)
 svsetup -questa
 
-pushd pipelined/regression
+pushd regression
     # With IDV
     IMPERAS_TOOLS=$(pwd)/imperas.ic \
         OTHERFLAGS="+TRACE2LOG_ENABLE=1 VERBOSE=1" \
diff --git a/pipelined/src/cache/cache.sv b/src/cache/cache.sv
similarity index 100%
rename from pipelined/src/cache/cache.sv
rename to src/cache/cache.sv
diff --git a/pipelined/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv
similarity index 100%
rename from pipelined/src/cache/cacheLRU.sv
rename to src/cache/cacheLRU.sv
diff --git a/pipelined/src/cache/cachefsm.sv b/src/cache/cachefsm.sv
similarity index 100%
rename from pipelined/src/cache/cachefsm.sv
rename to src/cache/cachefsm.sv
diff --git a/pipelined/src/cache/cacheway.sv b/src/cache/cacheway.sv
similarity index 100%
rename from pipelined/src/cache/cacheway.sv
rename to src/cache/cacheway.sv
diff --git a/pipelined/src/cache/subcachelineread.sv b/src/cache/subcachelineread.sv
similarity index 100%
rename from pipelined/src/cache/subcachelineread.sv
rename to src/cache/subcachelineread.sv
diff --git a/pipelined/src/ebu/ahbcacheinterface.sv b/src/ebu/ahbcacheinterface.sv
similarity index 100%
rename from pipelined/src/ebu/ahbcacheinterface.sv
rename to src/ebu/ahbcacheinterface.sv
diff --git a/pipelined/src/ebu/ahbinterface.sv b/src/ebu/ahbinterface.sv
similarity index 100%
rename from pipelined/src/ebu/ahbinterface.sv
rename to src/ebu/ahbinterface.sv
diff --git a/pipelined/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv
similarity index 100%
rename from pipelined/src/ebu/buscachefsm.sv
rename to src/ebu/buscachefsm.sv
diff --git a/pipelined/src/ebu/busfsm.sv b/src/ebu/busfsm.sv
similarity index 100%
rename from pipelined/src/ebu/busfsm.sv
rename to src/ebu/busfsm.sv
diff --git a/pipelined/src/ebu/controllerinputstage.sv b/src/ebu/controllerinputstage.sv
similarity index 100%
rename from pipelined/src/ebu/controllerinputstage.sv
rename to src/ebu/controllerinputstage.sv
diff --git a/pipelined/src/ebu/ebu.sv b/src/ebu/ebu.sv
similarity index 100%
rename from pipelined/src/ebu/ebu.sv
rename to src/ebu/ebu.sv
diff --git a/pipelined/src/ebu/ebuarbfsm.sv b/src/ebu/ebuarbfsm.sv
similarity index 100%
rename from pipelined/src/ebu/ebuarbfsm.sv
rename to src/ebu/ebuarbfsm.sv
diff --git a/pipelined/src/fpu/fclassify.sv b/src/fpu/fclassify.sv
similarity index 100%
rename from pipelined/src/fpu/fclassify.sv
rename to src/fpu/fclassify.sv
diff --git a/pipelined/src/fpu/fcmp.sv b/src/fpu/fcmp.sv
similarity index 100%
rename from pipelined/src/fpu/fcmp.sv
rename to src/fpu/fcmp.sv
diff --git a/pipelined/src/fpu/fctrl.sv b/src/fpu/fctrl.sv
similarity index 100%
rename from pipelined/src/fpu/fctrl.sv
rename to src/fpu/fctrl.sv
diff --git a/pipelined/src/fpu/fcvt.sv b/src/fpu/fcvt.sv
similarity index 100%
rename from pipelined/src/fpu/fcvt.sv
rename to src/fpu/fcvt.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/src/fpu/fdivsqrt/fdivsqrt.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
rename to src/fpu/fdivsqrt/fdivsqrt.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv
rename to src/fpu/fdivsqrt/fdivsqrtexpcalc.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv b/src/fpu/fdivsqrt/fdivsqrtfgen2.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv
rename to src/fpu/fdivsqrt/fdivsqrtfgen2.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv b/src/fpu/fdivsqrt/fdivsqrtfgen4.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtfgen4.sv
rename to src/fpu/fdivsqrt/fdivsqrtfgen4.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/src/fpu/fdivsqrt/fdivsqrtfsm.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv
rename to src/fpu/fdivsqrt/fdivsqrtfsm.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv b/src/fpu/fdivsqrt/fdivsqrtiter.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtiter.sv
rename to src/fpu/fdivsqrt/fdivsqrtiter.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
rename to src/fpu/fdivsqrt/fdivsqrtpostproc.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
rename to src/fpu/fdivsqrt/fdivsqrtpreproc.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv b/src/fpu/fdivsqrt/fdivsqrtqsel2.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv
rename to src/fpu/fdivsqrt/fdivsqrtqsel2.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv b/src/fpu/fdivsqrt/fdivsqrtqsel4.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4.sv
rename to src/fpu/fdivsqrt/fdivsqrtqsel4.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv b/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv
rename to src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv b/src/fpu/fdivsqrt/fdivsqrtstage2.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv
rename to src/fpu/fdivsqrt/fdivsqrtstage2.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv b/src/fpu/fdivsqrt/fdivsqrtstage4.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtstage4.sv
rename to src/fpu/fdivsqrt/fdivsqrtstage4.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv b/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv
rename to src/fpu/fdivsqrt/fdivsqrtuotfc2.sv
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv b/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv
similarity index 100%
rename from pipelined/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv
rename to src/fpu/fdivsqrt/fdivsqrtuotfc4.sv
diff --git a/pipelined/src/fpu/fhazard.sv b/src/fpu/fhazard.sv
similarity index 100%
rename from pipelined/src/fpu/fhazard.sv
rename to src/fpu/fhazard.sv
diff --git a/pipelined/src/fpu/fma/fma.sv b/src/fpu/fma/fma.sv
similarity index 100%
rename from pipelined/src/fpu/fma/fma.sv
rename to src/fpu/fma/fma.sv
diff --git a/pipelined/src/fpu/fma/fmaadd.sv b/src/fpu/fma/fmaadd.sv
similarity index 100%
rename from pipelined/src/fpu/fma/fmaadd.sv
rename to src/fpu/fma/fmaadd.sv
diff --git a/pipelined/src/fpu/fma/fmaalign.sv b/src/fpu/fma/fmaalign.sv
similarity index 100%
rename from pipelined/src/fpu/fma/fmaalign.sv
rename to src/fpu/fma/fmaalign.sv
diff --git a/pipelined/src/fpu/fma/fmaexpadd.sv b/src/fpu/fma/fmaexpadd.sv
similarity index 100%
rename from pipelined/src/fpu/fma/fmaexpadd.sv
rename to src/fpu/fma/fmaexpadd.sv
diff --git a/pipelined/src/fpu/fma/fmalza.sv b/src/fpu/fma/fmalza.sv
similarity index 100%
rename from pipelined/src/fpu/fma/fmalza.sv
rename to src/fpu/fma/fmalza.sv
diff --git a/pipelined/src/fpu/fma/fmamult.sv b/src/fpu/fma/fmamult.sv
similarity index 100%
rename from pipelined/src/fpu/fma/fmamult.sv
rename to src/fpu/fma/fmamult.sv
diff --git a/pipelined/src/fpu/fma/fmasign.sv b/src/fpu/fma/fmasign.sv
similarity index 100%
rename from pipelined/src/fpu/fma/fmasign.sv
rename to src/fpu/fma/fmasign.sv
diff --git a/pipelined/src/fpu/fpu.sv b/src/fpu/fpu.sv
similarity index 100%
rename from pipelined/src/fpu/fpu.sv
rename to src/fpu/fpu.sv
diff --git a/pipelined/src/fpu/fregfile.sv b/src/fpu/fregfile.sv
similarity index 100%
rename from pipelined/src/fpu/fregfile.sv
rename to src/fpu/fregfile.sv
diff --git a/pipelined/src/fpu/fsgninj.sv b/src/fpu/fsgninj.sv
similarity index 100%
rename from pipelined/src/fpu/fsgninj.sv
rename to src/fpu/fsgninj.sv
diff --git a/pipelined/src/fpu/postproc/cvtshiftcalc.sv b/src/fpu/postproc/cvtshiftcalc.sv
similarity index 100%
rename from pipelined/src/fpu/postproc/cvtshiftcalc.sv
rename to src/fpu/postproc/cvtshiftcalc.sv
diff --git a/pipelined/src/fpu/postproc/divshiftcalc.sv b/src/fpu/postproc/divshiftcalc.sv
similarity index 100%
rename from pipelined/src/fpu/postproc/divshiftcalc.sv
rename to src/fpu/postproc/divshiftcalc.sv
diff --git a/pipelined/src/fpu/postproc/flags.sv b/src/fpu/postproc/flags.sv
similarity index 100%
rename from pipelined/src/fpu/postproc/flags.sv
rename to src/fpu/postproc/flags.sv
diff --git a/pipelined/src/fpu/postproc/fmashiftcalc.sv b/src/fpu/postproc/fmashiftcalc.sv
similarity index 100%
rename from pipelined/src/fpu/postproc/fmashiftcalc.sv
rename to src/fpu/postproc/fmashiftcalc.sv
diff --git a/pipelined/src/fpu/postproc/negateintres.sv b/src/fpu/postproc/negateintres.sv
similarity index 100%
rename from pipelined/src/fpu/postproc/negateintres.sv
rename to src/fpu/postproc/negateintres.sv
diff --git a/pipelined/src/fpu/postproc/normshift.sv b/src/fpu/postproc/normshift.sv
similarity index 100%
rename from pipelined/src/fpu/postproc/normshift.sv
rename to src/fpu/postproc/normshift.sv
diff --git a/pipelined/src/fpu/postproc/postprocess.sv b/src/fpu/postproc/postprocess.sv
similarity index 100%
rename from pipelined/src/fpu/postproc/postprocess.sv
rename to src/fpu/postproc/postprocess.sv
diff --git a/pipelined/src/fpu/postproc/resultsign.sv b/src/fpu/postproc/resultsign.sv
similarity index 100%
rename from pipelined/src/fpu/postproc/resultsign.sv
rename to src/fpu/postproc/resultsign.sv
diff --git a/pipelined/src/fpu/postproc/round.sv b/src/fpu/postproc/round.sv
similarity index 100%
rename from pipelined/src/fpu/postproc/round.sv
rename to src/fpu/postproc/round.sv
diff --git a/pipelined/src/fpu/postproc/roundsign.sv b/src/fpu/postproc/roundsign.sv
similarity index 100%
rename from pipelined/src/fpu/postproc/roundsign.sv
rename to src/fpu/postproc/roundsign.sv
diff --git a/pipelined/src/fpu/postproc/shiftcorrection.sv b/src/fpu/postproc/shiftcorrection.sv
similarity index 100%
rename from pipelined/src/fpu/postproc/shiftcorrection.sv
rename to src/fpu/postproc/shiftcorrection.sv
diff --git a/pipelined/src/fpu/postproc/specialcase.sv b/src/fpu/postproc/specialcase.sv
similarity index 100%
rename from pipelined/src/fpu/postproc/specialcase.sv
rename to src/fpu/postproc/specialcase.sv
diff --git a/pipelined/src/fpu/unpack.sv b/src/fpu/unpack.sv
similarity index 100%
rename from pipelined/src/fpu/unpack.sv
rename to src/fpu/unpack.sv
diff --git a/pipelined/src/fpu/unpackinput.sv b/src/fpu/unpackinput.sv
similarity index 100%
rename from pipelined/src/fpu/unpackinput.sv
rename to src/fpu/unpackinput.sv
diff --git a/pipelined/src/generic/adder.sv b/src/generic/adder.sv
similarity index 100%
rename from pipelined/src/generic/adder.sv
rename to src/generic/adder.sv
diff --git a/pipelined/src/generic/aplusbeq0.sv b/src/generic/aplusbeq0.sv
similarity index 100%
rename from pipelined/src/generic/aplusbeq0.sv
rename to src/generic/aplusbeq0.sv
diff --git a/pipelined/src/generic/arrs.sv b/src/generic/arrs.sv
similarity index 100%
rename from pipelined/src/generic/arrs.sv
rename to src/generic/arrs.sv
diff --git a/pipelined/src/generic/binencoder.sv b/src/generic/binencoder.sv
similarity index 100%
rename from pipelined/src/generic/binencoder.sv
rename to src/generic/binencoder.sv
diff --git a/pipelined/src/generic/clockgater.sv b/src/generic/clockgater.sv
similarity index 100%
rename from pipelined/src/generic/clockgater.sv
rename to src/generic/clockgater.sv
diff --git a/pipelined/src/generic/counter.sv b/src/generic/counter.sv
similarity index 100%
rename from pipelined/src/generic/counter.sv
rename to src/generic/counter.sv
diff --git a/pipelined/src/generic/csa.sv b/src/generic/csa.sv
similarity index 100%
rename from pipelined/src/generic/csa.sv
rename to src/generic/csa.sv
diff --git a/pipelined/src/generic/decoder.sv b/src/generic/decoder.sv
similarity index 100%
rename from pipelined/src/generic/decoder.sv
rename to src/generic/decoder.sv
diff --git a/pipelined/src/generic/flop/flop.sv b/src/generic/flop/flop.sv
similarity index 100%
rename from pipelined/src/generic/flop/flop.sv
rename to src/generic/flop/flop.sv
diff --git a/pipelined/src/generic/flop/flopen.sv b/src/generic/flop/flopen.sv
similarity index 100%
rename from pipelined/src/generic/flop/flopen.sv
rename to src/generic/flop/flopen.sv
diff --git a/pipelined/src/generic/flop/flopenl.sv b/src/generic/flop/flopenl.sv
similarity index 100%
rename from pipelined/src/generic/flop/flopenl.sv
rename to src/generic/flop/flopenl.sv
diff --git a/pipelined/src/generic/flop/flopenr.sv b/src/generic/flop/flopenr.sv
similarity index 100%
rename from pipelined/src/generic/flop/flopenr.sv
rename to src/generic/flop/flopenr.sv
diff --git a/pipelined/src/generic/flop/flopenrc.sv b/src/generic/flop/flopenrc.sv
similarity index 100%
rename from pipelined/src/generic/flop/flopenrc.sv
rename to src/generic/flop/flopenrc.sv
diff --git a/pipelined/src/generic/flop/flopens.sv b/src/generic/flop/flopens.sv
similarity index 100%
rename from pipelined/src/generic/flop/flopens.sv
rename to src/generic/flop/flopens.sv
diff --git a/pipelined/src/generic/flop/flopr.sv b/src/generic/flop/flopr.sv
similarity index 100%
rename from pipelined/src/generic/flop/flopr.sv
rename to src/generic/flop/flopr.sv
diff --git a/pipelined/src/generic/flop/floprc.sv b/src/generic/flop/floprc.sv
similarity index 100%
rename from pipelined/src/generic/flop/floprc.sv
rename to src/generic/flop/floprc.sv
diff --git a/pipelined/src/generic/flop/synchronizer.sv b/src/generic/flop/synchronizer.sv
similarity index 100%
rename from pipelined/src/generic/flop/synchronizer.sv
rename to src/generic/flop/synchronizer.sv
diff --git a/pipelined/src/generic/lzc.sv b/src/generic/lzc.sv
similarity index 100%
rename from pipelined/src/generic/lzc.sv
rename to src/generic/lzc.sv
diff --git a/pipelined/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv
similarity index 100%
rename from pipelined/src/generic/mem/ram1p1rwbe.sv
rename to src/generic/mem/ram1p1rwbe.sv
diff --git a/pipelined/src/generic/mem/ram1p1rwbe_64x128.sv b/src/generic/mem/ram1p1rwbe_64x128.sv
similarity index 100%
rename from pipelined/src/generic/mem/ram1p1rwbe_64x128.sv
rename to src/generic/mem/ram1p1rwbe_64x128.sv
diff --git a/pipelined/src/generic/mem/ram1p1rwbe_64x44.sv b/src/generic/mem/ram1p1rwbe_64x44.sv
similarity index 100%
rename from pipelined/src/generic/mem/ram1p1rwbe_64x44.sv
rename to src/generic/mem/ram1p1rwbe_64x44.sv
diff --git a/pipelined/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv
similarity index 100%
rename from pipelined/src/generic/mem/ram2p1r1wbe.sv
rename to src/generic/mem/ram2p1r1wbe.sv
diff --git a/pipelined/src/generic/mem/ram2p1r1wbe_1024x68.sv b/src/generic/mem/ram2p1r1wbe_1024x68.sv
similarity index 100%
rename from pipelined/src/generic/mem/ram2p1r1wbe_1024x68.sv
rename to src/generic/mem/ram2p1r1wbe_1024x68.sv
diff --git a/pipelined/src/generic/mem/ram2p1r1wbe_64x32.sv b/src/generic/mem/ram2p1r1wbe_64x32.sv
similarity index 100%
rename from pipelined/src/generic/mem/ram2p1r1wbe_64x32.sv
rename to src/generic/mem/ram2p1r1wbe_64x32.sv
diff --git a/pipelined/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv
similarity index 100%
rename from pipelined/src/generic/mem/rom1p1r.sv
rename to src/generic/mem/rom1p1r.sv
diff --git a/pipelined/src/generic/mem/rom1p1r_128x32.sv b/src/generic/mem/rom1p1r_128x32.sv
similarity index 100%
rename from pipelined/src/generic/mem/rom1p1r_128x32.sv
rename to src/generic/mem/rom1p1r_128x32.sv
diff --git a/pipelined/src/generic/mem/rom1p1r_128x64.sv b/src/generic/mem/rom1p1r_128x64.sv
similarity index 100%
rename from pipelined/src/generic/mem/rom1p1r_128x64.sv
rename to src/generic/mem/rom1p1r_128x64.sv
diff --git a/pipelined/src/generic/mux.sv b/src/generic/mux.sv
similarity index 100%
rename from pipelined/src/generic/mux.sv
rename to src/generic/mux.sv
diff --git a/pipelined/src/generic/neg.sv b/src/generic/neg.sv
similarity index 100%
rename from pipelined/src/generic/neg.sv
rename to src/generic/neg.sv
diff --git a/pipelined/src/generic/onehotdecoder.sv b/src/generic/onehotdecoder.sv
similarity index 100%
rename from pipelined/src/generic/onehotdecoder.sv
rename to src/generic/onehotdecoder.sv
diff --git a/pipelined/src/generic/or_rows.sv b/src/generic/or_rows.sv
similarity index 100%
rename from pipelined/src/generic/or_rows.sv
rename to src/generic/or_rows.sv
diff --git a/pipelined/src/generic/priorityonehot.sv b/src/generic/priorityonehot.sv
similarity index 100%
rename from pipelined/src/generic/priorityonehot.sv
rename to src/generic/priorityonehot.sv
diff --git a/pipelined/src/generic/prioritythermometer.sv b/src/generic/prioritythermometer.sv
similarity index 100%
rename from pipelined/src/generic/prioritythermometer.sv
rename to src/generic/prioritythermometer.sv
diff --git a/pipelined/src/hazard/hazard.sv b/src/hazard/hazard.sv
similarity index 100%
rename from pipelined/src/hazard/hazard.sv
rename to src/hazard/hazard.sv
diff --git a/pipelined/src/ieu/alu.sv b/src/ieu/alu.sv
similarity index 100%
rename from pipelined/src/ieu/alu.sv
rename to src/ieu/alu.sv
diff --git a/pipelined/src/ieu/comparator.sv b/src/ieu/comparator.sv
similarity index 100%
rename from pipelined/src/ieu/comparator.sv
rename to src/ieu/comparator.sv
diff --git a/pipelined/src/ieu/controller.sv b/src/ieu/controller.sv
similarity index 100%
rename from pipelined/src/ieu/controller.sv
rename to src/ieu/controller.sv
diff --git a/pipelined/src/ieu/datapath.sv b/src/ieu/datapath.sv
similarity index 100%
rename from pipelined/src/ieu/datapath.sv
rename to src/ieu/datapath.sv
diff --git a/pipelined/src/ieu/extend.sv b/src/ieu/extend.sv
similarity index 100%
rename from pipelined/src/ieu/extend.sv
rename to src/ieu/extend.sv
diff --git a/pipelined/src/ieu/forward.sv b/src/ieu/forward.sv
similarity index 100%
rename from pipelined/src/ieu/forward.sv
rename to src/ieu/forward.sv
diff --git a/pipelined/src/ieu/ieu.sv b/src/ieu/ieu.sv
similarity index 100%
rename from pipelined/src/ieu/ieu.sv
rename to src/ieu/ieu.sv
diff --git a/pipelined/src/ieu/regfile.sv b/src/ieu/regfile.sv
similarity index 100%
rename from pipelined/src/ieu/regfile.sv
rename to src/ieu/regfile.sv
diff --git a/pipelined/src/ieu/shifter.sv b/src/ieu/shifter.sv
similarity index 100%
rename from pipelined/src/ieu/shifter.sv
rename to src/ieu/shifter.sv
diff --git a/pipelined/src/ifu/CodeAligner.py b/src/ifu/CodeAligner.py
similarity index 100%
rename from pipelined/src/ifu/CodeAligner.py
rename to src/ifu/CodeAligner.py
diff --git a/pipelined/src/ifu/bpred/RASPredictor.sv b/src/ifu/bpred/RASPredictor.sv
similarity index 100%
rename from pipelined/src/ifu/bpred/RASPredictor.sv
rename to src/ifu/bpred/RASPredictor.sv
diff --git a/pipelined/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv
similarity index 100%
rename from pipelined/src/ifu/bpred/bpred.sv
rename to src/ifu/bpred/bpred.sv
diff --git a/pipelined/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv
similarity index 100%
rename from pipelined/src/ifu/bpred/btb.sv
rename to src/ifu/bpred/btb.sv
diff --git a/pipelined/src/ifu/bpred/foldedgshare.sv b/src/ifu/bpred/foldedgshare.sv
similarity index 100%
rename from pipelined/src/ifu/bpred/foldedgshare.sv
rename to src/ifu/bpred/foldedgshare.sv
diff --git a/pipelined/src/ifu/bpred/globalhistory.sv b/src/ifu/bpred/globalhistory.sv
similarity index 100%
rename from pipelined/src/ifu/bpred/globalhistory.sv
rename to src/ifu/bpred/globalhistory.sv
diff --git a/pipelined/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv
similarity index 100%
rename from pipelined/src/ifu/bpred/gshare.sv
rename to src/ifu/bpred/gshare.sv
diff --git a/pipelined/src/ifu/bpred/localHistoryPredictor.sv b/src/ifu/bpred/localHistoryPredictor.sv
similarity index 100%
rename from pipelined/src/ifu/bpred/localHistoryPredictor.sv
rename to src/ifu/bpred/localHistoryPredictor.sv
diff --git a/pipelined/src/ifu/bpred/optgshare.sv b/src/ifu/bpred/optgshare.sv
similarity index 100%
rename from pipelined/src/ifu/bpred/optgshare.sv
rename to src/ifu/bpred/optgshare.sv
diff --git a/pipelined/src/ifu/bpred/satCounter2.sv b/src/ifu/bpred/satCounter2.sv
similarity index 100%
rename from pipelined/src/ifu/bpred/satCounter2.sv
rename to src/ifu/bpred/satCounter2.sv
diff --git a/pipelined/src/ifu/bpred/speculativeglobalhistory.sv b/src/ifu/bpred/speculativeglobalhistory.sv
similarity index 100%
rename from pipelined/src/ifu/bpred/speculativeglobalhistory.sv
rename to src/ifu/bpred/speculativeglobalhistory.sv
diff --git a/pipelined/src/ifu/bpred/speculativegshare.sv b/src/ifu/bpred/speculativegshare.sv
similarity index 100%
rename from pipelined/src/ifu/bpred/speculativegshare.sv
rename to src/ifu/bpred/speculativegshare.sv
diff --git a/pipelined/src/ifu/bpred/twoBitPredictor.sv b/src/ifu/bpred/twoBitPredictor.sv
similarity index 100%
rename from pipelined/src/ifu/bpred/twoBitPredictor.sv
rename to src/ifu/bpred/twoBitPredictor.sv
diff --git a/pipelined/src/ifu/decompress.sv b/src/ifu/decompress.sv
similarity index 100%
rename from pipelined/src/ifu/decompress.sv
rename to src/ifu/decompress.sv
diff --git a/pipelined/src/ifu/ifu.sv b/src/ifu/ifu.sv
similarity index 100%
rename from pipelined/src/ifu/ifu.sv
rename to src/ifu/ifu.sv
diff --git a/pipelined/src/ifu/irom.sv b/src/ifu/irom.sv
similarity index 100%
rename from pipelined/src/ifu/irom.sv
rename to src/ifu/irom.sv
diff --git a/pipelined/src/ifu/spill.sv b/src/ifu/spill.sv
similarity index 100%
rename from pipelined/src/ifu/spill.sv
rename to src/ifu/spill.sv
diff --git a/pipelined/src/lsu/amoalu.sv b/src/lsu/amoalu.sv
similarity index 100%
rename from pipelined/src/lsu/amoalu.sv
rename to src/lsu/amoalu.sv
diff --git a/pipelined/src/lsu/atomic.sv b/src/lsu/atomic.sv
similarity index 100%
rename from pipelined/src/lsu/atomic.sv
rename to src/lsu/atomic.sv
diff --git a/pipelined/src/lsu/dtim.sv b/src/lsu/dtim.sv
similarity index 100%
rename from pipelined/src/lsu/dtim.sv
rename to src/lsu/dtim.sv
diff --git a/pipelined/src/lsu/endianswap.sv b/src/lsu/endianswap.sv
similarity index 100%
rename from pipelined/src/lsu/endianswap.sv
rename to src/lsu/endianswap.sv
diff --git a/pipelined/src/lsu/lrsc.sv b/src/lsu/lrsc.sv
similarity index 100%
rename from pipelined/src/lsu/lrsc.sv
rename to src/lsu/lrsc.sv
diff --git a/pipelined/src/lsu/lsu.sv b/src/lsu/lsu.sv
similarity index 100%
rename from pipelined/src/lsu/lsu.sv
rename to src/lsu/lsu.sv
diff --git a/pipelined/src/lsu/subwordread.sv b/src/lsu/subwordread.sv
similarity index 100%
rename from pipelined/src/lsu/subwordread.sv
rename to src/lsu/subwordread.sv
diff --git a/pipelined/src/lsu/subwordwrite.sv b/src/lsu/subwordwrite.sv
similarity index 100%
rename from pipelined/src/lsu/subwordwrite.sv
rename to src/lsu/subwordwrite.sv
diff --git a/pipelined/src/lsu/swbytemask.sv b/src/lsu/swbytemask.sv
similarity index 100%
rename from pipelined/src/lsu/swbytemask.sv
rename to src/lsu/swbytemask.sv
diff --git a/pipelined/src/mdu/intdivrestoring.sv b/src/mdu/intdivrestoring.sv
similarity index 100%
rename from pipelined/src/mdu/intdivrestoring.sv
rename to src/mdu/intdivrestoring.sv
diff --git a/pipelined/src/mdu/intdivrestoringstep.sv b/src/mdu/intdivrestoringstep.sv
similarity index 100%
rename from pipelined/src/mdu/intdivrestoringstep.sv
rename to src/mdu/intdivrestoringstep.sv
diff --git a/pipelined/src/mdu/mdu.sv b/src/mdu/mdu.sv
similarity index 100%
rename from pipelined/src/mdu/mdu.sv
rename to src/mdu/mdu.sv
diff --git a/pipelined/src/mdu/mul.sv b/src/mdu/mul.sv
similarity index 100%
rename from pipelined/src/mdu/mul.sv
rename to src/mdu/mul.sv
diff --git a/pipelined/src/mmu/adrdec.sv b/src/mmu/adrdec.sv
similarity index 100%
rename from pipelined/src/mmu/adrdec.sv
rename to src/mmu/adrdec.sv
diff --git a/pipelined/src/mmu/adrdecs.sv b/src/mmu/adrdecs.sv
similarity index 100%
rename from pipelined/src/mmu/adrdecs.sv
rename to src/mmu/adrdecs.sv
diff --git a/pipelined/src/mmu/hptw.sv b/src/mmu/hptw.sv
similarity index 100%
rename from pipelined/src/mmu/hptw.sv
rename to src/mmu/hptw.sv
diff --git a/pipelined/src/mmu/mmu.sv b/src/mmu/mmu.sv
similarity index 100%
rename from pipelined/src/mmu/mmu.sv
rename to src/mmu/mmu.sv
diff --git a/pipelined/src/mmu/pmachecker.sv b/src/mmu/pmachecker.sv
similarity index 100%
rename from pipelined/src/mmu/pmachecker.sv
rename to src/mmu/pmachecker.sv
diff --git a/pipelined/src/mmu/pmpadrdec.sv b/src/mmu/pmpadrdec.sv
similarity index 100%
rename from pipelined/src/mmu/pmpadrdec.sv
rename to src/mmu/pmpadrdec.sv
diff --git a/pipelined/src/mmu/pmpchecker.sv b/src/mmu/pmpchecker.sv
similarity index 100%
rename from pipelined/src/mmu/pmpchecker.sv
rename to src/mmu/pmpchecker.sv
diff --git a/pipelined/src/mmu/tlb.sv b/src/mmu/tlb.sv
similarity index 100%
rename from pipelined/src/mmu/tlb.sv
rename to src/mmu/tlb.sv
diff --git a/pipelined/src/mmu/tlbcam.sv b/src/mmu/tlbcam.sv
similarity index 100%
rename from pipelined/src/mmu/tlbcam.sv
rename to src/mmu/tlbcam.sv
diff --git a/pipelined/src/mmu/tlbcamline.sv b/src/mmu/tlbcamline.sv
similarity index 100%
rename from pipelined/src/mmu/tlbcamline.sv
rename to src/mmu/tlbcamline.sv
diff --git a/pipelined/src/mmu/tlbcontrol.sv b/src/mmu/tlbcontrol.sv
similarity index 100%
rename from pipelined/src/mmu/tlbcontrol.sv
rename to src/mmu/tlbcontrol.sv
diff --git a/pipelined/src/mmu/tlblru.sv b/src/mmu/tlblru.sv
similarity index 100%
rename from pipelined/src/mmu/tlblru.sv
rename to src/mmu/tlblru.sv
diff --git a/pipelined/src/mmu/tlbmixer.sv b/src/mmu/tlbmixer.sv
similarity index 100%
rename from pipelined/src/mmu/tlbmixer.sv
rename to src/mmu/tlbmixer.sv
diff --git a/pipelined/src/mmu/tlbram.sv b/src/mmu/tlbram.sv
similarity index 100%
rename from pipelined/src/mmu/tlbram.sv
rename to src/mmu/tlbram.sv
diff --git a/pipelined/src/mmu/tlbramline.sv b/src/mmu/tlbramline.sv
similarity index 100%
rename from pipelined/src/mmu/tlbramline.sv
rename to src/mmu/tlbramline.sv
diff --git a/pipelined/src/mmu/vm64check.sv b/src/mmu/vm64check.sv
similarity index 100%
rename from pipelined/src/mmu/vm64check.sv
rename to src/mmu/vm64check.sv
diff --git a/pipelined/src/privileged/csr.sv b/src/privileged/csr.sv
similarity index 100%
rename from pipelined/src/privileged/csr.sv
rename to src/privileged/csr.sv
diff --git a/pipelined/src/privileged/csrc.sv b/src/privileged/csrc.sv
similarity index 100%
rename from pipelined/src/privileged/csrc.sv
rename to src/privileged/csrc.sv
diff --git a/pipelined/src/privileged/csri.sv b/src/privileged/csri.sv
similarity index 100%
rename from pipelined/src/privileged/csri.sv
rename to src/privileged/csri.sv
diff --git a/pipelined/src/privileged/csrm.sv b/src/privileged/csrm.sv
similarity index 100%
rename from pipelined/src/privileged/csrm.sv
rename to src/privileged/csrm.sv
diff --git a/pipelined/src/privileged/csrs.sv b/src/privileged/csrs.sv
similarity index 100%
rename from pipelined/src/privileged/csrs.sv
rename to src/privileged/csrs.sv
diff --git a/pipelined/src/privileged/csrsr.sv b/src/privileged/csrsr.sv
similarity index 100%
rename from pipelined/src/privileged/csrsr.sv
rename to src/privileged/csrsr.sv
diff --git a/pipelined/src/privileged/csru.sv b/src/privileged/csru.sv
similarity index 100%
rename from pipelined/src/privileged/csru.sv
rename to src/privileged/csru.sv
diff --git a/pipelined/src/privileged/privdec.sv b/src/privileged/privdec.sv
similarity index 100%
rename from pipelined/src/privileged/privdec.sv
rename to src/privileged/privdec.sv
diff --git a/pipelined/src/privileged/privileged.sv b/src/privileged/privileged.sv
similarity index 100%
rename from pipelined/src/privileged/privileged.sv
rename to src/privileged/privileged.sv
diff --git a/pipelined/src/privileged/privmode.sv b/src/privileged/privmode.sv
similarity index 100%
rename from pipelined/src/privileged/privmode.sv
rename to src/privileged/privmode.sv
diff --git a/pipelined/src/privileged/privpiperegs.sv b/src/privileged/privpiperegs.sv
similarity index 100%
rename from pipelined/src/privileged/privpiperegs.sv
rename to src/privileged/privpiperegs.sv
diff --git a/pipelined/src/privileged/trap.sv b/src/privileged/trap.sv
similarity index 100%
rename from pipelined/src/privileged/trap.sv
rename to src/privileged/trap.sv
diff --git a/pipelined/src/uncore/ahbapbbridge.sv b/src/uncore/ahbapbbridge.sv
similarity index 100%
rename from pipelined/src/uncore/ahbapbbridge.sv
rename to src/uncore/ahbapbbridge.sv
diff --git a/pipelined/src/uncore/clint_apb.sv b/src/uncore/clint_apb.sv
similarity index 100%
rename from pipelined/src/uncore/clint_apb.sv
rename to src/uncore/clint_apb.sv
diff --git a/pipelined/src/uncore/gpio_apb.sv b/src/uncore/gpio_apb.sv
similarity index 100%
rename from pipelined/src/uncore/gpio_apb.sv
rename to src/uncore/gpio_apb.sv
diff --git a/pipelined/src/uncore/plic_apb.sv b/src/uncore/plic_apb.sv
similarity index 100%
rename from pipelined/src/uncore/plic_apb.sv
rename to src/uncore/plic_apb.sv
diff --git a/pipelined/src/uncore/ram_ahb.sv b/src/uncore/ram_ahb.sv
similarity index 100%
rename from pipelined/src/uncore/ram_ahb.sv
rename to src/uncore/ram_ahb.sv
diff --git a/pipelined/src/uncore/rom_ahb.sv b/src/uncore/rom_ahb.sv
similarity index 100%
rename from pipelined/src/uncore/rom_ahb.sv
rename to src/uncore/rom_ahb.sv
diff --git a/pipelined/src/uncore/uartPC16550D.sv b/src/uncore/uartPC16550D.sv
similarity index 100%
rename from pipelined/src/uncore/uartPC16550D.sv
rename to src/uncore/uartPC16550D.sv
diff --git a/pipelined/src/uncore/uart_apb.sv b/src/uncore/uart_apb.sv
similarity index 100%
rename from pipelined/src/uncore/uart_apb.sv
rename to src/uncore/uart_apb.sv
diff --git a/pipelined/src/uncore/uncore.sv b/src/uncore/uncore.sv
similarity index 100%
rename from pipelined/src/uncore/uncore.sv
rename to src/uncore/uncore.sv
diff --git a/pipelined/src/wally/cvw.sv b/src/wally/cvw.sv
similarity index 100%
rename from pipelined/src/wally/cvw.sv
rename to src/wally/cvw.sv
diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv
similarity index 100%
rename from pipelined/src/wally/wallypipelinedcore.sv
rename to src/wally/wallypipelinedcore.sv
diff --git a/pipelined/src/wally/wallypipelinedsoc.sv b/src/wally/wallypipelinedsoc.sv
similarity index 100%
rename from pipelined/src/wally/wallypipelinedsoc.sv
rename to src/wally/wallypipelinedsoc.sv
diff --git a/synthDC/Makefile b/synthDC/Makefile
index 81d37e9d2..7ef295434 100755
--- a/synthDC/Makefile
+++ b/synthDC/Makefile
@@ -27,7 +27,7 @@ export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)nm_$(FREQ)_MHz_$(time
 export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash)
 export SAIFPOWER ?= 0
 
-OLDCONFIGDIR ?= ${WALLY}/pipelined/config
+OLDCONFIGDIR ?= ${WALLY}/config
 export CONFIGDIR ?= $(OUTPUTDIR)/hdl/config
 CONFIGFILES	?= $(shell find $(CONFIGDIR) -name rv*_*)
 CONFIGFILESTRIM = $(notdir $(CONFIGFILES))
@@ -102,11 +102,11 @@ endif
 	sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED 0/' $(CONFIGDIR)/$@_noPriv/wally-config.vh
 
 ifeq ($(SAIFPOWER), 1)
-	cp -f ../pipelined/regression/power.saif .
+	cp -f ../regression/power.saif .
 endif
 
 ifeq ($(SAIFPOWER), 1)
-	cp -f ../pipelined/regression/power.saif .
+	cp -f ../regression/power.saif .
 endif
 
 freqs: 
diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl
index 9fd86eccc..29a0d3a35 100755
--- a/synthDC/scripts/synth.tcl
+++ b/synthDC/scripts/synth.tcl
@@ -19,7 +19,7 @@ set_host_options -max_cores $::env(MAXCORES)
 # get outputDir and configDir from environment (Makefile)
 set outputDir $::env(OUTPUTDIR)
 set cfg $::env(CONFIGDIR)/$::env(CONFIG)_$::env(MOD)/wally-config.vh
-set hdl_src "../pipelined/src"
+set hdl_src "../src"
 set saifpower $::env(SAIFPOWER)
 set maxopt $::env(MAXOPT)
 set drive $::env(DRIVE)
diff --git a/pipelined/testbench/common/functionName.sv b/testbench/common/functionName.sv
similarity index 100%
rename from pipelined/testbench/common/functionName.sv
rename to testbench/common/functionName.sv
diff --git a/pipelined/testbench/common/instrNameDecTB.sv b/testbench/common/instrNameDecTB.sv
similarity index 100%
rename from pipelined/testbench/common/instrNameDecTB.sv
rename to testbench/common/instrNameDecTB.sv
diff --git a/pipelined/testbench/common/instrTrackerTB.sv b/testbench/common/instrTrackerTB.sv
similarity index 100%
rename from pipelined/testbench/common/instrTrackerTB.sv
rename to testbench/common/instrTrackerTB.sv
diff --git a/pipelined/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv
similarity index 100%
rename from pipelined/testbench/common/wallyTracer.sv
rename to testbench/common/wallyTracer.sv
diff --git a/pipelined/testbench/fp/case.sh b/testbench/fp/case.sh
similarity index 100%
rename from pipelined/testbench/fp/case.sh
rename to testbench/fp/case.sh
diff --git a/pipelined/testbench/sdc/ram2sdLoad.py b/testbench/sdc/ram2sdLoad.py
similarity index 100%
rename from pipelined/testbench/sdc/ram2sdLoad.py
rename to testbench/sdc/ram2sdLoad.py
diff --git a/pipelined/testbench/sdc/ramdisk2.hex b/testbench/sdc/ramdisk2.hex
similarity index 100%
rename from pipelined/testbench/sdc/ramdisk2.hex
rename to testbench/sdc/ramdisk2.hex
diff --git a/pipelined/testbench/sdc/run_tb.do b/testbench/sdc/run_tb.do
similarity index 100%
rename from pipelined/testbench/sdc/run_tb.do
rename to testbench/sdc/run_tb.do
diff --git a/pipelined/testbench/sdc/sdModel.sv b/testbench/sdc/sdModel.sv
similarity index 100%
rename from pipelined/testbench/sdc/sdModel.sv
rename to testbench/sdc/sdModel.sv
diff --git a/pipelined/testbench/sdc/sd_crc_16.sv b/testbench/sdc/sd_crc_16.sv
similarity index 100%
rename from pipelined/testbench/sdc/sd_crc_16.sv
rename to testbench/sdc/sd_crc_16.sv
diff --git a/pipelined/testbench/sdc/sd_crc_7.sv b/testbench/sdc/sd_crc_7.sv
similarity index 100%
rename from pipelined/testbench/sdc/sd_crc_7.sv
rename to testbench/sdc/sd_crc_7.sv
diff --git a/pipelined/testbench/sdc/sd_defines.h b/testbench/sdc/sd_defines.h
similarity index 100%
rename from pipelined/testbench/sdc/sd_defines.h
rename to testbench/sdc/sd_defines.h
diff --git a/pipelined/testbench/sdc/sd_top_tb.sv b/testbench/sdc/sd_top_tb.sv
similarity index 100%
rename from pipelined/testbench/sdc/sd_top_tb.sv
rename to testbench/sdc/sd_top_tb.sv
diff --git a/pipelined/testbench/sdc/wave.do b/testbench/sdc/wave.do
similarity index 100%
rename from pipelined/testbench/sdc/wave.do
rename to testbench/sdc/wave.do
diff --git a/pipelined/testbench/testbench-fp.sv b/testbench/testbench-fp.sv
similarity index 99%
rename from pipelined/testbench/testbench-fp.sv
rename to testbench/testbench-fp.sv
index 62a739c40..8d6826b70 100644
--- a/pipelined/testbench/testbench-fp.sv
+++ b/testbench/testbench-fp.sv
@@ -31,7 +31,7 @@
 
 // steps to run FMA Tests
 //    1) create test vectors in riscv-wally/Tests/fp with: ./run-all.sh
-//    2) go to riscv-wally/pipelined/testbench/fp/Tests
+//    2) go to cvw/testbench/fp/Tests
 //    3) run ./sim-fma-batch
 module testbenchfp;
   parameter TEST="none";
diff --git a/pipelined/testbench/testbench-linux.sv b/testbench/testbench-linux.sv
similarity index 100%
rename from pipelined/testbench/testbench-linux.sv
rename to testbench/testbench-linux.sv
diff --git a/pipelined/testbench/testbench.sv b/testbench/testbench.sv
similarity index 99%
rename from pipelined/testbench/testbench.sv
rename to testbench/testbench.sv
index 853a6e001..a3fa2c093 100644
--- a/pipelined/testbench/testbench.sv
+++ b/testbench/testbench.sv
@@ -238,7 +238,7 @@ logic [3:0] dummy;
       else memfilename = {pathname, tests[test], ".elf.memfile"};
       if (`FPGA) begin
         string romfilename, sdcfilename;
-        romfilename = {"../../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
+        romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
         sdcfilename = {"../testbench/sdc/ramdisk2.hex"};   
         $readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
         $readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
diff --git a/pipelined/testbench/testbench_imperas.sv b/testbench/testbench_imperas.sv
similarity index 100%
rename from pipelined/testbench/testbench_imperas.sv
rename to testbench/testbench_imperas.sv
diff --git a/pipelined/testbench/tests-fp.vh b/testbench/tests-fp.vh
similarity index 100%
rename from pipelined/testbench/tests-fp.vh
rename to testbench/tests-fp.vh
diff --git a/pipelined/testbench/tests.vh b/testbench/tests.vh
similarity index 99%
rename from pipelined/testbench/tests.vh
rename to testbench/tests.vh
index 1d094254e..f119b0a4e 100644
--- a/pipelined/testbench/tests.vh
+++ b/testbench/tests.vh
@@ -33,13 +33,13 @@
 // *** remove MYIMPERASTEST cases when ported 
 
 string tvpaths[] = '{
-    "../../addins/imperas-riscv-tests/work/",
-    "../../tests/riscof/work/riscv-arch-test/",
-    "../../tests/riscof/work/wally-riscv-arch-test/",
-    "../../tests/imperas-riscv-tests/work/",
-    "../../benchmarks/coremark/work/",
-    "../../addins/embench-iot/",
-    "../../tests/custom/work/"
+    "../addins/imperas-riscv-tests/work/",
+    "../tests/riscof/work/riscv-arch-test/",
+    "../tests/riscof/work/wally-riscv-arch-test/",
+    "../tests/imperas-riscv-tests/work/",
+    "../benchmarks/coremark/work/",
+    "../addins/embench-iot/",
+    "../tests/custom/work/"
     };
 
   string coremark[] = '{
diff --git a/tests/testgen/privileged/run.sh b/tests/testgen/privileged/run.sh
index 1fa3a9d01..414f4f2d5 100755
--- a/tests/testgen/privileged/run.sh
+++ b/tests/testgen/privileged/run.sh
@@ -11,7 +11,7 @@ printf "\n\n#####\nStarting tests for $1\n#####\n\n"
 
 if [[ "$2" != "-simonly" ]]
 then
-	cd $WALLY/pipelined/testgen/privileged
+	cd $WALLY/testgen/privileged
 	python3 "testgen-$1.py"
 	printf "\n\n#####\nRan testgen-$1.py Making...\n#####\n\n\n"
 
@@ -48,7 +48,7 @@ fi
 if [[ "$2" == "-sim" || "$2" == "-simonly" ]]
 then
 	printf "\n\n\n#####\nSimulating!\n#####\n\n"
-	cd $WALLY/pipelined/regression
+	cd $WALLY/regression
 	vsim -do wally-privileged.do -c
 fi
 

From 8078cafa2749284b4a624726e40250755a5391fc Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 2 Feb 2023 14:48:23 -0800
Subject: [PATCH 5/9] Renamed regression to sim

---
 .gitignore                                     | 14 +++++++-------
 Install                                        |  2 +-
 Makefile                                       |  4 ++--
 README.md                                      |  2 +-
 benchmarks/coremark/Makefile                   |  4 ++--
 benchmarks/embench/Makefile                    |  2 +-
 setup.imperas.sh                               |  2 +-
 {regression => sim}/Makefile                   | 18 +++++++++---------
 {regression => sim}/buildrootBugFinder.py      |  0
 {regression => sim}/fpga-wave.do               |  0
 {regression => sim}/imperas.ic                 |  0
 {regression => sim}/lint-wally                 |  0
 {regression => sim}/linux-wave.do              |  0
 {regression => sim}/make-tests.sh              |  0
 {regression => sim}/makefile-memfile           |  2 +-
 {regression => sim}/regression-wally           |  0
 {regression => sim}/run-imperasdv-tests.bash   |  0
 {regression => sim}/sim-buildroot              |  0
 {regression => sim}/sim-buildroot-batch        |  0
 {regression => sim}/sim-imperas                |  0
 {regression => sim}/sim-testfloat              |  0
 {regression => sim}/sim-testfloat-batch        |  0
 {regression => sim}/sim-wally                  |  0
 {regression => sim}/sim-wally-batch            |  0
 .../slack-notifier/slack-notifier.py           |  0
 {regression => sim}/test                       |  0
 {regression => sim}/testfloat.do               |  0
 {regression => sim}/wally-pipelined-batch.do   |  0
 .../wally-pipelined-imperas-no-idv.do          |  0
 {regression => sim}/wally-pipelined-imperas.do |  0
 {regression => sim}/wally-pipelined.do         |  0
 {regression => sim}/wave-all.do                |  0
 {regression => sim}/wave-dos/ahb-muldiv.do     |  0
 {regression => sim}/wave-dos/ahb-waves.do      |  0
 {regression => sim}/wave-dos/cache-waves.do    |  0
 {regression => sim}/wave-dos/default-waves.do  |  0
 {regression => sim}/wave-dos/generic.do        |  0
 {regression => sim}/wave-dos/linux-waves.do    |  0
 .../wave-dos/peripheral-waves.do               |  0
 {regression => sim}/wave-fpu.do                |  0
 {regression => sim}/wave.do                    |  0
 synthDC/Makefile                               |  4 ++--
 tests/testgen/privileged/run.sh                |  2 +-
 43 files changed, 28 insertions(+), 28 deletions(-)
 rename {regression => sim}/Makefile (62%)
 rename {regression => sim}/buildrootBugFinder.py (100%)
 rename {regression => sim}/fpga-wave.do (100%)
 rename {regression => sim}/imperas.ic (100%)
 rename {regression => sim}/lint-wally (100%)
 rename {regression => sim}/linux-wave.do (100%)
 rename {regression => sim}/make-tests.sh (100%)
 rename {regression => sim}/makefile-memfile (99%)
 rename {regression => sim}/regression-wally (100%)
 rename {regression => sim}/run-imperasdv-tests.bash (100%)
 rename {regression => sim}/sim-buildroot (100%)
 rename {regression => sim}/sim-buildroot-batch (100%)
 rename {regression => sim}/sim-imperas (100%)
 rename {regression => sim}/sim-testfloat (100%)
 rename {regression => sim}/sim-testfloat-batch (100%)
 rename {regression => sim}/sim-wally (100%)
 rename {regression => sim}/sim-wally-batch (100%)
 rename {regression => sim}/slack-notifier/slack-notifier.py (100%)
 rename {regression => sim}/test (100%)
 rename {regression => sim}/testfloat.do (100%)
 rename {regression => sim}/wally-pipelined-batch.do (100%)
 rename {regression => sim}/wally-pipelined-imperas-no-idv.do (100%)
 rename {regression => sim}/wally-pipelined-imperas.do (100%)
 rename {regression => sim}/wally-pipelined.do (100%)
 rename {regression => sim}/wave-all.do (100%)
 rename {regression => sim}/wave-dos/ahb-muldiv.do (100%)
 rename {regression => sim}/wave-dos/ahb-waves.do (100%)
 rename {regression => sim}/wave-dos/cache-waves.do (100%)
 rename {regression => sim}/wave-dos/default-waves.do (100%)
 rename {regression => sim}/wave-dos/generic.do (100%)
 rename {regression => sim}/wave-dos/linux-waves.do (100%)
 rename {regression => sim}/wave-dos/peripheral-waves.do (100%)
 rename {regression => sim}/wave-fpu.do (100%)
 rename {regression => sim}/wave.do (100%)

diff --git a/.gitignore b/.gitignore
index b389dd1dd..5619adbff 100644
--- a/.gitignore
+++ b/.gitignore
@@ -42,8 +42,8 @@ tests/linux-testgen/buildroot-image-output
 tests/linux-testgen/buildroot-config-src/main.config.old
 tests/linux-testgen/buildroot-config-src/linux.config.old
 tests/linux-testgen/buildroot-config-src/busybox.config.old
-regression/slack-notifier/slack-webhook-url.txt
-regression/logs
+sim/slack-notifier/slack-webhook-url.txt
+sim/logs
 fpga/generator/IP
 fpga/generator/vivado.*
 fpga/generator/.Xil/*
@@ -79,24 +79,24 @@ synthDC/ppa/plots
 synthDC/wallyplots/
 synthDC/runArchive
 synthDC/hdl
-regression/power.saif
+sim/power.saif
 tests/fp/vectors/*.tv
 synthDC/Summary.csv
-regression/wkdir
+sim/wkdir
 tests/custom/work
 tests/custom/*/*/*.list
 tests/custom/*/*/*.elf
 tests/custom/*/*/*.map
 tests/custom/*/*/*.memfile
 tests/custom/crt0/*.a
-regression/sd_model.log
+sim/sd_model.log
 fpga/src/sdc/*
 fpga/src/sdc.tar.gz
 fpga/src/CopiedFiles_do_not_add_to_repo/*
-regression/branch.log
+sim/branch.log
 /fpga/generator/sim/imp-funcsim.v
 /fpga/generator/sim/imp-timesim.sdf
 /fpga/generator/sim/imp-timesim.v
 /fpga/generator/sim/syn-funcsim.v
 external
-regression/results
+sim/results
diff --git a/Install b/Install
index 46f4d78ec..47a91dddd 100644
--- a/Install
+++ b/Install
@@ -328,6 +328,6 @@ source ./setup.sh        # may require some modification for your system. Always
 
   cd <to location of repo clone>
   make
-  cd regression
+  cd sim
   ./regression-wally       #(depends on having Questa installed)
 
diff --git a/Makefile b/Makefile
index 24ba57e57..1f540b56c 100644
--- a/Makefile
+++ b/Makefile
@@ -15,8 +15,8 @@ install:
 	##ln -s ${RISCV}/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe tests/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64/riscvOVPsimPlus.exe
 
 regression:
-	make -C regression
+	make -C sim
 
 clean:
-	make clean -C regression
+	make clean -C sim
 
diff --git a/README.md b/README.md
index 824c7c176..ce92151ed 100644
--- a/README.md
+++ b/README.md
@@ -53,7 +53,7 @@ Edit setup.sh and change the following lines to point to the path and license se
 
 Run a regression simulation with Questa to prove everything is installed.
 
-	$ cd regression
+	$ cd sim
 	$ ./regression-wally       (depends on having Questa installed)
 
 # Toolchain Installation (Sys Admin)
diff --git a/benchmarks/coremark/Makefile b/benchmarks/coremark/Makefile
index b8235ea94..e0aa6661d 100644
--- a/benchmarks/coremark/Makefile
+++ b/benchmarks/coremark/Makefile
@@ -21,8 +21,8 @@ PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \
 all: $(work_dir)/coremark.bare.riscv.elf.memfile
 
 run:
-	(cd ../../regression && (time vsim -c -do "do wally-pipelined-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log))
-	cd ../../benchmarks/coremark/
+	(cd ../../sim && (time vsim -c -do "do wally-pipelined-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log))
+	cd ../benchmarks/coremark/
 #	KMG: added post processing script to give out branch miss proportion along with other stats to the coremark test
 	python3 coremark-postprocess.py
 
diff --git a/benchmarks/embench/Makefile b/benchmarks/embench/Makefile
index b5030d119..0d619c90b 100644
--- a/benchmarks/embench/Makefile
+++ b/benchmarks/embench/Makefile
@@ -34,7 +34,7 @@ sim: modelsim_build_memfile modelsim_run speed
 
 # launches modelsim to simulate tests on wally
 modelsim_run:
-	(cd ../../regression/ && vsim -c -do "do wally-pipelined-batch.do rv32gc embench")
+	(cd ../../sim/ && vsim -c -do "do wally-pipelined-batch.do rv32gc embench")
 	cd ../../benchmarks/embench/
 
 # builds the objdump based on the compiled c elf files
diff --git a/setup.imperas.sh b/setup.imperas.sh
index 4e30fb07f..755a298b5 100644
--- a/setup.imperas.sh
+++ b/setup.imperas.sh
@@ -31,7 +31,7 @@ export IMPERAS_PERSONALITY=CPUMAN_DV_ASYNC
 # setup QUESTA (Imperas only command, YMMV)
 svsetup -questa
 
-pushd regression
+pushd sim
     # With IDV
     IMPERAS_TOOLS=$(pwd)/imperas.ic \
         OTHERFLAGS="+TRACE2LOG_ENABLE=1 VERBOSE=1" \
diff --git a/regression/Makefile b/sim/Makefile
similarity index 62%
rename from regression/Makefile
rename to sim/Makefile
index adc7bc718..6a917bcda 100644
--- a/regression/Makefile
+++ b/sim/Makefile
@@ -2,27 +2,27 @@ all: riscoftests memfiles
 	# *** Build old tests/imperas-riscv-tests for now;
 	# Delete this part when the privileged tests transition over to tests/wally-riscv-arch-test
 	# DH: 2/27/22 temporarily commented out imperas-riscv-tests because license expired
-	#make -C ../../tests/imperas-riscv-tests --jobs
-	#make -C ../../tests/imperas-riscv-tests XLEN=64 --jobs
+	#make -C ../tests/imperas-riscv-tests --jobs
+	#make -C ../tests/imperas-riscv-tests XLEN=64 --jobs
 	# Only compile Imperas tests if they are installed locally.  
 	# They are usually a symlink to $RISCV/imperas-riscv-tests and only 
 	# get compiled there manually during installation
-	#make -C ../../addins/imperas-riscv-tests
-	#make -C ../../addins/imperas-riscv-tests XLEN=64
-	#cd ../../addins/imperas-riscv-tests; elf2hex.sh
-	#cd ../../addins/imperas-riscv-tests; extractFunctionRadix.sh work/*/*/*.elf.objdump
+	#make -C ../addins/imperas-riscv-tests
+	#make -C ../addins/imperas-riscv-tests XLEN=64
+	#cd ../addins/imperas-riscv-tests; elf2hex.sh
+	#cd ../addins/imperas-riscv-tests; extractFunctionRadix.sh work/*/*/*.elf.objdump
 	# Link Linux test vectors 
-	#cd ../../tests/linux-testgen/linux-testvectors/;./tvLinker.sh
+	#cd ../tests/linux-testgen/linux-testvectors/;./tvLinker.sh
 
 allclean: clean all
 
 clean:
-	make clean -C ../../tests/riscof
+	make clean -C ../tests/riscof
 #   make clean -C ../../tests/wally-riscv-arch-test
 #	make allclean -C ../../tests/imperas-riscv-tests
 
 riscoftests: 
 # 	Builds riscv-arch-test 64 and 32-bit versions and builds wally-riscv-arch-test 64 and 32-bit versions
-	make -C ../../tests/riscof/ 
+	make -C ../tests/riscof/ 
 memfiles:
 	make -f makefile-memfile wally-sim-files --jobs
diff --git a/regression/buildrootBugFinder.py b/sim/buildrootBugFinder.py
similarity index 100%
rename from regression/buildrootBugFinder.py
rename to sim/buildrootBugFinder.py
diff --git a/regression/fpga-wave.do b/sim/fpga-wave.do
similarity index 100%
rename from regression/fpga-wave.do
rename to sim/fpga-wave.do
diff --git a/regression/imperas.ic b/sim/imperas.ic
similarity index 100%
rename from regression/imperas.ic
rename to sim/imperas.ic
diff --git a/regression/lint-wally b/sim/lint-wally
similarity index 100%
rename from regression/lint-wally
rename to sim/lint-wally
diff --git a/regression/linux-wave.do b/sim/linux-wave.do
similarity index 100%
rename from regression/linux-wave.do
rename to sim/linux-wave.do
diff --git a/regression/make-tests.sh b/sim/make-tests.sh
similarity index 100%
rename from regression/make-tests.sh
rename to sim/make-tests.sh
diff --git a/regression/makefile-memfile b/sim/makefile-memfile
similarity index 99%
rename from regression/makefile-memfile
rename to sim/makefile-memfile
index 646da5ac3..6c2da42fa 100644
--- a/regression/makefile-memfile
+++ b/sim/makefile-memfile
@@ -1,4 +1,4 @@
-ROOT	:= ../..
+ROOT	:= ..
 SUFFIX	:= work
 ARCHDIR	:= $(ROOT)/tests/riscof
 WALLYDIR:= $(ROOT)/tests/wally-riscv-arch-test
diff --git a/regression/regression-wally b/sim/regression-wally
similarity index 100%
rename from regression/regression-wally
rename to sim/regression-wally
diff --git a/regression/run-imperasdv-tests.bash b/sim/run-imperasdv-tests.bash
similarity index 100%
rename from regression/run-imperasdv-tests.bash
rename to sim/run-imperasdv-tests.bash
diff --git a/regression/sim-buildroot b/sim/sim-buildroot
similarity index 100%
rename from regression/sim-buildroot
rename to sim/sim-buildroot
diff --git a/regression/sim-buildroot-batch b/sim/sim-buildroot-batch
similarity index 100%
rename from regression/sim-buildroot-batch
rename to sim/sim-buildroot-batch
diff --git a/regression/sim-imperas b/sim/sim-imperas
similarity index 100%
rename from regression/sim-imperas
rename to sim/sim-imperas
diff --git a/regression/sim-testfloat b/sim/sim-testfloat
similarity index 100%
rename from regression/sim-testfloat
rename to sim/sim-testfloat
diff --git a/regression/sim-testfloat-batch b/sim/sim-testfloat-batch
similarity index 100%
rename from regression/sim-testfloat-batch
rename to sim/sim-testfloat-batch
diff --git a/regression/sim-wally b/sim/sim-wally
similarity index 100%
rename from regression/sim-wally
rename to sim/sim-wally
diff --git a/regression/sim-wally-batch b/sim/sim-wally-batch
similarity index 100%
rename from regression/sim-wally-batch
rename to sim/sim-wally-batch
diff --git a/regression/slack-notifier/slack-notifier.py b/sim/slack-notifier/slack-notifier.py
similarity index 100%
rename from regression/slack-notifier/slack-notifier.py
rename to sim/slack-notifier/slack-notifier.py
diff --git a/regression/test b/sim/test
similarity index 100%
rename from regression/test
rename to sim/test
diff --git a/regression/testfloat.do b/sim/testfloat.do
similarity index 100%
rename from regression/testfloat.do
rename to sim/testfloat.do
diff --git a/regression/wally-pipelined-batch.do b/sim/wally-pipelined-batch.do
similarity index 100%
rename from regression/wally-pipelined-batch.do
rename to sim/wally-pipelined-batch.do
diff --git a/regression/wally-pipelined-imperas-no-idv.do b/sim/wally-pipelined-imperas-no-idv.do
similarity index 100%
rename from regression/wally-pipelined-imperas-no-idv.do
rename to sim/wally-pipelined-imperas-no-idv.do
diff --git a/regression/wally-pipelined-imperas.do b/sim/wally-pipelined-imperas.do
similarity index 100%
rename from regression/wally-pipelined-imperas.do
rename to sim/wally-pipelined-imperas.do
diff --git a/regression/wally-pipelined.do b/sim/wally-pipelined.do
similarity index 100%
rename from regression/wally-pipelined.do
rename to sim/wally-pipelined.do
diff --git a/regression/wave-all.do b/sim/wave-all.do
similarity index 100%
rename from regression/wave-all.do
rename to sim/wave-all.do
diff --git a/regression/wave-dos/ahb-muldiv.do b/sim/wave-dos/ahb-muldiv.do
similarity index 100%
rename from regression/wave-dos/ahb-muldiv.do
rename to sim/wave-dos/ahb-muldiv.do
diff --git a/regression/wave-dos/ahb-waves.do b/sim/wave-dos/ahb-waves.do
similarity index 100%
rename from regression/wave-dos/ahb-waves.do
rename to sim/wave-dos/ahb-waves.do
diff --git a/regression/wave-dos/cache-waves.do b/sim/wave-dos/cache-waves.do
similarity index 100%
rename from regression/wave-dos/cache-waves.do
rename to sim/wave-dos/cache-waves.do
diff --git a/regression/wave-dos/default-waves.do b/sim/wave-dos/default-waves.do
similarity index 100%
rename from regression/wave-dos/default-waves.do
rename to sim/wave-dos/default-waves.do
diff --git a/regression/wave-dos/generic.do b/sim/wave-dos/generic.do
similarity index 100%
rename from regression/wave-dos/generic.do
rename to sim/wave-dos/generic.do
diff --git a/regression/wave-dos/linux-waves.do b/sim/wave-dos/linux-waves.do
similarity index 100%
rename from regression/wave-dos/linux-waves.do
rename to sim/wave-dos/linux-waves.do
diff --git a/regression/wave-dos/peripheral-waves.do b/sim/wave-dos/peripheral-waves.do
similarity index 100%
rename from regression/wave-dos/peripheral-waves.do
rename to sim/wave-dos/peripheral-waves.do
diff --git a/regression/wave-fpu.do b/sim/wave-fpu.do
similarity index 100%
rename from regression/wave-fpu.do
rename to sim/wave-fpu.do
diff --git a/regression/wave.do b/sim/wave.do
similarity index 100%
rename from regression/wave.do
rename to sim/wave.do
diff --git a/synthDC/Makefile b/synthDC/Makefile
index 7ef295434..f13b38ab6 100755
--- a/synthDC/Makefile
+++ b/synthDC/Makefile
@@ -102,11 +102,11 @@ endif
 	sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED 0/' $(CONFIGDIR)/$@_noPriv/wally-config.vh
 
 ifeq ($(SAIFPOWER), 1)
-	cp -f ../regression/power.saif .
+	cp -f ../sim/power.saif .
 endif
 
 ifeq ($(SAIFPOWER), 1)
-	cp -f ../regression/power.saif .
+	cp -f ../sim/power.saif .
 endif
 
 freqs: 
diff --git a/tests/testgen/privileged/run.sh b/tests/testgen/privileged/run.sh
index 414f4f2d5..d1afb4e89 100755
--- a/tests/testgen/privileged/run.sh
+++ b/tests/testgen/privileged/run.sh
@@ -48,7 +48,7 @@ fi
 if [[ "$2" == "-sim" || "$2" == "-simonly" ]]
 then
 	printf "\n\n\n#####\nSimulating!\n#####\n\n"
-	cd $WALLY/regression
+	cd $WALLY/sim
 	vsim -do wally-privileged.do -c
 fi
 

From a9226e6f73b9ccda7554e4840041e7d6d280c42c Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Thu, 2 Feb 2023 19:40:41 -0800
Subject: [PATCH 6/9] Removed lab1matrix solutions

---
 examples/C/lab1matrix/Makefile  |  33 ------------
 examples/C/lab1matrix/matMult   | Bin 43352 -> 0 bytes
 examples/C/lab1matrix/matMult.c |  87 --------------------------------
 3 files changed, 120 deletions(-)
 delete mode 100644 examples/C/lab1matrix/Makefile
 delete mode 100755 examples/C/lab1matrix/matMult
 delete mode 100644 examples/C/lab1matrix/matMult.c

diff --git a/examples/C/lab1matrix/Makefile b/examples/C/lab1matrix/Makefile
deleted file mode 100644
index 18c011f4f..000000000
--- a/examples/C/lab1matrix/Makefile
+++ /dev/null
@@ -1,33 +0,0 @@
-TARGET = matMult
-
-$(TARGET).objdump: $(TARGET)
-	riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump
-	spike $(TARGET)
-    
-$(TARGET): $(TARGET).c Makefile
-	riscv64-unknown-elf-gcc -o $(TARGET) -g -O\
-	  -march=rv64gc -mabi=lp64d -mcmodel=medany \
-	  -nostdlib -static -lm -fno-tree-loop-distribute-patterns \
-	  -T../common/test.ld -I../common \
-	  $(TARGET).c ../common/crt.S ../common/syscalls.c
-# Compiler flags:
-#  -o $(TARGET) defines the name of the output file
-#  -g generates debugging symbols for gdb
-#  -O turns on basic optimization; -O3 turns on heavy optimization; omit for no optimization
-#  -march=rv64gc -mabi=lp64d =mcmodel=medany generates code for RV64GC with doubles and long/ptrs = 64 bits
-#  -static forces static linking (no dynamic shared libraries on bare metal)
-#  -lm links the math library if necessary (when #include math.h)
-#  -nostdlib avoids inserting standard startup files and default libraries 
-#     because we are using crt.s on bare metal
-#  -fno-tree-loop-distribute-patterns turns replacing loops with memcpy/memset in the std library 
-#  -T specifies the linker file
-#  -I specifies the include path (e.g. for util.h)
-#  The last line defines the C files to compile.  
-#    crt.S is needed as our startup file to initialize the processor
-#    syscalls.c implements printf through the HTIF for Spike
-# other flags from riscv-tests makefiles that don't seem to be important
-#	  -ffast-math -DPREALLOCATE=1 -std=gnu99  \
-#     -fno-common -fno-builtin-printf -nostartfiles -lgcc \
-
-clean:
-	rm -f $(TARGET) $(TARGET).objdump
diff --git a/examples/C/lab1matrix/matMult b/examples/C/lab1matrix/matMult
deleted file mode 100755
index e3d3b25dd44f3d863bf10fb093a7f51972edf99a..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 43352
zcmeHwd3;nwwtrRM?!M{lq(j0IAq2uEgjL)SArKZtbU+;lNJu&h4cSbZO|}F`0^)|5
zF@r=woI&LI{5bdoM;&#Ths!uRjx*13e2yC`jN^ieiVl$9_f*xny#$^2-tV6`pO^dj
zr0dkFb55N)=hUgHdvABv7tEaMl2Y*H5?=^YYarZ2`oQ(ty}I<Em?$m~7CtjXcSTD$
zk*eGA*<c`59x}qXWI96IM3_w<xKa(DDL3`f=)I<7KH_oXZ_`D({pq2ak4udeVu}GK
zGNP;OvOt#wx-8ITfi4SlS)j`TT^8uFK$iu&EYM|vE(`o0wm{=VIjM1y%x}z>lN%??
zDUDNPL1TfO+Bj8CYn&#hH%^x`8fVDM8ZVQVH(oAhHqMk+G+rTRHO`V(HeUHnN&PO@
z$fo==uE1+9;VEcK6Qck9yTAR*Q*ACGS~s|S^|#F)S)V#m%n{=FAMiIvqQu`E7fSri
zu~6b~jvFQZ=6F!zZ;lrw{^r;y@i!+9CI064P~vY+JWBk{NkECeIf*FoHzx@t{^lg3
z#NV70l=##7Y_Le5wo%ZnQTFt2_<4)J&ULCjcj9MF1%cW}gkN?SQ)SvVe@1sX`u3Xa
zMHN-od*6#cmi$rL@r)C_PWCyq`|UmN?K}41NBfT-IPuuYCr{<SGxhz;{yOX9*`Hne
zW#KmqPrv)l2k(FQ*H1qF{IjpV{PvqOr|WaG$9|EUIyS!f)9hUt^{L&*ZYkNZ!PP)^
z+r22i_}yYx-R`>l`giNSrF%-JmVHp>UA|}e)D<7Bh+n*K@nyjegYh@)yWz6cAFfWW
ze6Vs>)hAWS>mFP;YyBtde^6X6vPb?O4&APycUhpz0$mp9vOt#wx-8ITfi4SlS)j`T
zT^8uFK$iu&EYM|vE(>&7pvwYX7U;4-mj${k&}D%x3v^ka%K}{%=(0eB1p?RXay{;O
z#C3}&?~Vg4z3neMTD#jW|DXOt-s2tDmX*_fZ$Ixn_L26ZXEroU>gIZ8|Fpnc_qp~p
z<2n83xw}SB+dnPY&TG5H-rtth|0n(b@b%HOIm^Cu?Vr{(XaZ;(2L)dLlc4gOzZ1u=
zo}$l5azjJU>zhyQKDp<_Z;rq8(JRMZeed<R7oI9PS$<;4@#>F++;{VXTlQ}~a8v)W
zCr&=za@ci?{Y(2-JI2V*CdS_s_~AqDcQ^M=_KI6PvOrGnZGF|@^84pluGZuhF??5R
z=6T|=wlUr^k?dW5$1~0C{o8lnV?TJuk@jcLcn04Scd_TN3^e)Vk(srp4?oq~cA;=&
z-$*^&cw^wIhwL3K38MeV6DQ>r^72dezS3OY{Cd-@rcaMw`thsHCCz&jy#AwWn_p4T
z&QAu7yk9g8=;u4KW5+4axf{=SpS(Efv<PgilK!5Th>hoOIyqr`;}rDy_ZJWPrTgRu
zwNpcTLf%y$1g9?9v&6gf-PQSPcCT@*eYeV2yrID_Wn=%b-PZLV*|-ky1D?`W+x^^)
zZT%mz@s`D>Vq)Uy6|F6Hp5J!AGNJ8ZdyoM1TzuPO%|DphRPciW==q@p-P1l<0RF2t
zLXI_7lC1R`8rqBdH{2)Mi<|8BcQ!Q4yWVeqX8Bjxr#23BxqCNfh#elU=%0Pa-D<nU
zfi|MOe_FuzrD(N<JJ9r{kOgJXky=~5!kvDkX=?h>tiL6Giq|Ys+P?1S=>O=^*W148
z=xA+jezU#g^jiw|r2Pi9X9fCayWDG^`eKlHNPe7|DWLg%4e5a&-`eKITN%wCl%@YI
z6JPS^f6>?Lz8I8EG^qLQigoD~Of#@F{ZmCV{_8c+BeT0`J(?*psppHoensw@)Xn>z
z-*elXPmixZL-41^J5FodqBvOQw8W?%u6RWJ{?@y;-u&w^_F<8C$G(=p>i0#Hr^&XS
z{j%fUTaTVOa_3>h{Dy|1cN|%J_{_eRdp!5p*1@KZ{!gIo!)MX<aK&M9*Ve}04JGcC
zheeZp@2v;V9J!0ypx2jQruf^M#1*%;X4>-4xBA;`*LAl-TAh++D>)w%?Z#;yvE_w*
zE!4LysyfCr-8XSV!@idHpIUak_x+rA_MF<c$?t}bLhe(a9xpmge#m;eX<F8M?qhKu
zIadE=%OSFX-yZaAR=`;OVfz_n^+o#@#g~2%ngPF&B{K1q9lz&iSABZC@3(8O*}aHn
z<f`kvCtB_6Woulc$erHm5tiSo^>o`iYG?n3qoP}*zvb(Wz>S&mu@?V|FGXJSk<hU-
zy_#P<*gsK<!2-7aa(8V3<ZpR#-;ejT&`5mGHX(ByJo8{nctkU<Z~kic=X*Z+&4(|2
z@XEW_o+<ox;a4S}mw&S4!|D%)Zh3Ii=uP9c`s1&1`4fe!Eddd+HDN|;e67bSaEm}f
zfea*h26)_inq1onbEIcMM{82LsBS5_`SiTg3mOYry;phGUXwf3@6Hs~bX)AOUpw7;
z^6Qkq-!l5Pwhb0<wzW@wvu#65{>?cppFK5X+WotC_~K4)oR%qiw}86EJ{?%{mD}Uq
z(KbXp-g3U&(UvKGv2({38#Hc*=1A>VXL4GG?AkaaLG(+=X*u%e#FH=Gv~NrBVC%D|
zI!?De{PiiZ<0f0=wEXO;oR%Ns@0+KZa&ub#^<b-StJu?I<t7N%_E}qpA8bw9Dy)kW
zL?A99BQWnatJQwl705U(tbzoQ^zl8rUTP{t*6H~0@tYo)h;}K5?`c|s(VrfFq&@Kr
zQFZ%k_0|_3A&YntPLEfZ!$+R?ojHBskym|Zs<$4QbKA#zno2a!%-cGuw_fwhrfGp^
z4~i`>ZoH86@3%{rf#-eVrIsPnwwQ4perivX-}AD|wf$jx<fI|fhVP=fuw2`zY_MJ1
zCr#UUK1q;!CryLQmk)YPeYh)Awm$sTQP;SquNF-+0`DA+d-zXBT}?yA0C(G=ZQdi_
z96ht+=2IPkKW~?MM4z;rzU0UY-<;WT(>EPQ=8b%(b^9=J<M!MuT9bs8w5#8=f`h;R
zW@82QcE!OxO_$u|+P<UZRL5sMF}}B+ylLZoK5=c+k<!y=s+(R!`)rK&vxjwAz3KUf
zsjsGKO*4-CrtO=?nb#c5L~QvJ5^^vO*O95W{q>ti4%B9ZzAC*ocp#Xu<ntS5uin2p
zZO!MEv#a)3EkjhFbG`SYyc45Ojyv_(+fTlC=-4wKjZGc*-q7a80zH>J4`2qoA`9MK
zl&h&v<QyORUL^g{P3b+xeU#TcOc;*6n9IN0UD3Y*aZ)Dl+Fk1k5%2Zad%w*2Y~aUu
ztL**R@4Sk+pSOi)e`Y+ij^8(;4fD6PDR;!fzQ-ose&ej>G{i{XhyBfR^BC{cNsR?#
znl6&abO(OZG?3P;pW}@_tO;-3xo;C?*^LL9hurm{hRTQBbtq>`Ca~7HJwuG#ZkJKa
zeKB-<z%xMR0DkHq$=P{-n-BeNxj)xB;FFrREScIb{cMcyr;xiveDmrxPkB5Wr+wMc
z<e^Nu{ntmf96fV!(@~YtBJ=CAzw6BBw}mUvc2p3TM;y8N=$YOvKRoSU@uw8|f(6XJ
zW;s=UDhrTNTh2f2Kah!4r@OGGbr;=#Eel#RbH%>4X1mGT+qO@S@q8_;XT758>)`8S
zJiE}REcnY)wB4x+tO`_?p$t~nhw92gyak$3Ra;qBRaPC!t||^z4<0fsyS%2RU%VJx
zy{xiwh!DB;*_UMJmcs5rj62oQvHx^O$3FZ~8TprH+6edCzjt&DFm-}o{V)7Q%KG05
zPr;ae6EV)S={X^yeGP2kim=nwrtKBjgL$*i-h?l7dW4K48>g<v$2sQ_NLRN0cIOH6
zEmA_cq!(|QqKKofoVr||Wva0Iqv+=L1gk?L?J`2S?Q5ur^Hi$BzDn0Bs7Q6wcU~c*
zr*6BP3b&iw?22=H(dJJl0&miNK&6vBkuVM)<2?l5(NF8Oknp%<`;DMZtP+<}YkFd}
zm`H$(n=2+IQj@jq<#loMM1JC(x>DxbV?-npKdww_2#SJaVpK@)qlV<iz~rG>%0f9x
zcwaZ@e*tQ_K~Ir#z8odx0tx6k-!`#Q<itOenkD7J$V!o^j65exB)uIWo<!qaQqL{u
zid5`g3c#=H)K3Q0Z<QkR9O^LJyV5wO52|#@_5~Kcm|HbUWT(&o$bmgds3AL(>P7f-
zSC1Ci{iwEuYLi6vaAJCfD)}P&0;*V$=bk6BCsSoODpr0-^iM27Z7J1))um#9k7WD^
z)%c46<f`gXRD1S8RpzOBJbfv7MB*|qrs7rPc+|wm#9L9l5LMrPqyH?z<Jt=(tUpj$
zzXX+Ja)Gr(3{tUl7ck&THx^q&HC(eH4qT%Z*TtwLj{p{2V-(kNV7#LZkL^YU2w2*+
z5ufv2&G=m4+JevPT$|81A%b#b6y+*Kxmi)x36V72P~IO!wMkK-U5H-fuDj7HddHDV
zm0!sgS=2ykYZTcdg;4PuMO^lPxa@(WvUCfH?$nYn5u|BK;xJ>tnZVE`+i8GywMbL`
zmW6h)Nb5&ll=JNpk)~WN7sLfcdfE>_@7lJ;s$W(mx+ju;bHOXlNrDfh&nt}RVZhM^
z(bdA&jhrqE-E}o9gs%rxeg-CYRdGo8a;cx+QMI_PPWVPs^&3=GxWub?xE%4&hb0ds
zvAE#71m(MjC|VFo_@hMhGg9P92*K4rAJ14hKn=#<b=1@_5UGa<e}UQvm9efRGF&H&
zYmQ?@rRy1-UOYNud346|=#1rYsf;yJXDp9SRvw+Kl8zzXT*018A;1%-5?9hNsN*`;
zi%>})QnZdwr%5$n9U=12XwB|UzR$gt5I==t?%!u>0Uk<u9-Z<=#f^@WppJi*a613x
z5*+^$A>wSxgh>O@foE{<CkP%+aG=LqfYY7;oYLz?0)GG@sR~S?9w{%RQg>1e+>NH(
zH1ej;+HAg`pK=Io`4L3FhNywbqZQFl4AGc1K*~eXI~T<325Z}w1Ex#1QzEjkdW%Cc
z6W=8e*TBXJb!GM9-zm`w@d)a@{OJ6!v?)N&h3$nGUrZ3*fpOG-r4dQ%2VJuLTZrs&
zH7FjF=|mw5t@^qEY6Gc*A45Pwsdz&AsO<?Qj#80#fS2T7ZN&8eOqXoG29m7$QQ|?_
zgZPht!>S*R>R_r~fECUk7=?pxH_DH)$R8MuN_SORD7--^<6Ys~g|^uP^x!F@(Iwk=
zE74+)%py_CAj+ynZQw4{_M?_iEB4A1YRknYO?ZC~dhZY=Y*T+NjDJc&w!fo=-7R|)
zLlGFjzDu*WEB3cYmwvv-&^+F-PX|nwY;S=Ll-0J%bfS=jW9LDl+$#H!U0#I*tFo+G
zY?bHkLVZX)@=&3XG8729$|0lIdEmN5ssLI8BG|fBrjqpMQ4{G?3=jJY?QJsQ5Sort
zyNIXA^U_M-?W<HhnWINKg<5gR_KV#{)zz%3a`0+7kXnW&7)@8p(Yrvu7WLjaG3H7H
zp}$_NlNpl$$@$P?z1H$&kc)Jeq0d5vu7rBAQFbH4evNieZ_+yVNu<{Ji4byL{0@NL
z77X7$p>`D44iXL2Jf1#q$@c!pNh;baq@RX77wlGfRY+9G0VI4q>Vy2nwIV1J{)W1>
z?a}qUUWP4}m~ch=INYNVvP#BrT1o~XU9$ZPsBwN^F}3!(j4*{gz5sER%%zUy{0lCC
z8)S`49IUFsZZI0&MRi%|vsfn9GHcu3^;pcTd$9|_YPJnqt#}HIcv9TE8FKCC)G!Ad
zA$h>lCEH1y8rA|mXTITKE#zVCU2o5d?b~G>P1~N4y5~aGGlKNOAZdO$sn*P)N723R
z>z9}(-BM6J+~-Ar<C0Llf~ptMnCnqZBm*CwMfQD&sxa^2`DER3uv~Jjcvj8pB&7ei
zx4`(EnsCceO@=9-PbEYC8nwY?Scjfh+s5Q-ta87}cnvM%{b0Kp%Dte{Q#)0kgu`A)
zBEAo)`Z-k<-;?R6uA*vhYJIdjs)fWmkg5}K<1FqpT7Mh&EUFc#UUU))$v3U6>w%7!
zQ*(7dW&H?Dm&t1fn(FPSPM4RN>N))|SAS{@MZ4L{rCo@u<thW-g~aA61TchvD*@b0
zz!U)Y5O5)Y=LpCH;KEM&Vv^9a7By?zZEO3i1~49I-;Jg>+>fEqaovc|`L0zE{Df&S
zb*v+=z%gGL-S36Cp)#q76#5(RpF)`H9RL}W%Fa0jXo3;&3=lJ967G)*S9kO~4HT{f
z02_$Z_m~;tzbg$?-@Y}bm)F9$?t2Z668TpOU#RwJ^RZ_WzDG@KDmsoDhwrzhWq@kY
z@;@@T35J^XZ@OimQF^Xvi5t!><4j8(w;;GR4-fPvZdu7KZy26EriJ!_if71sriFBM
zuwp#L{!ogdp%nHao~A|L9*B#_(;h(mYgDrl_>boh<faIHT#<`-nhAaTz&1bc{Te_D
z9-{pDFo*KzV@a^Mq#ojAd%D#E5;sk`_5swbo2Fa)MCv!2CdOTZNsgN)#a-iQU+AV8
zaF;qgxhcNyx}4-?&_-)#A_*H@TT?G~sR<-fh=cA)sGY~9BC|WB-{Oro&Yq4|x@7xj
zph;XQZs|e0r56wp{b(C;TO8qC+vX+*#Wp4Jb2QmAnH>p$EVpegHa*XhoOshys_@cY
z#C}8NG|olKsV`iz{T2`=A|b3(o7Sbh5vC=}%CT?kK`j$AHiEfP?UT=KNkOAYW@9zK
zXz{oX0=*Y}t_J`-LBKr#UMAoU0Ph3nc?f`u2Beg`o0WqZ9)|oS-rG&mJY>Ym_A=zw
z#6YlAEK!;2?~syM9S}=;UIvm}tY7`;&Pc5?g`9V((zz~9>Fio5;vR>W>eW{0O3+SB
zKrh8u;b6T`B1vcmwtLoKooJ?FeYq5^WWf#iobR);hv+6@PmdrXf|W4@xFH5rA2b6P
zX$DaFCgk<3LyNq+&)rm<gH8SY0J;O{zZO9M&GgYqsNWjyOyuKV8AY1V&jOmt_M4_P
z8?Dg5(<C;E9B4_W;GDil_JfUz*i)+Oh71UG4MWQibY|z7=DUEP5g?g~?jIPT-4Hor
zL9QEUHf})cC#Llgv|OcIY3-seZSHNliMf>!H|Ziovs{!Ui6P@(Q7K7#4EVH#00YYD
zY5xM31kR!0OuK}@Ap~YD1wm>2E&?Y5ELWiL()|lLPc0{(n>|Yppy-nAq;t2A;nH~n
z$d{L3kllU+=6R!N15iO@c12GNpC#C#BC{`gpPhBWL^6D@F4;~48b%>EdpL=eg~JeV
zv&SiTzR28x4zKXuZM3=CVS5Q|iS^<NwLjg4&U0v@{F|ZUiE`yHK&Ix(OCV8m<y``3
zu6#uR&6R{cJXc^;n?=xen*EmFNR{c{V@7+JTV1l90^wZx_{cONg{kW@YchpGv&|#s
zIEZUT`xLsJASZj}1)y=?ippelS44RK9pjY~`rQhmKX&SkWOQ2&>Ivr)K|d&-SXLVl
z6Q)!3a#Xt=fSD)!kaoz+P_^GSGEDDQ{DtsU!9CRb1=)v8Bk!JN`}62vIH_~NIFcv}
zMJC<l8th$ZNXad9VT+#v(hsQ7ul<HuK2#-!o#?nXGYru5Vk*d!1NC)cv_+EN08Kj6
za4^I*LhaGkQnV-ZCBF1_(=AKsM-s*;39`s(jp84p`1>k;(RVw>l9on2z6=H2WS6u7
zRCS+(>S<%w5x9o1lNIP9`q>0dod&E-@BTLUCW@3Bfg(^XB(@kp;--<~*~092*-rUH
z<$*C!VmikRc|hdRQG{;y<<ar!Kkz5y3~Zy;VVYs`BqU5ous~;x6;|9u{p7_77beW`
zyRdh2<EctC#v|nnzr>c%J6*1o>lJ86Q$c84v?O4B39_3^vxzevjmc5nB;?6Udpfv5
zJ!kldc4ChkdJ=tNSXe*b41X4KW|Hn4zD<zVK+lwZVupVNx=HOObCdlER^Q%zNkl5z
zx|spOQfcRb42LGuT>=esP|xwImvoP6>#iiBiwp%IY%`;&BQ@)RfhS+2#Ati<R6{ce
zoFm6V=GdNO$=)e2Gj*P&<N`S7>~gVkXj74sx{1_GbeLi#_fE#RpiPA1JYtk`lEvot
zM7k|(VcaGO``8=ZYqX_pHY@orEP(X)QIql>2GTE%Mv}mOar#YUO`HHq%80NK+{G*o
zK?=uHDjU9=GHPTLrbTIUDI5kLvLxL(T%XQn>mH8Gj3~~qFSYbRJv%!SEsjKZ6BdSO
z_)(j~8ENluIA_H>jr}~`Ft^S*M~?E(MqJMAC+B&7m_SzRqeQ`uee<MaSqk**e#)xZ
zQI<oF<>6^VL5CcYO8S!2gdg^^NNj%+OXe7$BRhAX3gUsRufshE62#yrq1Z5xp|IQ5
zk$-M<2bcoGqLd;-43G8=FnM``98#T3ql&w@AG#UQc@B;Y&%seN5s+`GprkX#2}l?>
zcIuB+{UsQez<lQoL<i%P4HY)ph36}UnH<_(pbQa#xX`e|Fwv|RDKDy-i}Rw+D&xD$
zK`J*~63LaV96CYS(#-VD5+k}a21EA3Ui6wwa@3@-1kIoC3>&IMhT&wI)|BI>L{bdu
z*&=&t&Vo+(NcO2_#LDwZuW5NEa5$e%pDrkK!;l5oM0$i?LTrBUv)|k)c8%O=Gt9SC
zT%&dhd!@M#{<JA^Pn|)2{^Y(_7DiA$$&~YL1|ulvM^L`PlnZPIh0#Y=+6+c8FE|_X
zbq@0_%p9~Cj9|Vlf_WfQF0>hppj;S1xrcQuvKd@sn5~tY*V|lSc5B<_^}^n7xDpMi
zt4`Pq-^94h*gL&z2#=XEW4%}>vTiWXLB<To8k2j2$k}Og`zMC3M=ae1hB7SjLl(JK
z)QPNyNRbT?DePpUNE#~yB^lntxJ^(p-BeaG5`+vlGp-4QJZ$zRMHR!xjXH9X{jCAn
z!*Y>u$k-sn%J2t<-XA;YF}XW!Ze$B}?@ZKRb~a#UEEyS)2xFClB4G<~u#k2PUu!HN
z%k2^ah8&b|$YwEaUMDiu#cnf5j<V#{VvXp-&%<^)(YM#oS?kyDw7J3)EtZM#?1U8D
z8;z364eSacxGAz*Zs7P%1;M>?L0B=ILXAcfOc{SS?^A`%xN6hpx^1XkYv534dSMHL
zj58%3+%Y)Jppb7Ui!fy(Q!cO>jG&~H!IW7{d7aH*A4V0~3=TCYYwgONHdi7fQXXO2
z0fx5k4FXE_StE3*y@uHfOChW<f0>Zw_4^(MibR^9tTuN>LC0{8>A1&tbh*=J3huer
zcTiHyGYxB(byiw4LqsaJAkIR<56EsZw<54UFt{&_V(<Y*U1u}+D5DB(2H#`Ub;4%(
zEP;%`tWO&{!ZG|D^A_3+zQU*?o59x@RcOC$K<-pc#_#L(-wXrw%J7p0=UFdC4hbvc
zbhDsSH=0t|m4>s{l!$i*SqV8mOjgZgg*Jl@S&^{$VIY_A27}icPPJOwTw4;B#~^Fu
z#j=jzIE&Evj?e{Rq4RgzTw@8OI6p&NVs6_&BL*uCN^8V5eqe(80uD0^fpHkT)-YSE
zkp{Uk*C3(#{83puZLXIae8PH>jiwy6q{englEPgwEA(ZMrN|;XmY0;}2b@1K_lLmA
z;GG7gN6Iz6;S|YyQ<#}SCP%jnMso6l(QBD=zRlp=aJTRd*A|8e8D!N>W@V96nR0>6
zU}0F~f}J+k>cWH!Mu?;o%srJd<$RmLC5&2VGg!;0BAY>$Cl?9_x01;UZ3Z1OOol0@
zd1jc5LADTV%4XrQkT*`6TSCdqIp1b5+n|)GY_1Ir6Ees~G&W_CaZI_uW{@BCf)Y06
z+JG=2gApRhrcB8_BH$QgN(nRYli@xraK589OQ4C$WIRwvW6<F&>dXmi@l)e9=GHPe
z8C=h(xnZ&p<L288I%ErM2Kl*xF<+%&V!;u8+`{ta+6+c8)5(ON_g==7g*Jm%FlvF#
zAP)yU6Eo+dy(WjCX9m-lxx{9WyZSEX`3`d`GtaXbj9{h>PN$w1ILyzmGIMPPUt`o#
zo5432wa{kJc^Eg>X7Ct4pId4(n9RDtZJo5Z&e39mdA5k1FN0GI%4&|=X>%nMrem;y
zQ30F5O^hnH8GMFOOKk?9V^q1#AU~*;OKk?vgsB*Gn_()=xZ>rpm)i^`M$&O5BTUC&
zRwNx)CWh%4oEk~Tm8-&Z4Dz#ar5{%w4AU|AZ;|r2axzTEU_AS9sm)+7MwJWuCS#%7
z!j}4p0e6K_Pa2S|4^Okz-wjj6b{TK=FwbNV#T=jP(+Dp$u+~fMy#_oGM!jmlj~tY+
zA21R9kSXI<;uXxej$S)$#{7a~zR-TsfQLE}zilwdW(;1Oj!6jD$Me`0+6;1lhkInq
z)EFUGnR<B)p6iRl!Wmp*P+{SWSsf#UCrf(_p6l#8JOMI>Va$Co9EVJuT^r_L413y(
z+Yw|PuD@V7kqQ53z*kKf7Q&df!^Au}ao@55_oD<`J<rr}yDthq-PCz9Fnw&SFrEYE
zKV#&)Y3fH}@Udaba(KFMI;I^#r$i92`xtRUO(_F5gFGT^FIf2{OjYD$*-so4&dCPm
ztl^rt(`K0MAQ#$~8L~oVU1&dGzyl5{Jm+{JprZ=ImFy54Gz_>rjN<s(9Y(R+vblr#
zHjj@r#GOK$wd4U~uO90tpx8&Rg@v(u-VUQ;Jwy8w&Lcby%hwSe)J#@4X!G=27)F&C
zusV$5p+68t?Kj|KVbqfb<QXA@&Lns_OvR!8Nf^a8yMxCR>}-snV~nrDRGmg1{0Ad<
zai;;BL9aoP*BQ<*IIH2Roi<m7hItvxW4iUA;|!M{rkiTOSz#0#ygZCzkh7TTl`D=H
z0!{$(t^iYr1MrQoG&ZJ-%@lAJ>-aD#!+^cQC=SzW!>CRn8F0LCEKJqO3xUpFAnS5q
z@p#o8^G<;pmmLn&Z+UrIVxKXfV~-_{JvbEQ5@$y<m$h5cIg*xi9>Ws5(-@Wrn}zHS
z3*%8Uxr`udV6vdi;3k8zw&2*!m0OrDyn}QW?V!ydM>(;ERS9RZFplLSeX@Fyxspf0
zzLfLq14e^aS(AAVr!%m5;SL<mlFpnZojFUwoC{0`<b8%YwNn;kxRw<O*tZ+-jxdVB
zI}OU(2y5~fo@TnB&ERuPM^@*GGuB`yja3}-wBe--**C+;;iZf6YAl&|*PZcLoIBAP
z{8^SN44c=bYgzaCo!2Gw#jD(OL&kl@vNJw*ZF6+sm+OY|bi&csfYTimo^TjA$CTtX
zhMC^Gtzx~vy&|rUHMDUGPj^QdlW$s>gX@>aa^Ns+ZXk>^CALZoUSv?}glKb(UsIvI
z2EU0{$IN6o1J7k#Q5eT`%Ii$XNGon4W*Z-fpW_n%?v5Ie?+=<2D^otnlz58QnUapD
z#|_%cw-D#r4DyR)vc!2sZDyE?LGD>%ezCA`jZpFw!+i`Z%`b+z2iNGGow^|2*glkP
z4jJM6+MPsN|D(bE#guYE_&qp&y-p%^@Vjbf`s+<9Jj!6a@xQSkQ%Zxzykjtek}P<)
zk@av`CWD_aYM#v?%QfBbJ7mY05|Psh2gPG?$`Y|i9VPrS*c%*Vg*Joy29oKVDc@qs
z`8I<Qlr+Xplnc&AsUGYaSwAu*xsl;V8HW&HnBOcz2nc(PA=qU~EFBCoUHEH2Ve%Ut
za^cWF7=h!#9A#Xg%^<&Xr7c3|nea6Xpi5QFlQ8qN=7bE>L_(T=iyQA!F}i_(r@xne
zzeCSY?D_j%EQHHh0QiZG_idvLKT7t-KJmmCmCUost4-;ReXuG18Y%IoCer!7m^XHX
z_VU`sYnJzzSpj%;7T!+lQ0!ub?<N{1F1-^C!dXu`EhMoki12czaht5-<)p=_#mm#4
z^OJbY(&ih3K}#wBo}5Gl`38Rg`YK;vin<GMibY?gQeQq5Gl<4BPWW8HSiP6WV@V&d
z`qL9{395P0P3glofGxE3fou&?Yj=XZh9p%rkWA_6sT<a*O1fzv4(YYrzBmA*y_Tg~
zJ(i2g$lie=+5|^30VLMvwbl_g1iDC&7r1V^qSeiyiXm1F24=h)45SXx5S(OS(uf8F
zsq0h&4TgxQ2Oo4Jf@Ibw(Qs!N={{?%BJ_AIuj0lil`%b2X_VBF2jx(di7W%O(w7=N
z?oL)$Jtl)K9VW>}N%|^-!x{wYZo-g<2I_dEkFKm$8uU<9+Duu1UDkRvDmDk%w+H0K
zqx4ud4af{4T4z!x65~=skBt{cbEC0~bWj>7!x$*h!2$AQ5|-_wLJRgKb<8-{M2&;=
z?PbP6UWy$DNlYVYBmrOGPyr<Mz&xp57&HeB<d+yP=urbtF&H~8iUq<uvCz{CJ5paf
zQ#^=EP=HQb5WQIO%0`F^71%y}dr3++(j+CnJerGVoxL=3o!RTU3N=9=l7=Gma&L8`
zj$n#^vQIVjjm~O<7+9wQ4>{Ty5vHEyF=HfHg%Vmd%|GiWk5P|~Mq$x(G~?1X;gOPm
z-BII>^f>WqyJ;Fur;#-O958Dh=~Jz_wvWcsw2HLMKUe(o7%?t*6f^&bU*~~hn%ZZ}
z1L{jQln0jL??L>1jKA}-#H&@^r@maj2q;-cIQsgObu&KPchJX9e0cWK$3yrK9?FBf
zEwes$Q38xy_Pv~bX^Df19<@xt?%|YAYYydGWV4&~`c4=mStCfV-AOE{8w4T2dXU&%
zDiu3jq#=3Z+xAKrTD@vDa#l`syjnL|H?KFbk1<l_)@vA8v?9?M(lr`G!{~(35#))F
zl7{)`@f!>kRJRPJv*f9PI5X9uCrcgGHgiZZn0wZnL1-(-sii>;Ko8@rpA_ecMlF*{
zsDbo?NnV7(fg=dID2NwU!ogCe^}h<C&nONHQeZjY2>OnGJ&K3+IOv8qbY@ec7hiH2
zExzOyT1%<4AXNF8>`NO<Gg=R2Ir0`sAVR8ZAB5{lfNn>Cka)byuBeigB)x1a@et*;
zex@dz5=q2Zu66hfHOh=aNqrKYN-XSg3OI);6R^Njz$c?uqOd9ONDU{be9UV~-XB7i
z3SIQBcY#VRQUfh3l#CqiCE4(%8W!}THUF>oBCW*8U<;2m8?s5^h%qK~9-|t4>=?1*
z*7o9r@ZDpA_&U{13iAM?Ev5EhG;R(7)j}P9cS{eJ62ZgCQ<=~x_Kz+2-D8keLZro@
zEh|YS#-TkAZM83)+=aZcURjXRgUN=PImKGThzIq?o1!@lGrE9`W4dsh`oArUNoxd+
z%Zn{5?VC;ZgVwag<?!`dqax>}9+Mdv<$E$-Z?c(AO>UrwJp~h#VDh_%U=9!b$Qe~M
zBb`%FS*ytC3`Z;^kq(NaQ#w=jMuSQRlzFJdIWVdmO-)K;_y=p1_LE6YMp>G4j;D!U
z=MX*5Rg98v9j~j{C+&gJfvwy}7&eV3!vA;cqvTMp<?{^yO+1WBonS3g<rwQqZAJ_d
z2hW~_Bv32&--7g_OGY)^o}miX!&8S@wi-8(CQd4I)<Knas3{Vo?J*RQO)XCBatei^
z^nl{H4`6s#5A*8rbpG^!ex;dlI`OBNc}6K0Ry8$5p$dk9)^MdjqE)G5$ZJ(7fY)qK
znu!Qn0!h_GEFe8l`k}gtI)g_>$W#OlCotNh@Ub=;Cvm66S=O;KtW}P)K}urzP}rAw
z2cUr>-p>U89qBBb!iEOXjiox?0%pCko8Kx{3ZP|}0vxZUnBfdG8h~OsNrOr00FQCc
zR}yS1ml)03t$jqTKQygFlvqFNG*CzxtqmKc6E%V73d1u-OH?j}L>R*8i;C(?JKM1|
zC3srqAzkh3!?8y<0cdkTX2>QTiOg9tcv*vo^i0cSt>`RHq+<y|%*YJNy^x0~tGzaX
zDkj5^Rj|fq8!bBZlZ*`q4VAVm9P<Qf(VlpX*3ol?uILSNwxZI~Y1a#8O~nmR5oo?~
zH5xD_JyM+RYQTK@R+q|7v~!@GrCJaotPwJZj$pc5LN|9Pbw%D3fxY#f19nbP!Y!*+
z$B~oaFe7!IbW$mF)zjYze_+&2xbTqx0zcOKcqjg729y4Y`shx(WAvpkJb1Y6L**uP
zK+bZu4T;795SvOY##m!aX@fp8tAH1Gbx49`eYj592D<)8FURQjQ|$!S-`b|TQ_)7o
zbGRHUs4<iIn1@2MO`kR_>yJvFQNko%XiPqF0+3cg(nv|7PH-O58-_SzPPFJ?hZ$5b
z(0PaKL)&eVMavzP&Pgg04J3+W6QLv9NxO(x+#*GjV@f9>a&V-Xz)%z<jVP!@R@Zw}
zr@vIw&lqS-t81clleQfC`@5cSkx`;^v|}+3@(o!4a&;(nlA8qiq^vUzM{DvljSyDf
z%|}a6>eB(VAy~T?3g`%?pisl{T7S^~cBHWllB^pv305m2O)>*UFUOrMp{1pngGW4a
zF)1RgOQ=&a5pICPMS4f4<51s=aD{IpI-3E`SVW)h=*$kMBe7Ci2LfVPM>U<6l}kxU
z-pPQHf&nThz-xWJR;@53It!wg8)hwnNc;0VQ{Cw9;YQ656VR4aCsfBXs<SYS?lKO}
zAbH(QX>J&Vmn9+~PY>h}|A&-5BoG=LEU%-+@f9t)86=Bx808rvQ#a;K?{s!_fr~Wq
zY9cdTIKs`2+`3%R*x0I4kVW;-i+bQi<9oGL&i7i6>8YwaS7uRabl!ET=Lu~1I7OtV
zm)e@Kir-14(zT%iGrX<2ISL~DZ>eELZ)Xu%I(}&>QlUcTqelWt64{Kpri4ljd;^AH
z+9L8wtGGc!gI7HhK{)cX%c6QVsVc=d$yo&mK~mHdrx<Zk75t&|VJBMjs1uR1Hv@@B
zWgx`May4w)Nh_ty#uM_FD}=LGia0dtRnh4g(zJX>8o2dw*qND*zRq6P*~ys^L5fa+
zmPxr8#_JLGjn{XuU;*6N%Ma94ib?bXo#mA^_+8Fr)%C%O>ax=8z~bUMfuC-jC+Zj1
z)P=I02KupH`rTz}42ja3P;FgJ>9RmbRMu2iWUG%T+UikNqa)ggT}vcr+N^7`CyzQm
zd(^1BQF$Y?hgTKX1r}dYw|v~#iU8G0f|pd*jvHGFI8aqnT2^^URat3q^(xdu%c{#R
zsjCSrEel2R1*?k7OTk-_J^ae-;pNpe!|~J6Wy33LYHEj<2JsV8!IEX6vf;JGp-@>}
zb-mWCv}RdJWtpfb3(bZl>dQiNLdBtaQMIfxBm#Azyg6dT;+m?m5mi;i_4Q?S!^`Vd
zm5rzi)(4gkUr}6HxoSk&%3}Ia>iQ9rM^qM<jKVLR)&*Cp(M_6@Jvwj9`2syx)9)+7
zT7k0q`l8ypvOustSW_+VlTFl6R8+DoSQ!dd7gd#21!`A;5*DK0ys8i0P*#NBcv==x
zPALjj2VwYN1(YwZEUplXi>pg3K~aaF^#c9KXi*rAD61}}@fFuq1jLG9X=pKlBSmd-
zX@H>7qF!}YUZncaJufa>Nd{R)ZYnCOs9qK*T3%dK2@{GHHFc$Me=t-Os;n2G5)6lQ
zBn?XuL#1V)DOnXN6Gc=nE-ERjK)h&J5eABv)kB>SVz0Oa(Z&6X0DMduEf@8x>H{#X
z2-PgEsSg#Et;Co^i|fjYON(l2pi^0$X#&qOsuoojSK)U>VF0ow3bJ8kF?i|s0gH-g
zAmhfuj--;nPmrz%!k!Vf;?dCrppnzSO^^7k@w!z;Ms28$oI#E$QbRARF2#hX2nNV;
zqP(uAiZm9*l_BLF(xj?ZEY}u>Dhi+<Qo}e$L1+lAD;5W#OGz=T!jq>6BqbQ78D2db
zle()bgY#?Yx4!;Iaf$G}0->E3z)w_+2-H+nAqtm;f|YrTO|(1c5ylPmpdC?D8`42<
zLLV_PJXBLtiKq-#Yuvc8!<SVrt*%*7J-n>4d_=H1P`RuW^QJhkI9Ofw|04p5{3G_t
zV9AJzK;W#J=mf(G{Ub?gYM*^9qNud2ycpIi3azRwtB1*o>O-Z76+i&cr~x=v0hq)Z
zC=J#CF<wpb;lb(&V%p@%7iAAd1{`A2pO|z3o`tBsg{0@N?o<z@!r<uIkwsPXQA{7@
z^ifJ50epx!8J_@JT=W}Q9k?tZ*T^K7!1G*vnU^W(y&1ajlW*$cZ)wjo_59>i*Yso|
z7MME!m<9h}cz$w&ENpabc5m_C9@iTGqr@L4-;vsu_LKDO8F%*B(JMa@JBxP{T@5n-
zSNYH7KcD|f{vY!HnExO7ujc<L|F!%-=f9r+pZO3kSP%Y^{6f>;l;q<nGm{_cMP0Zi
zqB7-IQ=XfWeAaQj1|EK3L^A0bfIq_X>xBH{e)-9@uCejSBH!4F>_T+>79szF7UTI9
zDE<*HvKP_w%UNV+x?nH$Gi2P(uRrlyNwMw6%xh7x{M_#e(~gB%U5r0z@Ka*&{I$jD
zG5Ag99XI?iqPoc5q(8qvceO@C|J&qL?N8Sf?J{Lbw&UkUP7jBk#(UMTloNqtI(|=&
z^~g^i2|CwACggGOmy!Dzd87yF#ow9ZAAQYFKJNOSII|jD-ydJB7k?uq&-9m{yePjh
zt(?_z^yjZIjt|pKX-wXnT1(x)B5Xf?+4GP?_mG?wJs(sHkC)$wV*4?^(!5K>@x^%l
zYI?bm|9u7KI5juK(%>wBU-~*59&crtJP^ra3AZ?A^ohoM#IPY}lj9Ye%};+v)7#?d
zv*LL+L{j5fFddK1a#{Lk|2wr<!c5+n7EAx%g%~W!PwIptge5pzL^oR^B^qIB7L0ke
z%M#trhK79hYPgv^<rbfHgfSY@c|eM68Et3$meX13`+WzV;?sqmWAh=!vll;%F%czQ
zZe551ltdpp@2&)1f`k3bBcE&V{FCpDr#L0~d`&b!CCW6&kIlm&gO82>)dnA%pFT7A
z*m=AO_*A^4v}ts--R>~-vGZt$!N=y&-N5HS&)B^FprMalAAe!+v3dL{gOAM*hYdb<
zoq5UNWAovwz~e3pKBLF=7egPL@82`{*md-;1|OS$jvIVzzB_5~v3Z={*(5)TY^@K)
z8C`L}<L7k6-kABGZ1Aypz_0KwF)=1DWqpU7A;43=vHK7De=4{kKpzcC5%V$L(8sR7
z=NWwLdOk_X!9Qd>H(Ji+hCX)voDDq1N$mP80)hO?%g(Evn^z;~@KvOb3E|y!#O68b
zfR#7W9QyJ`MVt$qjehij2D|*c(azz|oNJu3Ax>tMH6_KBd?*^APgUj!8F?~{IH~J1
zmp(^2hh0ck2UKili*X`@1UfmYlfF5^m@z~h59z#YPI+`NaZW!`CqH$L)(5$$^IZ7+
zgdXVB7IoYbdG)KRLd7L0Lv^}b%uuLoWhhUbgY%5sJVJ>)+>5~RjyOi;UBFe5ha;-U
zqtlwmD=jNoR)MjX*DzdMQc_p8oNJXe0XpP5l*M($)fG5c8pgWnim2vFI@g#s^vWQi
zVM)~Ke1*V(E_A;j5BDAPEeJ<qc^wX}k@5ULg?ob$p^BO5Tn!2`3HuN=MqKU)n81Pf
zBNEJbeepcY)>Yo$nO0|A;d&l`sQyjf5F<6kdof!9%;czRENa9*+F*HKa_j<)m}Kx=
zusGtOYcl=_X1Tn78FnGH;=eI4p{_dXp{a_?0gy}{Kd*zEF47d)x^O<Ze@0vdK=B*H
zavo&<DNJa}i7|D0WiCcVMZx@U&_*%hilr?<TP%*q7tz9w3wNfYu2|Yyw8r9yq3jyX
zc3odx@@Fh<0~%s+MEf!={J3t@h4Y!}KpMCe#o725Ez|9n#x%xM#m?{G-)Rnl|4I`i
z;)><}7qk&>WCRU?GjG?3r#Uc8JM(jS0Qj@<C*GkM9%sVu;D6>j_@8al46!>)7RTl9
zKn4}bjZxR14ZoQNP8;(v;vE37IBM(h6HW1Q%=lyDpLluhX%78)j5c7nc6oG3VT@n;
sR&#|gJ?H}$od{yOQ25RFs6rIQC>K*zJMy#fAKk6_KhcHr8O#6w07E3%>;M1&

diff --git a/examples/C/lab1matrix/matMult.c b/examples/C/lab1matrix/matMult.c
deleted file mode 100644
index b794819f9..000000000
--- a/examples/C/lab1matrix/matMult.c
+++ /dev/null
@@ -1,87 +0,0 @@
-// matMult.c
-// mmasserfrye@hmc.edu 30 January 2022
-
-#include <stdio.h>  // supports printf
-#include <math.h>   // supports fabs
-#include "util.h"   // supports verify
-
-// puts the indicated row of length n from matrix mat into array arr
-void getRow(int n, int row, double *mat, double *arr){
-    int ind;
-    for (int i=0; i<n; i++){
-        ind = i+row*n;
-        arr[i] = mat[ind];
-    }
-}
-
-// computes the dot product of arrays a and b of length n
-double dotproduct(int n, double a[], double b[]) {
-
-    volatile int i;
-    double sum;
-    sum = 0;
-
-    for (i=0; i<n; i++) {
-        if (i==0) sum=0;
-        sum += a[i]*b[i];
-    }
-    return sum;
-}
-
-// multiplies matrices A (m1 x n1m2) and B (n1m2 x n2) and puts the result in Y
-void mult(int m1, int n1m2, int n2, double *A, double *B, double *Y) {
-
-    // transpose B into Bt so we can dot product matching rows
-    double Bt[n2*n1m2];
-    int ind;
-    int indt;
-    for (int i=0; i<n1m2; i++){
-        for (int j=0; j<n2; j++){
-            ind = i*n2+j;
-            indt = j*n1m2+i;
-            Bt[indt] = B[ind];
-        }
-    }
-
-    int indY;
-    double Arow[n1m2];
-    double Bcol[n1m2];
-
-    for (int i=0; i<m1; i++){
-        for (int j=0; j<n2; j++){
-            indY = i*n2+j;
-            getRow(n1m2, i, A, Arow);
-            getRow(n1m2, j, Bt, Bcol);
-            Y[indY] = dotproduct(n1m2, Arow, Bcol);
-        }
-    }
-}
-
-int main(void) {
-
-    // change these bits to test stuff
-    int m = 20;
-    int n = 1;
-    double X[20]; // change to m*n
-    double Y[400]; // change to m^2
-
-    // fill in some numbers so the test feels legit
-    for (int i=0; i<n; i++){
-        X[i] = i;
-    }
- 
-    setStats(1);
-    mult(m, n, m, X, X, Y);
-    setStats(0);
-
-    /*
-    // use this code from Harris's fir.c to print matrix one element at a time
-    // library linked doesn't support printing doubles, so convert to integers to print
-    for (int i=0; i<m*m; i++)  {
-        int tmp = Y[i];
-        printf("Y[%d] = %d\n", i, tmp);
-    }
-    */
-    return 0;
-    
-}
\ No newline at end of file

From 398992db3bb303849c3b273e21dda082122eb571 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Fri, 3 Feb 2023 08:36:03 -0800
Subject: [PATCH 7/9] Updated division radix test script with paths, but script
 is out of date for files it manipulates

---
 bin/radixcopiesmultiregression.sh | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/bin/radixcopiesmultiregression.sh b/bin/radixcopiesmultiregression.sh
index 1953b1da4..f701dada2 100755
--- a/bin/radixcopiesmultiregression.sh
+++ b/bin/radixcopiesmultiregression.sh
@@ -10,39 +10,39 @@ currCopies="define DIVCOPIES 32'h1"
 sed -i "s/$searchRadix/$currRadix/" $configFile
 sed -i "s/$searchCopies/$currCopies/" $configFile
 echo regression on Radix :$currRadix: and Copies :$currCopies:
-./regression/regression-wally
+./sim/regression-wally
 
 currRadix="define RADIX 32'h2"
 currCopies="define DIVCOPIES 32'h2"
 sed -i "s/$searchRadix/$currRadix/" $configFile
 sed -i "s/$searchCopies/$currCopies/" $configFile
 echo regression on Radix :$currRadix: and Copies :$currCopies:
-./regression/regression-wally
+./sim/regression-wally
 
 currRadix="define RADIX 32'h2"
 currCopies="define DIVCOPIES 32'h4"
 sed -i "s/$searchRadix/$currRadix/" $configFile
 sed -i "s/$searchCopies/$currCopies/" $configFile
 echo regression on Radix :$currRadix: and Copies :$currCopies:
-./regression/regression-wally
+./sim/regression-wally
 
 currRadix="define RADIX 32'h4"
 currCopies="define DIVCOPIES 32'h1"
 sed -i "s/$searchRadix/$currRadix/" $configFile
 sed -i "s/$searchCopies/$currCopies/" $configFile
 echo regression on Radix :$currRadix: and Copies :$currCopies:
-./regression/regression-wally
+./sim/regression-wally
 
 currRadix="define RADIX 32'h4"
 currCopies="define DIVCOPIES 32'h2"
 sed -i "s/$searchRadix/$currRadix/" $configFile
 sed -i "s/$searchCopies/$currCopies/" $configFile
 echo regression on Radix :$currRadix: and Copies :$currCopies:
-./regression/regression-wally
+./sim/regression-wally
 
 currRadix="define RADIX 32'h4"
 currCopies="define DIVCOPIES 32'h4"
 sed -i "s/$searchRadix/$currRadix/" $configFile
 sed -i "s/$searchCopies/$currCopies/" $configFile
 echo regression on Radix :$currRadix: and Copies :$currCopies:
-./regression/regression-wally
\ No newline at end of file
+./sim/regression-wally
\ No newline at end of file

From ed02d5a0774023ee631f22710f09e3d833c21ce9 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Fri, 3 Feb 2023 08:36:51 -0800
Subject: [PATCH 8/9] Removed redundant line from synthesis makefile

---
 synthDC/Makefile | 1 -
 1 file changed, 1 deletion(-)

diff --git a/synthDC/Makefile b/synthDC/Makefile
index f13b38ab6..c715a88b4 100755
--- a/synthDC/Makefile
+++ b/synthDC/Makefile
@@ -24,7 +24,6 @@ export DRIVE ?= FLOP
 time := $(shell date +%F-%H-%M)
 hash := $(shell git rev-parse --short HEAD)
 export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash)
-export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash)
 export SAIFPOWER ?= 0
 
 OLDCONFIGDIR ?= ${WALLY}/config

From e0915acad9c141c6ad6e106094c2841c1915097d Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 4 Feb 2023 03:42:20 -0800
Subject: [PATCH 9/9] Improved illegal NaN-box detection and formatted fsgninj

---
 src/fpu/fsgninj.sv     | 18 +++++++++---------
 src/fpu/unpack.sv      | 11 +++++------
 src/fpu/unpackinput.sv | 25 ++++++++++++++-----------
 3 files changed, 28 insertions(+), 26 deletions(-)

diff --git a/src/fpu/fsgninj.sv b/src/fpu/fsgninj.sv
index d5568cabe..0db7dc2f3 100755
--- a/src/fpu/fsgninj.sv
+++ b/src/fpu/fsgninj.sv
@@ -29,11 +29,11 @@
 `include "wally-config.vh"
 
 module fsgninj (  
-	input  logic        		Xs, Ys,	// X and Y sign bits
-	input  logic [`FLEN-1:0] 	X,		// X
-	input  logic [`FMTBITS-1:0]	Fmt,	// format
-	input  logic [1:0]  		OpCtrl,	// operation control
-	output logic [`FLEN-1:0] 	SgnRes	// result
+	input  logic        		    Xs, Ys,	// X and Y sign bits
+	input  logic [`FLEN-1:0] 	  X,		  // X
+	input  logic [`FMTBITS-1:0]	Fmt,	  // format
+	input  logic [1:0]  		    OpCtrl,	// operation control
+	output logic [`FLEN-1:0] 	  SgnRes	// result
 );
 
 	logic ResSgn;	// result sign
@@ -54,13 +54,13 @@ module fsgninj (
 		assign SgnRes = {ResSgn, X[`FLEN-2:0]};
   else if (`FPSIZES == 2)
 		assign SgnRes = {~Fmt|ResSgn, X[`FLEN-2:`LEN1], Fmt ? X[`LEN1-1] : ResSgn, X[`LEN1-2:0]};
-  else if (`FPSIZES == 3) begin
+  else if (`FPSIZES ==  3) begin
 		logic [2:0] SgnBits;
     always_comb
       case (Fmt)
-        `FMT: SgnBits = {ResSgn, X[`LEN1-1], X[`LEN2-1]};
-        `FMT1: SgnBits = {1'b1, ResSgn, X[`LEN2-1]};
-        `FMT2: SgnBits = {2'b11, ResSgn};
+        `FMT:    SgnBits = {ResSgn, X[`LEN1-1], X[`LEN2-1]};
+  	    `FMT1:   SgnBits = {1'b1, ResSgn, X[`LEN2-1]};
+        `FMT2:   SgnBits = {2'b11, ResSgn};
         default: SgnBits = {3{1'bx}};
       endcase
 		assign SgnRes = {SgnBits[2], X[`FLEN-2:`LEN1], SgnBits[1], X[`LEN1-2:`LEN2], SgnBits[0], X[`LEN2-2:0]};
diff --git a/src/fpu/unpack.sv b/src/fpu/unpack.sv
index 13addc2e3..356d7e897 100644
--- a/src/fpu/unpack.sv
+++ b/src/fpu/unpack.sv
@@ -48,15 +48,14 @@ module unpack (
   
   unpackinput unpackinputX (.In(X), .Fmt, .Sgn(Xs), .Exp(Xe), .Man(Xm), .En(XEn),
                           .NaN(XNaN), .SNaN(XSNaN), .ExpNonZero(XExpNonZero),
-                          .Zero(XZero), .Inf(XInf), .ExpMax(XExpMax), .FracZero(XFracZero));
+                          .Zero(XZero), .Inf(XInf), .ExpMax(XExpMax), .FracZero(XFracZero), .Subnorm(XSubnorm));
 
   unpackinput unpackinputY (.In(Y), .Fmt, .Sgn(Ys), .Exp(Ye), .Man(Ym), .En(YEn),
                           .NaN(YNaN), .SNaN(YSNaN), .ExpNonZero(YExpNonZero),
-                          .Zero(YZero), .Inf(YInf), .ExpMax(YExpMax), .FracZero(YFracZero));
+                          .Zero(YZero), .Inf(YInf), .ExpMax(YExpMax), .FracZero(YFracZero), .Subnorm());
 
   unpackinput unpackinputZ (.In(Z), .Fmt, .Sgn(Zs), .Exp(Ze), .Man(Zm), .En(ZEn),
                           .NaN(ZNaN), .SNaN(ZSNaN), .ExpNonZero(ZExpNonZero),
-                          .Zero(ZZero), .Inf(ZInf), .ExpMax(ZExpMax), .FracZero(ZFracZero));
-  // is the input subnormal
-  assign XSubnorm = ~XExpNonZero & ~XFracZero;
-endmodule
\ No newline at end of file
+                          .Zero(ZZero), .Inf(ZInf), .ExpMax(ZExpMax), .FracZero(ZFracZero), .Subnorm());
+ 
+ endmodule
\ No newline at end of file
diff --git a/src/fpu/unpackinput.sv b/src/fpu/unpackinput.sv
index 34663bd8c..b85077d20 100644
--- a/src/fpu/unpackinput.sv
+++ b/src/fpu/unpackinput.sv
@@ -31,16 +31,17 @@ module unpackinput (
   input  logic [`FLEN-1:0]        In,         // inputs from register file
   input  logic                    En,         // enable the input
   input  logic [`FMTBITS-1:0]     Fmt,        // format signal 00 - single 01 - double 11 - quad 10 - half
-  output logic                    Sgn,        // sign bits of XYZ
-  output logic [`NE-1:0]          Exp,        // exponents of XYZ (converted to largest supported precision)
-  output logic [`NF:0]            Man,        // mantissas of XYZ (converted to largest supported precision)
-  output logic                    NaN,        // is XYZ a NaN
-  output logic                    SNaN,       // is XYZ a signaling NaN
-  output logic                    Zero,       // is XYZ zero
-  output logic                    Inf,        // is XYZ infinity
+  output logic                    Sgn,        // sign bits of the number 
+  output logic [`NE-1:0]          Exp,        // exponent of the number  (converted to largest supported precision)
+  output logic [`NF:0]            Man,        // mantissa of the number  (converted to largest supported precision)
+  output logic                    NaN,        // is the number a NaN
+  output logic                    SNaN,       // is the number a signaling NaN
+  output logic                    Zero,       // is the number zero
+  output logic                    Inf,        // is the number infinity
   output logic                    ExpNonZero, // is the exponent not zero
   output logic                    FracZero,   // is the fraction zero
-  output logic                    ExpMax      // does In have the maximum exponent (NaN or Inf)
+  output logic                    ExpMax,      // does In have the maximum exponent (NaN or Inf)
+  output logic                    Subnorm     // is the number subnormal
 );
 
   logic [`NF-1:0] Frac;       // Fraction of XYZ
@@ -261,10 +262,12 @@ module unpackinput (
   end
 
   // Output logic
-  assign FracZero = ~|Frac; // is the fraction zero?
+  assign FracZero = ~|Frac & ~BadNaNBox; // is the fraction zero?
   assign Man = {ExpNonZero, Frac}; // add the assumed one (or zero if Subnormal or zero) to create the significand
   assign NaN = ((ExpMax & ~FracZero)|BadNaNBox)&En; // is the input a NaN?
   assign SNaN = NaN&~Frac[`NF-1]&~BadNaNBox; // is the input a singnaling NaN?
-  assign Inf = ExpMax & FracZero &En; // is the input infinity?
-  assign Zero = ~ExpNonZero & FracZero; // is the input zero?
+  assign Inf = ExpMax & FracZero &En & ~BadNaNBox; // is the input infinity?
+  assign Zero = ~ExpNonZero & FracZero & ~BadNaNBox; // is the input zero?
+  assign Subnorm = ~ExpNonZero & ~FracZero & ~BadNaNBox; // is the input subnormal
+
 endmodule
\ No newline at end of file