Merge pull request #849 from davidharrishmc/dev

lint cleanup and divider optimization

bin/lint-wally

@@ -12,7 +12,7 @@ NC='\033[0m' # No Color
 fails=0
 
 if [ "$1" == "--nightly" ]; then
-    configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i) # fdqh_rv64gc
+    configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i) 
     derivconfigs=`ls $WALLY/config/deriv`
     for entry in $derivconfigs
     do
@@ -21,7 +21,7 @@ if [ "$1" == "--nightly" ]; then
         fi
     done
 else
-    configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i ) # add fdqh_rv64gc when working
+    configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i fdqh_rv64gc)
 fi
 
 for config in ${configs[@]}; do

config/derivlist.txt

@@ -388,10 +388,23 @@ VIRTMEM_SUPPORTED    0
 
 deriv nodcache_rv32gc rv32gc
 DCACHE_SUPPORTED    0
+D_SUPPORTED         0
+ZALRSC_SUPPORTED    0
+ZAAMO_SUPPORTED     0
+ZICBOM_SUPPORTED    0
+ZICBOZ_SUPPORTED    0
+VIRTMEM_SUPPORTED    0
 
+# nocache_rv32gc must also disable several features incompatible with no cache
 deriv nocache_rv32gc rv32gc
 ICACHE_SUPPORTED    0
 DCACHE_SUPPORTED    0
+D_SUPPORTED         0
+ZALRSC_SUPPORTED    0
+ZAAMO_SUPPORTED     0
+ZICBOM_SUPPORTED    0
+ZICBOZ_SUPPORTED    0
+VIRTMEM_SUPPORTED    0
 
 deriv noicache_rv64gc rv64gc
 ICACHE_SUPPORTED    0

src/fpu/fdivsqrt/fdivsqrt.sv

@@ -61,7 +61,6 @@ module fdivsqrt import cvw::*;  #(parameter cvw_t P) (
   logic [P.DIVb+3:0]           D;                            // Iterator Divisor
   logic [P.DIVb:0]             FirstU, FirstUM;              // Intermediate result values
   logic [P.DIVb+1:0]           FirstC;                       // Step tracker
-  logic                        Firstun;                      // Quotient selection
   logic                        WZeroE;                       // Early termination flag
   logic [P.DURLEN-1:0]         CyclesE;                      // FSM cycles
   logic                        SpecialCaseM;                 // Divide by zero, square root of negative, etc.
@@ -89,11 +88,11 @@ module fdivsqrt import cvw::*;  #(parameter cvw_t P) (
 
   fdivsqrtiter #(P) fdivsqrtiter(                                // CSA Iterator
     .clk, .IFDivStartE, .FDivBusyE, .SqrtE, .X, .D, 
-    .FirstU, .FirstUM, .FirstC, .Firstun, .FirstWS(WS), .FirstWC(WC));
+    .FirstU, .FirstUM, .FirstC, .FirstWS(WS), .FirstWC(WC));
 
   fdivsqrtpostproc #(P) fdivsqrtpostproc(                        // Postprocessor
     .clk, .reset, .StallM, .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, 
-    .SqrtE, .Firstun, .SqrtM, .SpecialCaseM, 
+    .SqrtE, .SqrtM, .SpecialCaseM, 
     .UmM, .WZeroE, .DivStickyM, 
     // Int-specific 
     .IntNormShiftM, .ALTBM, .AsM, .BsM, .BZeroM, .W64M, .RemOpM(Funct3M[1]), .AM, 

src/fpu/fdivsqrt/fdivsqrtiter.sv

@@ -35,7 +35,6 @@ module fdivsqrtiter import cvw::*;  #(parameter cvw_t P) (
   input  logic [P.DIVb+3:0] X, D,                  // Q4.DIVb
   output logic [P.DIVb:0]   FirstU, FirstUM,       // U1.DIVb
   output logic [P.DIVb+1:0] FirstC,                // Q2.DIVb
-  output logic              Firstun,
   output logic [P.DIVb+3:0] FirstWS, FirstWC       // Q4.DIVb
 );
 
@@ -119,6 +118,5 @@ module fdivsqrtiter import cvw::*;  #(parameter cvw_t P) (
   assign FirstU  = U[0];
   assign FirstUM = UM[0];
   assign FirstC  = C[0];
-  assign Firstun = un[0];
 endmodule
 

src/fpu/fdivsqrt/fdivsqrtpostproc.sv

@@ -35,7 +35,7 @@ module fdivsqrtpostproc import cvw::*;  #(parameter cvw_t P) (
   input  logic [P.DIVb:0]      FirstU, FirstUM,   // U1.DIVb
   input  logic [P.DIVb+1:0]    FirstC,            // Q2.DIVb
   input  logic                 SqrtE,
-  input  logic                 Firstun, SqrtM, SpecialCaseM, 
+  input  logic                 SqrtM, SpecialCaseM, 
   input  logic [P.XLEN-1:0]    AM,                // U/Q(XLEN.0)
   input  logic                 RemOpM, ALTBM, BZeroM, AsM, BsM, W64M,
   input  logic [P.DIVBLEN-1:0] IntNormShiftM,     
@@ -71,7 +71,7 @@ module fdivsqrtpostproc import cvw::*;  #(parameter cvw_t P) (
     mux2 #(P.DIVb+4) fzeromux(FZeroDivE, FZeroSqrtE, SqrtE, FZeroE);
     csa #(P.DIVb+4) fadd(WS, WC, FZeroE, 1'b0, WSF, WCF); // compute {WCF, WSF} = {WS + WC + FZero};
     aplusbeq0 #(P.DIVb+4) wcfpluswsfeq0(WCF, WSF, wfeq0E);
-    assign WZeroE = weq0E|(wfeq0E & Firstun);
+    assign WZeroE = weq0E | wfeq0E;
   end else begin
     assign WZeroE = weq0E;
   end 

src/fpu/fdivsqrt/fdivsqrtpreproc.sv

@@ -233,8 +233,9 @@ module fdivsqrtpreproc import cvw::*;  #(parameter cvw_t P) (
     flopen #(P.XLEN)    srcareg(clk, IFDivStartE, AE,       AM);
     if (P.XLEN==64) 
       flopen #(1)        w64reg(clk, IFDivStartE, W64E,     W64M);
+    else assign W64M = 0;
   end else
-    assign {ALTBM, W64M, AsM, BsM, BZeroM, AM, IntNormShiftM} = 0;
+    assign {ALTBM, W64M, AsM, BsM, BZeroM, AM, IntNormShiftM} = '0;
 
 endmodule
 

src/fpu/postproc/postprocess.sv

@@ -134,6 +134,7 @@ module postprocess import cvw::*;  #(parameter cvw_t P) (
       assign OutFmt = IntToFp|~CvtOp ? Fmt : (OpCtrl[1:0] == P.FMT); 
   else if (P.FPSIZES == 3 | P.FPSIZES == 4) 
       assign OutFmt = IntToFp|~CvtOp ? Fmt : OpCtrl[1:0]; 
+  else assign OutFmt = 0; // FPSIZES = 1
 
   ///////////////////////////////////////////////////////////////////////////////
   // Normalization

src/ieu/kmu/zknde64.sv

@@ -38,11 +38,14 @@ module zknde64 import cvw::*; #(parameter cvw_t P) (
    
     if (P.ZKND_SUPPORTED) // ZKND supports aes64ds, aes64dsm, aes64im
         aes64d    aes64d(.rs1(A), .rs2(B), .finalround(ZKNSelect[2]), .aes64im(ZKNSelect[3]), .result(aes64dRes)); // decode AES
+    else assign aes64dRes = '0;
     if (P.ZKNE_SUPPORTED) begin // ZKNE supports aes64es, aes64esm
         aes64e    aes64e(.rs1(A), .rs2(B), .finalround(ZKNSelect[2]), .Sbox0Out, .SboxEIn, .result(aes64eRes));
         mux2 #(32) sboxmux(SboxEIn, SboxKIn, ZKNSelect[1], Sbox0In);
-    end else    
+    end else begin  
+        assign aes64eRes = '0;
         assign Sbox0In = SboxKIn;
+    end
     
     // One S Box is always needed for aes64ks1i and is also needed for aes64e if that is supported.  Put it at the top level to allow sharing
     aessbox32 sbox(Sbox0In, Sbox0Out);                       // Substitute bytes of value obtained for tmp2 using Rijndael sbox

src/lsu/lsu.sv

@@ -144,7 +144,6 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
   
   logic                  DTLBMissM;                              // DTLB miss causes HPTW walk
   logic                  DTLBWriteM;                             // Writes PTE and PageType to DTLB
-  logic                  DataUpdateDAM;                          // DTLB hit needs to update dirty or access bits
   logic                  LSULoadAccessFaultM;                    // Load acces fault
   logic                  LSUStoreAmoAccessFaultM;                // Store access fault
   logic                  IgnoreRequestTLB;                       // On either ITLB or DTLB miss, ignore miss so HPTW can handle
@@ -194,7 +193,7 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
 
   if(P.VIRTMEM_SUPPORTED) begin : hptw
     hptw #(P) hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissOrUpdateAF, .ITLBWriteF,
-      .DTLBMissOrUpdateDAM, .DTLBWriteM, .DataUpdateDAM,
+      .DTLBMissOrUpdateDAM, .DTLBWriteM,
       .FlushW, .DCacheBusStallM, .SATP_REGW, .PCSpillF,
       .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_ADUE, .PrivilegeModeW,
       .ReadDataM(ReadDataM[P.XLEN-1:0]), // ReadDataM is LLEN, but HPTW only needs XLEN
@@ -236,6 +235,8 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
   if(P.ZICSR_SUPPORTED == 1) begin : dmmu
     logic DisableTranslation;                             // During HPTW walk or D$ flush disable virtual memory address translation
     logic WriteAccessM;
+    logic DataUpdateDAM;                                  // DTLB hit needs to update dirty or access bits
+
     assign DisableTranslation = SelHPTW | FlushDCacheM;
     assign WriteAccessM = PreLSURWM[0];
     mmu #(.P(P), .TLB_ENTRIES(P.DTLB_ENTRIES), .IMMU(0))

src/mmu/hptw.sv

@@ -49,7 +49,6 @@ module hptw import cvw::*;  #(parameter cvw_t P) (
   input  logic              ITLBMissOrUpdateAF,
   input  logic              DTLBMissOrUpdateDAM,
   input  logic              FlushW,
-  input  logic              DataUpdateDAM,
   output logic [P.XLEN-1:0] PTE,                    // page table entry to TLBs
   output logic [1:0]        PageType,               // page type to TLBs
   output logic              ITLBWriteF, DTLBWriteM, // write TLB with new entry

testbench/testbench.sv

@@ -110,6 +110,7 @@ module testbench;
   logic Validate;
   logic SelectTest;
   logic TestComplete;
+  logic PrevPCZero;
 
   initial begin
     // look for arguments passed to simulation, or use defaults
@@ -354,15 +355,6 @@ module testbench;
         $display("Benchmark: coremark is done.");
         $stop;
       end
-    if (P.ZICSR_SUPPORTED & dut.core.ifu.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.ieu.InstrValidM) begin 
-      $display("Program fetched illegal instruction 0x00000000 from address 0x00000000.  Might be fault with no fault handler.");
-      //$stop; // presently wally32/64priv tests trigger this for reasons not yet understood.
-    end
-
-  // modifications 4/3/24 kunlin & harris to speed up Verilator
-  // For some reason, Verilator runs ~100x slower when these SelectTest and Validate codes are in the posedge clk block
-  //end // added
-  //always @(posedge SelectTest) // added
     if(SelectTest) begin
       if (riscofTest) begin 
         memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
@@ -402,6 +394,7 @@ module testbench;
   always @(posedge Validate) // added
 `endif
     if(Validate) begin
+      if (PrevPCZero) totalerrors = totalerrors + 1; //  error if PC is stuck at zero
       if (TEST == "buildroot")
         $fclose(uartoutfile);
       if (TEST == "embench") begin
@@ -632,8 +625,10 @@ module testbench;
     loggers (clk, reset, DCacheFlushStart, DCacheFlushDone, memfilename, TEST);
 
   // track the current function or global label
+  if (DEBUG > 0 | ((PrintHPMCounters | BPRED_LOGGER) & P.ZICNTR_SUPPORTED)) begin : FunctionName
     FunctionName #(P) FunctionName(.reset(reset_ext | TestBenchReset),
 			      .clk(clk), .ProgramAddrMapFile(ProgramAddrMapFile), .ProgramLabelMapFile(ProgramLabelMapFile));
+  end
 
   // Append UART output to file for tests
   if (P.UART_SUPPORTED) begin: uart_logger
@@ -652,10 +647,16 @@ module testbench;
   // 1. jump to self loop (0x0000006f)
   // 2. a store word writes to the address "tohost"
   // 3. or PC is stuck at 0
-  always_comb begin
-    TestComplete = ((InstrM == 32'h6f) & dut.core.InstrValidM ) |
-		   ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"] & dut.core.lsu.IEUAdrM != 0) & InstrMName == "SW" ) | 
-    (FunctionName.PCM == 4 & dut.core.ieu.c.InstrValidM);
+
+
+  always @(posedge clk) begin
+  //  if (reset) PrevPCZero <= 0;
+  //  else if (dut.core.InstrValidM) PrevPCZero <= (FunctionName.PCM == 0 & dut.core.ifu.InstrM == 0);
+    TestComplete <= ((InstrM == 32'h6f) & dut.core.InstrValidM ) |
+		   ((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"] & dut.core.lsu.IEUAdrM != 0) & InstrMName == "SW"); // |
+    //   (FunctionName.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.InstrValidM & PrevPCZero));
+   // if (FunctionName.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.InstrValidM & PrevPCZero)
+    //  $error("Program fetched illegal instruction 0x00000000 from address 0x00000000 twice in a row.  Usually due to fault with no fault handler.");
   end 
 
   DCacheFlushFSM #(P) DCacheFlushFSM(.clk, .start(DCacheFlushStart), .done(DCacheFlushDone));