From e182cac9bc430ecfc3ce2a2debc5644cfa2cf8c1 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 17 Jul 2021 15:24:26 -0400
Subject: [PATCH] hptw: Removed NonBusTrapM from LSU

---
 wally-pipelined/src/privileged/trap.sv | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/wally-pipelined/src/privileged/trap.sv b/wally-pipelined/src/privileged/trap.sv
index ea50fddc0..1d0c3d348 100644
--- a/wally-pipelined/src/privileged/trap.sv
+++ b/wally-pipelined/src/privileged/trap.sv
@@ -56,7 +56,7 @@ module trap (
   logic [11:0] PendingIntsM; 
   //logic InterruptM;
   logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector;
-  logic NonBusTrapM, BusTrapM;
+  logic ExceptionNonIntM;
 
   // Determine pending enabled interrupts
   assign MIntGlobalEnM = (PrivilegeModeW != `M_MODE) || STATUS_MIE; // if M ints enabled or lower priv 3.1.9
@@ -64,7 +64,8 @@ module trap (
   assign PendingIntsM = ((MIP_REGW & MIE_REGW) & ({12{MIntGlobalEnM}} & 12'h888)) | ((SIP_REGW & SIE_REGW) & ({12{SIntGlobalEnM}} & 12'h222));
   assign PendingInterruptM = (|PendingIntsM) & InstrValidM;  
   assign InterruptM = PendingInterruptM & ~CommittedM;
-  assign ExceptionM = BusTrapM | NonBusTrapM;
+  //assign ExceptionM = BusTrapM | NonBusTrapM;
+  assign ExceptionM = TrapM;
   
   // interrupt if any sources are pending
   // & with a M stage valid bit to avoid interrupts from interrupt a nonexistent flushed instruction (in the M stage)
@@ -73,13 +74,13 @@ module trap (
   // Trigger Traps and RET
   //   Created groups of trap signals so that bus could take in all traps it doesn't already produce (i.e. using just TrapM to squash access created circular paths)
   // *** Ben July 06, 2021 probably remove bus and nonbus trapm after dcache implemenation.
-  assign BusTrapM = LoadAccessFaultM | StoreAccessFaultM;
-  assign NonBusTrapM = InstrMisalignedFaultM | InstrAccessFaultM | IllegalInstrFaultM |
+  //assign BusTrapM = LoadAccessFaultM | StoreAccessFaultM;
+  assign ExceptionNonIntM = InstrMisalignedFaultM | InstrAccessFaultM | IllegalInstrFaultM |
                        LoadMisalignedFaultM | StoreMisalignedFaultM |
                        InstrPageFaultM | LoadPageFaultM | StorePageFaultM |
                        BreakpointFaultM | EcallFaultM |
-                       InterruptM;
-  assign TrapM = BusTrapM | NonBusTrapM;
+                       LoadAccessFaultM | StoreAccessFaultM;
+  assign TrapM = ExceptionNonIntM | InterruptM;
   assign MTrapM = TrapM & (NextPrivilegeModeM == `M_MODE);
   assign STrapM = TrapM & (NextPrivilegeModeM == `S_MODE) & `S_SUPPORTED;
   assign UTrapM = TrapM & (NextPrivilegeModeM == `U_MODE) & `N_SUPPORTED;