diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv
index ba73f73a6..0efbcf41b 100644
--- a/wally-pipelined/src/cache/dcache.sv
+++ b/wally-pipelined/src/cache/dcache.sv
@@ -44,10 +44,11 @@ module dcache
input logic [`XLEN-1:0] WriteDataM,
output logic [`XLEN-1:0] ReadDataW,
output logic DCacheStall,
- output logic CommittedM,
+ output logic CommittedM,
// inputs from TLB and PMA/P
- input logic FaultM,
+ input logic ExceptionM,
+ input logic PendingInterruptM,
input logic DTLBMissM,
input logic CacheableM,
// ahb side
@@ -409,7 +410,7 @@ module dcache
NextState = STATE_PTW_MISS_FETCH_WDV;
end
// amo hit
- else if(|AtomicM & CacheableM & ~FaultM & CacheHit & ~DTLBMissM) begin
+ else if(|AtomicM & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
NextState = STATE_AMO_UPDATE;
DCacheStall = 1'b1;
@@ -417,7 +418,7 @@ module dcache
else NextState = STATE_READY;
end
// read hit valid cached
- else if(MemRWM[1] & CacheableM & ~FaultM & CacheHit & ~DTLBMissM) begin
+ else if(MemRWM[1] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
NextState = STATE_READY;
DCacheStall = 1'b0;
@@ -425,7 +426,7 @@ module dcache
else NextState = STATE_READY;
end
// write hit valid cached
- else if (MemRWM[0] & CacheableM & ~FaultM & CacheHit & ~DTLBMissM) begin
+ else if (MemRWM[0] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
SelAdrM = 1'b1;
DCacheStall = 1'b0;
SRAMWordWriteEnableM = 1'b1;
@@ -435,27 +436,27 @@ module dcache
else NextState = STATE_READY;
end
// read or write miss valid cached
- else if((|MemRWM) & CacheableM & ~FaultM & ~CacheHit & ~DTLBMissM) begin
+ else if((|MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & ~CacheHit & ~DTLBMissM) begin
NextState = STATE_MISS_FETCH_WDV;
CntReset = 1'b1;
DCacheStall = 1'b1;
end
// uncached write
- else if(MemRWM[0] & ~CacheableM & ~FaultM & ~DTLBMissM) begin
+ else if(MemRWM[0] & ~CacheableM & ~ExceptionM & ~DTLBMissM) begin
NextState = STATE_UNCACHED_WRITE;
CntReset = 1'b1;
DCacheStall = 1'b1;
AHBWrite = 1'b1;
end
// uncached read
- else if(MemRWM[1] & ~CacheableM & ~FaultM & ~DTLBMissM) begin
+ else if(MemRWM[1] & ~CacheableM & ~ExceptionM & ~DTLBMissM) begin
NextState = STATE_UNCACHED_READ;
CntReset = 1'b1;
DCacheStall = 1'b1;
AHBRead = 1'b1;
end
// fault
- else if(AnyCPUReqM & FaultM & ~DTLBMissM) begin
+ else if(AnyCPUReqM & (ExceptionM | PendingInterruptM) & ~DTLBMissM) begin
NextState = STATE_READY;
end
else NextState = STATE_READY;
diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index 7a02ff2fa..71113fbd2 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -40,6 +40,8 @@ module lsu
input logic [2:0] Funct3M,
input logic [6:0] Funct7M,
input logic [1:0] AtomicM,
+ input logic ExceptionM,
+ input logic PendingInterruptM,
output logic CommittedM,
output logic SquashSCW,
output logic DataMisalignedM,
@@ -319,7 +321,8 @@ module lsu
.ReadDataW(ReadDataWfromDCache),
.DCacheStall(DCacheStall),
.CommittedM(CommittedM),
- .FaultM(LoadMisalignedFaultM | StoreMisalignedFaultM), // this is wrong needs to be all faults.
+ .ExceptionM(ExceptionM),
+ .PendingInterruptM(PendingInterruptM),
.DTLBMissM(DTLBMissM),
.CacheableM(CacheableM),
diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv
index e80c0b851..fcc225db2 100644
--- a/wally-pipelined/src/privileged/privileged.sv
+++ b/wally-pipelined/src/privileged/privileged.sv
@@ -64,6 +64,8 @@ module privileged (
input logic LoadAccessFaultM,
input logic StoreAccessFaultM,
+ output logic ExceptionM,
+ output logic PendingInterruptM,
output logic IllegalFPUInstrE,
output logic [1:0] PrivilegeModeW,
output logic [`XLEN-1:0] SATP_REGW,
diff --git a/wally-pipelined/src/privileged/trap.sv b/wally-pipelined/src/privileged/trap.sv
index 9eec51c26..7462353db 100644
--- a/wally-pipelined/src/privileged/trap.sv
+++ b/wally-pipelined/src/privileged/trap.sv
@@ -27,23 +27,26 @@
`include "wally-config.vh"
module trap (
- input logic clk, reset,
- input logic InstrMisalignedFaultM, InstrAccessFaultM, IllegalInstrFaultM,
- input logic BreakpointFaultM, LoadMisalignedFaultM, StoreMisalignedFaultM,
- input logic LoadAccessFaultM, StoreAccessFaultM, EcallFaultM, InstrPageFaultM,
- input logic LoadPageFaultM, StorePageFaultM,
- input logic mretM, sretM, uretM,
- input logic [1:0] PrivilegeModeW, NextPrivilegeModeM,
- input logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW,
- input logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW,
- input logic STATUS_MIE, STATUS_SIE,
- input logic [`XLEN-1:0] PCM,
- input logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM,
- input logic [31:0] InstrM,
- input logic StallW,
- input logic InstrValidM, CommittedM,
- output logic NonBusTrapM, TrapM, MTrapM, STrapM, UTrapM, RetM,
- output logic InterruptM,
+ input logic clk, reset,
+ input logic InstrMisalignedFaultM, InstrAccessFaultM, IllegalInstrFaultM,
+ input logic BreakpointFaultM, LoadMisalignedFaultM, StoreMisalignedFaultM,
+ input logic LoadAccessFaultM, StoreAccessFaultM, EcallFaultM, InstrPageFaultM,
+ input logic LoadPageFaultM, StorePageFaultM,
+ input logic mretM, sretM, uretM,
+ input logic [1:0] PrivilegeModeW, NextPrivilegeModeM,
+ input logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW,
+ input logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW,
+ input logic STATUS_MIE, STATUS_SIE,
+ input logic [`XLEN-1:0] PCM,
+ input logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM,
+ input logic [31:0] InstrM,
+ input logic StallW,
+ input logic InstrValidM, CommittedM,
+ output logic NonBusTrapM, TrapM, MTrapM, STrapM, UTrapM, RetM,
+ output logic InterruptM,
+ output logic ExceptionM,
+ output logic PendingInterruptM,
+
output logic [`XLEN-1:0] PrivilegedNextPCM, CauseM, NextFaultMtvalM
// output logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW,
// input logic WriteMIPM, WriteSIPM, WriteUIPM, WriteMIEM, WriteSIEM, WriteUIEM
@@ -59,7 +62,10 @@ module trap (
assign MIntGlobalEnM = (PrivilegeModeW != `M_MODE) || STATUS_MIE; // if M ints enabled or lower priv 3.1.9
assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) || STATUS_SIE; // if S ints enabled or lower priv 3.1.9
assign PendingIntsM = ((MIP_REGW & MIE_REGW) & ({12{MIntGlobalEnM}} & 12'h888)) | ((SIP_REGW & SIE_REGW) & ({12{SIntGlobalEnM}} & 12'h222));
- assign InterruptM = (|PendingIntsM) & InstrValidM & ~CommittedM;
+ assign PendingInterruptM = (|PendingIntsM) & InstrValidM;
+ assign InterruptM = PendingInterruptM & ~CommittedM;
+ assign ExceptionM = BusTrapM | NonBusTrapM;
+
// interrupt if any sources are pending
// & with a M stage valid bit to avoid interrupts from interrupt a nonexistent flushed instruction (in the M stage)
// & with ~CommittedM to make sure MEPC isn't chosen so as to rerun the same instr twice
diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv
index 55c8959f4..e0337bc39 100644
--- a/wally-pipelined/src/wally/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wally/wallypipelinedhart.sv
@@ -161,6 +161,8 @@ module wallypipelinedhart
logic InstrAccessFaultF;
logic [2:0] DCtoAHBSizeM;
+ logic ExceptionM;
+ logic PendingInterruptM;
ifu ifu(.InstrInF(InstrRData),
@@ -179,7 +181,9 @@ module wallypipelinedhart
.MemRWM(MemRWM),
.Funct3M(Funct3M),
.Funct7M(InstrM[31:25]),
- .AtomicM(AtomicM),
+ .AtomicM(AtomicM),
+ .ExceptionM(ExceptionM),
+ .PendingInterruptM(PendingInterruptM),
.CommittedM(CommittedM),
.SquashSCW(SquashSCW),
.DataMisalignedM(DataMisalignedM),