Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main

addins/riscv-arch-test

@@ -1 +1 @@
-Subproject commit be67c99bd461742aa1c100bcc0732657faae2230
+Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86

wally-pipelined/config/rv32ic/wally-config.vh

@@ -40,7 +40,7 @@
 `define IEEE754 0
 
 `define MISA (32'h00000104)
-`define ZICSR_SUPPORTED 0
+`define ZICSR_SUPPORTED 1
 `define ZIFENCEI_SUPPORTED 0
 `define COUNTERS 32
 `define ZICOUNTERS_SUPPORTED 0

wally-pipelined/regression/sim-wally-batch

@@ -1,3 +1,3 @@
 vsim -c <<!
-do wally-pipelined-batch.do rv32ic arch32c
+do wally-pipelined-batch.do rv32ic arch32i
 !

wally-pipelined/src/privileged/csrm.sv

@@ -89,9 +89,35 @@ module csrm #(parameter
   logic            WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM;
   logic            WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM;
   logic            WriteMCOUNTERENM, WriteMCOUNTINHIBITM;
-  logic [`PMP_ENTRIES-1:0] WritePMPCFGM;
+
-  logic [`PMP_ENTRIES-1:0] WritePMPADDRM ; 
+ // There are PMP_ENTRIES = 0, 16, or 64 PMPADDR registers, each of which has its own flop
-  logic [`PMP_ENTRIES-1:0] ADDRLocked, CFGLocked;
+  genvar i;
+  generate
+    if (`PMP_ENTRIES > 0) begin:pmp
+      logic [`PMP_ENTRIES-1:0] WritePMPCFGM;
+      logic [`PMP_ENTRIES-1:0] WritePMPADDRM ; 
+      logic [`PMP_ENTRIES-1:0] ADDRLocked, CFGLocked;
+      for(i=0; i<`PMP_ENTRIES; i++) begin
+        // when the lock bit is set, don't allow writes to the PMPCFG or PMPADDR
+        // also, when the lock bit of the next entry is set and the next entry is TOR, don't allow writes to this entry PMPADDR
+        assign CFGLocked[i] = PMPCFG_ARRAY_REGW[i][7];
+        if (i == `PMP_ENTRIES-1) 
+          assign ADDRLocked[i] = PMPCFG_ARRAY_REGW[i][7];
+        else
+          assign ADDRLocked[i] = PMPCFG_ARRAY_REGW[i][7] | (PMPCFG_ARRAY_REGW[i+1][7] & PMPCFG_ARRAY_REGW[i+1][4:3] == 2'b01);
+        
+        assign WritePMPADDRM[i] = (CSRMWriteM & (CSRAdrM == (PMPADDR0+i))) & ~StallW & ~ADDRLocked[i];
+        flopenr #(`XLEN) PMPADDRreg(clk, reset, WritePMPADDRM[i], CSRWriteValM, PMPADDR_ARRAY_REGW[i]);
+        if (`XLEN==64) begin
+          assign WritePMPCFGM[i] = (CSRMWriteM & (CSRAdrM == (PMPCFG0+2*(i/8)))) & ~StallW & ~CFGLocked[i];
+          flopenr #(8) PMPCFGreg(clk, reset, WritePMPCFGM[i], CSRWriteValM[(i%8)*8+7:(i%8)*8], PMPCFG_ARRAY_REGW[i]);
+        end else begin
+          assign WritePMPCFGM[i]  = (CSRMWriteM & (CSRAdrM == (PMPCFG0+i/4))) & ~StallW & ~CFGLocked[i];
+          flopenr #(8) PMPCFGreg(clk, reset, WritePMPCFGM[i], CSRWriteValM[(i%4)*8+7:(i%4)*8], PMPCFG_ARRAY_REGW[i]);
+        end
+      end
+    end
+  endgenerate
 
   localparam MISA_26 = (`MISA) & 32'h03ffffff;
 
@@ -118,7 +144,7 @@ module csrm #(parameter
   // CSRs
   flopenr #(`XLEN) MTVECreg(clk, reset, WriteMTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, MTVEC_REGW); //busybear: changed reset value to 0
   generate
-    if (`S_SUPPORTED | (`U_SUPPORTED & `N_SUPPORTED)) begin // DELEG registers should exist
+    if (`S_SUPPORTED | (`U_SUPPORTED & `N_SUPPORTED)) begin:deleg // DELEG registers should exist
       flopenr #(`XLEN) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM & MEDELEG_MASK /*12'h7FF*/, MEDELEG_REGW);
       flopenr #(`XLEN) MIDELEGreg(clk, reset, WriteMIDELEGM, CSRWriteValM & MIDELEG_MASK /*12'h222*/, MIDELEG_REGW);
     end else begin
@@ -132,43 +158,15 @@ module csrm #(parameter
   flopenr #(`XLEN) MCAUSEreg(clk, reset, WriteMCAUSEM, NextCauseM, MCAUSE_REGW);
   if(`QEMU) assign MTVAL_REGW = `XLEN'b0;
   else flopenr #(`XLEN) MTVALreg(clk, reset, WriteMTVALM, NextMtvalM, MTVAL_REGW);
-  generate
+  generate // *** needs comment about bit 1
-    if (`BUSYBEAR == 1)
+    if (`BUSYBEAR == 1) begin:counters
       flopenr #(32)   MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, {CSRWriteValM[31:2],1'b0,CSRWriteValM[0]}, MCOUNTEREN_REGW);
-    else if (`BUILDROOT == 1)
+    end else  begin:counters
       flopenr #(32)   MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], MCOUNTEREN_REGW);
-    else
+    end
-      flopens #(32)   MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], MCOUNTEREN_REGW);
   endgenerate
   flopenr #(32)   MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], MCOUNTINHIBIT_REGW);
 
-  // There are PMP_ENTRIES = 0, 16, or 64 PMPADDR registers, each of which has its own flop
-
-  // *** need to add support for locked PMPCFG and PMPADR
-  genvar i;
-  generate
-    for(i=0; i<`PMP_ENTRIES; i++) begin
-      // when the lock bit is set, don't allow writes to the PMPCFG or PMPADDR
-      // also, when the lock bit of the next entry is set and the next entry is TOR, don't allow writes to this entry PMPADDR
-      assign CFGLocked[i] = PMPCFG_ARRAY_REGW[i][7];
-      if (i == `PMP_ENTRIES-1) 
-        assign ADDRLocked[i] = PMPCFG_ARRAY_REGW[i][7];
-      else
-        assign ADDRLocked[i] = PMPCFG_ARRAY_REGW[i][7] | (PMPCFG_ARRAY_REGW[i+1][7] & PMPCFG_ARRAY_REGW[i+1][4:3] == 2'b01);
-      
-      assign WritePMPADDRM[i] = (CSRMWriteM & (CSRAdrM == (PMPADDR0+i))) & ~StallW & ~ADDRLocked[i];
-      flopenr #(`XLEN) PMPADDRreg(clk, reset, WritePMPADDRM[i], CSRWriteValM, PMPADDR_ARRAY_REGW[i]);
-      if (`XLEN==64) begin
-        assign WritePMPCFGM[i] = (CSRMWriteM & (CSRAdrM == (PMPCFG0+2*(i/8)))) & ~StallW & ~CFGLocked[i];
-        flopenr #(8) PMPCFGreg(clk, reset, WritePMPCFGM[i], CSRWriteValM[(i%8)*8+7:(i%8)*8], PMPCFG_ARRAY_REGW[i]);
-      end else begin
-        assign WritePMPCFGM[i]  = (CSRMWriteM & (CSRAdrM == (PMPCFG0+i/4))) & ~StallW & ~CFGLocked[i];
-//        assign WritePMPCFGHM[i] = (CSRMWriteM && (CSRAdrM == PMPCFG0+2*i+1)) && ~StallW;
-        flopenr #(8) PMPCFGreg(clk, reset, WritePMPCFGM[i], CSRWriteValM[(i%4)*8+7:(i%4)*8], PMPCFG_ARRAY_REGW[i]);
-//        flopenr #(`XLEN) PMPCFGHreg(clk, reset, WritePMPCFGHM[i], CSRWriteValM, PMPCFG_ARRAY_REGW[i][63:32]);
-      end
-    end
-  endgenerate
 
   // Read machine mode CSRs
   // verilator lint_off WIDTH
@@ -188,10 +186,6 @@ module csrm #(parameter
         entry = (CSRAdrM - PMPCFG0)*4;
         CSRMReadValM = {PMPCFG_ARRAY_REGW[entry+3],PMPCFG_ARRAY_REGW[entry+2],PMPCFG_ARRAY_REGW[entry+1],PMPCFG_ARRAY_REGW[entry]};
       end
-
-      /*
-      if (~CSRAdrM[0]) CSRMReadValM = {PMPCFG_ARRAY_REGW[]};
-      else             CSRMReadValM = {{(`XLEN-32){1'b0}}, PMPCFG_ARRAY_REGW[(CSRAdrM - PMPCFG0-1)/2][63:32]};*/
     end
     else case (CSRAdrM) 
       MISA_ADR:  CSRMReadValM = MISA_REGW;
@@ -202,8 +196,6 @@ module csrm #(parameter
       MSTATUS:   CSRMReadValM = MSTATUS_REGW;
       MSTATUSH:  CSRMReadValM = 0; // flush this out later if MBE and SBE fields are supported
       MTVEC:     CSRMReadValM = MTVEC_REGW;
-      //MEDELEG:   CSRMReadValM = {{(`XLEN-12){1'b0}}, MEDELEG_REGW};
-      //MIDELEG:   CSRMReadValM = {{(`XLEN-12){1'b0}}, MIDELEG_REGW};
       MEDELEG:   CSRMReadValM = MEDELEG_REGW;
       MIDELEG:   CSRMReadValM = MIDELEG_REGW;
       MIP:       CSRMReadValM = {{(`XLEN-12){1'b0}}, MIP_REGW};

wally-pipelined/testbench/testbench-linux.sv

@@ -175,18 +175,18 @@ module testbench();
   `define PC          dut.hart.ifu.pcreg.q
   `define CSR_BASE    dut.hart.priv.priv.csr
   `define HPMCOUNTER  `CSR_BASE.counters.genblk1.HPMCOUNTER_REGW
-  `define PMP_BASE    `CSR_BASE.csrm.genblk4
+  `define PMP_BASE    `CSR_BASE.csrm.pmp
   `define PMPCFG      genblk2.PMPCFGreg.q
   `define PMPADDR     PMPADDRreg.q
-  `define MEDELEG     `CSR_BASE.csrm.genblk1.MEDELEGreg.q
+  `define MEDELEG     `CSR_BASE.csrm.deleg.MEDELEGreg.q
-  `define MIDELEG     `CSR_BASE.csrm.genblk1.MIDELEGreg.q
+  `define MIDELEG     `CSR_BASE.csrm.deleg.MIDELEGreg.q
   `define MIE         `CSR_BASE.csri.MIE_REGW
   `define MIP         `CSR_BASE.csri.MIP_REGW
   `define MCAUSE      `CSR_BASE.csrm.MCAUSEreg.q
   `define SCAUSE      `CSR_BASE.csrs.genblk1.SCAUSEreg.q
   `define MEPC        `CSR_BASE.csrm.MEPCreg.q
   `define SEPC        `CSR_BASE.csrs.genblk1.SEPCreg.q
-  `define MCOUNTEREN  `CSR_BASE.csrm.genblk3.MCOUNTERENreg.q
+  `define MCOUNTEREN  `CSR_BASE.csrm.counters.MCOUNTERENreg.q
   `define SCOUNTEREN  `CSR_BASE.csrs.genblk1.genblk2.SCOUNTERENreg.q
   `define MSCRATCH    `CSR_BASE.csrm.MSCRATCHreg.q
   `define SSCRATCH    `CSR_BASE.csrs.genblk1.SSCRATCHreg.q

wally-pipelined/testbench/testbench.sv

@@ -81,7 +81,9 @@ logic [3:0] dummy;
       case (TEST)
         "arch64i":                        tests = arch64i;
         "arch64priv":                     tests = arch64priv;
-        "arch64c":      if (`C_SUPPORTED) tests = arch64c;
+        "arch64c":      if (`C_SUPPORTED) 
+                          if (`ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv};
+                          else                  tests = {arch64c};
         "arch64m":      if (`M_SUPPORTED) tests = arch64m;
         "arch64d":      if (`D_SUPPORTED) tests = arch64d;
         "imperas64i":                     tests = imperas64i;
@@ -102,7 +104,9 @@ logic [3:0] dummy;
       case (TEST)
         "arch32i":                        tests = arch32i;
         "arch32priv":                     tests = arch32priv;
-        "arch32c":      if (`C_SUPPORTED) tests = arch32c;
+        "arch32c":      if (`C_SUPPORTED) 
+                          if (`ZICSR_SUPPORTED) tests = {arch32c, arch32cpriv};
+                          else                  tests = {arch32c};
         "arch32m":      if (`M_SUPPORTED) tests = arch32m;
         "arch32f":      if (`F_SUPPORTED) tests = arch32f;
         "imperas32i":                     tests = imperas32i;

wally-pipelined/testbench/tests.vh

@@ -958,7 +958,6 @@ string imperas32f[] = '{
     "rv64i_m/C/candi-01", "4010",
     "rv64i_m/C/cbeqz-01", "4010",
     "rv64i_m/C/cbnez-01", "5010",
-    "rv64i_m/C/cebreak-01", "2070",
     "rv64i_m/C/cj-01", "3010",
     "rv64i_m/C/cjalr-01", "2010",
     "rv64i_m/C/cjr-01", "2010",
@@ -983,6 +982,11 @@ string imperas32f[] = '{
     "rv64i_m/C/cxor-01", "8010"
   };
 
+  string arch64cpriv[] = '{
+//    `RISCVARCHTEST,
+      "rv64i_m/C/cebreak-01", "2070"
+  };
+
   string arch64i[] = '{
     `RISCVARCHTEST,
     "rv64i_m/I/add-01", "9010",
@@ -1405,7 +1409,6 @@ string imperas32f[] = '{
     "rv32i_m/C/candi-01", "3010",
     "rv32i_m/C/cbeqz-01", "3010",
     "rv32i_m/C/cbnez-01", "3010",
-    "rv32i_m/C/cebreak-01", "2050",
     "rv32i_m/C/cj-01", "3010",
     "rv32i_m/C/cjal-01", "3010",
     "rv32i_m/C/cjalr-01", "2010",
@@ -1426,6 +1429,12 @@ string imperas32f[] = '{
     "rv32i_m/C/cxor-01", "4010"
   };
 
+  string arch32cpriv[] = '{
+  //  `RISCVARCHTEST,
+      "rv32i_m/C/cebreak-01", "2050"
+  };      
+
+
   string arch32i[] = '{
     `RISCVARCHTEST,
     "rv32i_m/I/add-01", "5010",