From e0eb91f79521e32c6b6a90b672c9f230937be073 Mon Sep 17 00:00:00 2001
From: David Harris <David_Harris@hmc.edu>
Date: Wed, 6 Mar 2024 11:02:04 -0800
Subject: [PATCH] Changed always @(posedge clk) to always_ff @(posedge clk)
 where it was omitted in several places

---
 src/generic/mem/rom1p1r.sv | 2 +-
 src/privileged/csri.sv     | 4 ++--
 src/uncore/clint_apb.sv    | 4 ++--
 src/uncore/plic_apb.sv     | 2 +-
 src/uncore/uartPC16550D.sv | 2 +-
 5 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv
index 1c6fea356..7350eac9c 100644
--- a/src/generic/mem/rom1p1r.sv
+++ b/src/generic/mem/rom1p1r.sv
@@ -52,7 +52,7 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0)
     end
   end
   
-  always @ (posedge clk) begin
+  always_ff @ (posedge clk) begin
     if(ce) dout <= ROM[addr];
   end
    
diff --git a/src/privileged/csri.sv b/src/privileged/csri.sv
index 35b6f3fe6..fafc5c845 100644
--- a/src/privileged/csri.sv
+++ b/src/privileged/csri.sv
@@ -74,11 +74,11 @@ module csri import cvw::*;  #(parameter cvw_t P) (
     assign SIP_WRITE_MASK = 12'h000;
     assign MIE_WRITE_MASK = 12'h888;
   end
-  always @(posedge clk)
+  always_ff @(posedge clk)
     if (reset)          MIP_REGW_writeable <= 12'b0;
     else if (WriteMIPM) MIP_REGW_writeable <= (CSRWriteValM[11:0] & MIP_WRITE_MASK);
     else if (WriteSIPM) MIP_REGW_writeable <= (CSRWriteValM[11:0] & SIP_WRITE_MASK) | (MIP_REGW_writeable & ~SIP_WRITE_MASK);
-  always @(posedge clk)
+  always_ff @(posedge clk)
     if (reset)          MIE_REGW <= 12'b0;
     else if (WriteMIEM) MIE_REGW <= (CSRWriteValM[11:0] & MIE_WRITE_MASK); // MIE controls M and S fields
     else if (WriteSIEM) MIE_REGW <= (CSRWriteValM[11:0] & 12'h222 & MIDELEG_REGW) | (MIE_REGW & 12'h888); // only S fields
diff --git a/src/uncore/clint_apb.sv b/src/uncore/clint_apb.sv
index 691ba372d..961a50824 100644
--- a/src/uncore/clint_apb.sv
+++ b/src/uncore/clint_apb.sv
@@ -63,7 +63,7 @@ module clint_apb import cvw::*;  #(parameter cvw_t P) (
 
   // register access
   if (P.XLEN==64) begin:clint // 64-bit
-    always @(posedge PCLK) begin
+    always_ff @(posedge PCLK) begin
       case(entry)
         16'h0000: PRDATA <= {63'b0, MSIP};
         16'h4000: PRDATA <= MTIMECMP;
@@ -97,7 +97,7 @@ module clint_apb import cvw::*;  #(parameter cvw_t P) (
             MTIME[j*8 +: 8] <= PWDATA[j*8 +: 8];
       end else MTIME <= MTIME + 1; 
   end else begin:clint // 32-bit
-    always @(posedge PCLK) begin
+    always_ff @(posedge PCLK) begin
       case(entry)
         16'h0000: PRDATA <= {31'b0, MSIP};
         16'h4000: PRDATA <= MTIMECMP[31:0];
diff --git a/src/uncore/plic_apb.sv b/src/uncore/plic_apb.sv
index 130a34e00..7858b2e35 100644
--- a/src/uncore/plic_apb.sv
+++ b/src/uncore/plic_apb.sv
@@ -104,7 +104,7 @@ module plic_apb import cvw::*;  #(parameter cvw_t P) (
   // ==================
   localparam PLIC_NUM_SRC_MIN_32 = P.PLIC_NUM_SRC < 32 ? P.PLIC_NUM_SRC : 31;
     
-  always @(posedge PCLK) begin
+  always_ff @(posedge PCLK) begin
     // resetting
     if (~PRESETn) begin
       intPriority   <= #1 0;
diff --git a/src/uncore/uartPC16550D.sv b/src/uncore/uartPC16550D.sv
index f8aa4e016..555a7682c 100644
--- a/src/uncore/uartPC16550D.sv
+++ b/src/uncore/uartPC16550D.sv
@@ -520,7 +520,7 @@ module uartPC16550D #(parameter UART_PRESCALE) (
       intrpending = 0;
     end
   end
-  always @(posedge PCLK) INTR <= #1 intrpending; // prevent glitches on interrupt pin
+  always_ff @(posedge PCLK) INTR <= #1 intrpending; // prevent glitches on interrupt pin
 
   // Side effect of reading LSR is lowering overrun, parity, framing, break intr's
   assign setSquashRXerrIP = ~MEMRb & (A==3'b101);