diff --git a/pipelined/regression/wave-all.do b/pipelined/regression/wave-all.do index a62db607d..f151680f3 100644 --- a/pipelined/regression/wave-all.do +++ b/pipelined/regression/wave-all.do @@ -487,11 +487,11 @@ add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdM add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdW add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD1D add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD2D -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ExtImmD +add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ImmExtD add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdD add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD1E add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD2E -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ExtImmE +add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ImmExtE add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ForwardedSrcAE add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcAE add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcBE @@ -513,7 +513,7 @@ add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/regf/rd2 add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/regf/i add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ext/InstrD add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ext/ImmSrcD -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ext/ExtImmD +add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ext/ImmExtD add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD1EReg/clk add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD1EReg/reset add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD1EReg/clear @@ -524,11 +524,11 @@ add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD2EReg/reset add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD2EReg/clear add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD2EReg/d add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD2EReg/q -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ExtImmEReg/clk -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ExtImmEReg/reset -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ExtImmEReg/clear -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ExtImmEReg/d -add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ExtImmEReg/q +add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ImmExtEReg/clk +add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ImmExtEReg/reset +add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ImmExtEReg/clear +add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ImmExtEReg/d +add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ImmExtEReg/q add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/Rs1EReg/clk add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/Rs1EReg/reset add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/Rs1EReg/clear diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv index eddb824dd..083d7fdc5 100644 --- a/pipelined/src/ieu/datapath.sv +++ b/pipelined/src/ieu/datapath.sv @@ -71,13 +71,13 @@ module datapath ( // Fetch stage signals // Decode stage signals logic [`XLEN-1:0] R1D, R2D; // Read data from Rs1 (RD1), Rs2 (RD2) - logic [`XLEN-1:0] ExtImmD; // Extended immediate in Decode stage *** According to Figure 4.12, should be ImmExtD + logic [`XLEN-1:0] ImmExtD; // Extended immediate in Decode stage *** According to Figure 4.12, should be ImmExtD logic [4:0] RdD; // Destination register in Decode stage // Execute stage signals logic [`XLEN-1:0] R1E, R2E; // Source operands read from register file - logic [`XLEN-1:0] ExtImmE; // Extended immediate in Execute stage ***According to Figure 4.12, should be ImmExtE + logic [`XLEN-1:0] ImmExtE; // Extended immediate in Execute stage ***According to Figure 4.12, should be ImmExtE logic [`XLEN-1:0] SrcAE, SrcBE; // ALU operands - logic [`XLEN-1:0] ALUResultE, AltResultE, IEUResultE; // ALU result, Alternative result (ExtImmE or PC+4), computed address *** According to Figure 4.12, IEUResultE should be called IEUAdrE + logic [`XLEN-1:0] ALUResultE, AltResultE, IEUResultE; // ALU result, Alternative result (ImmExtE or PC+4), computed address *** According to Figure 4.12, IEUResultE should be called IEUAdrE // Memory stage signals logic [`XLEN-1:0] IEUResultM; // Address computed by ALU *** According to Figure 4.12, IEUResultM should be called IEUAdrM logic [`XLEN-1:0] IFResultM; // Result from either IEU or single-cycle FPU op writing an integer register @@ -93,12 +93,12 @@ module datapath ( assign Rs2D = InstrD[24:20]; assign RdD = InstrD[11:7]; regfile regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, ResultW, R1D, R2D); - extend ext(.InstrD(InstrD[31:7]), .ImmSrcD, .ExtImmD); + extend ext(.InstrD(InstrD[31:7]), .ImmSrcD, .ImmExtD); // Execute stage pipeline register and logic flopenrc #(`XLEN) RD1EReg(clk, reset, FlushE, ~StallE, R1D, R1E); flopenrc #(`XLEN) RD2EReg(clk, reset, FlushE, ~StallE, R2D, R2E); - flopenrc #(`XLEN) ExtImmEReg(clk, reset, FlushE, ~StallE, ExtImmD, ExtImmE); + flopenrc #(`XLEN) ImmExtEReg(clk, reset, FlushE, ~StallE, ImmExtD, ImmExtE); flopenrc #(5) Rs1EReg(clk, reset, FlushE, ~StallE, Rs1D, Rs1E); flopenrc #(5) Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs2E); flopenrc #(5) RdEReg(clk, reset, FlushE, ~StallE, RdD, RdE); @@ -107,9 +107,9 @@ module datapath ( mux3 #(`XLEN) fbemux(R2E, ResultW, IFResultM, ForwardBE, ForwardedSrcBE); comparator_dc_flip #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE); mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE); - mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ExtImmE, ALUSrcBE, SrcBE); + mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE); alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, Funct3E, ALUResultE, IEUAdrE); - mux2 #(`XLEN) altresultmux(ExtImmE, PCLinkE, JumpE, AltResultE); + mux2 #(`XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE); mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE); // Memory stage pipeline register diff --git a/pipelined/src/ieu/extend.sv b/pipelined/src/ieu/extend.sv index e62f977fe..514aeb702 100644 --- a/pipelined/src/ieu/extend.sv +++ b/pipelined/src/ieu/extend.sv @@ -32,25 +32,25 @@ module extend ( input logic [31:7] InstrD, // All instruction bits except opcode (lower 7 bits) input logic [2:0] ImmSrcD, // Select what kind of extension to perform - output logic [`XLEN-1:0 ] ExtImmD); // Extended immediate ***According to Figure 4.12, should be ImmExtD + output logic [`XLEN-1:0 ] ImmExtD); // Extended immediate ***According to Figure 4.12, should be ImmExtD localparam [`XLEN-1:0] undefined = {(`XLEN){1'bx}}; // could change to 0 after debug always_comb case(ImmSrcD) // I-type - 3'b000: ExtImmD = {{(`XLEN-12){InstrD[31]}}, InstrD[31:20]}; + 3'b000: ImmExtD = {{(`XLEN-12){InstrD[31]}}, InstrD[31:20]}; // S-type (stores) - 3'b001: ExtImmD = {{(`XLEN-12){InstrD[31]}}, InstrD[31:25], InstrD[11:7]}; + 3'b001: ImmExtD = {{(`XLEN-12){InstrD[31]}}, InstrD[31:25], InstrD[11:7]}; // B-type (branches) - 3'b010: ExtImmD = {{(`XLEN-12){InstrD[31]}}, InstrD[7], InstrD[30:25], InstrD[11:8], 1'b0}; + 3'b010: ImmExtD = {{(`XLEN-12){InstrD[31]}}, InstrD[7], InstrD[30:25], InstrD[11:8], 1'b0}; // J-type (jal) - 3'b011: ExtImmD = {{(`XLEN-20){InstrD[31]}}, InstrD[19:12], InstrD[20], InstrD[30:21], 1'b0}; + 3'b011: ImmExtD = {{(`XLEN-20){InstrD[31]}}, InstrD[19:12], InstrD[20], InstrD[30:21], 1'b0}; // U-type (lui, auipc) - 3'b100: ExtImmD = {{(`XLEN-31){InstrD[31]}}, InstrD[30:12], 12'b0}; + 3'b100: ImmExtD = {{(`XLEN-31){InstrD[31]}}, InstrD[30:12], 12'b0}; // Store Conditional: zero offset - 3'b101: if (`A_SUPPORTED) ExtImmD = 0; - else ExtImmD = undefined; - default: ExtImmD = undefined; // undefined + 3'b101: if (`A_SUPPORTED) ImmExtD = 0; + else ImmExtD = undefined; + default: ImmExtD = undefined; // undefined endcase endmodule